KR20030001750A - method for manufacturing of semiconductor device - Google Patents
method for manufacturing of semiconductor device Download PDFInfo
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- KR20030001750A KR20030001750A KR1020010037102A KR20010037102A KR20030001750A KR 20030001750 A KR20030001750 A KR 20030001750A KR 1020010037102 A KR1020010037102 A KR 1020010037102A KR 20010037102 A KR20010037102 A KR 20010037102A KR 20030001750 A KR20030001750 A KR 20030001750A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 35
- 238000000034 method Methods 0.000 title claims abstract description 16
- 238000004519 manufacturing process Methods 0.000 title abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 23
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 22
- 239000002184 metal Substances 0.000 claims abstract description 14
- 239000012535 impurity Substances 0.000 claims description 23
- 150000002500 ions Chemical class 0.000 claims description 10
- 229910008486 TiSix Inorganic materials 0.000 claims description 2
- 238000001039 wet etching Methods 0.000 claims description 2
- 150000004767 nitrides Chemical class 0.000 abstract description 8
- 230000009977 dual effect Effects 0.000 abstract description 7
- 238000005530 etching Methods 0.000 abstract description 5
- 229920005591 polysilicon Polymers 0.000 abstract 4
- 239000002019 doping agent Substances 0.000 abstract 2
- 238000002955 isolation Methods 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 230000000873 masking effect Effects 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 239000000779 smoke Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/823842—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823857—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
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- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
본 발명은 반도체 소자의 제조방법에 관한 것으로, 특히 공정 개선과 제품 신뢰성을 향상시키는데 적당한 반도체 소자의 제조방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device suitable for improving the process and product reliability.
이하, 첨부된 도면을 참고하여 종래의 반도체 소자의 제조방법을 설명하면 다음과 같다.Hereinafter, a manufacturing method of a conventional semiconductor device will be described with reference to the accompanying drawings.
도 1a 내지 도 1d는 종래의 반도체 소자의 제조방법을 나타낸 공정단면도이다.1A to 1D are cross-sectional views illustrating a method of manufacturing a conventional semiconductor device.
도 1a에 도시한 바와 같이, 활성 영역과 필드 영역으로 정의된 반도체 기판(11)의 필드 영역을 선택적으로 제거하여 소정 깊이를 갖는 트랜치(trench)를 형성하고, 상기 트랜치의 내부에 절연 물질을 매립하여 소자 격리막(12)을 형성한다.As shown in FIG. 1A, a field region of the semiconductor substrate 11 defined as an active region and a field region is selectively removed to form a trench having a predetermined depth, and an insulating material is embedded in the trench. The device isolation film 12 is formed.
이어, 상기 소자 분리막(12)에 의해 정의된 p-웰 영역과 n-웰 영역에 마스킹 및 불순물 이온주입을 통해 NMOS 및 PMOS 트랜지스터가 형성될 영역을 확정한다,Subsequently, masking and implantation of impurity ions into the p-well region and the n-well region defined by the device isolation layer 12 determine the region where the NMOS and PMOS transistors are to be formed.
도 1b에 도시한 바와 같이, 상기 반도체 기판(11)의 전면에 게이트 산화막(13), 불순물이 주입되지 않는 다결정 실리콘막(14)을 차례로 증착하고, NMOS 영역에는 N형 불순물(Phosphorus), PMOS 영역에는 P형 불순물(Boron)을 각각 주입하여 듀얼 폴리를 형성한다.As shown in FIG. 1B, a gate oxide film 13 and a polycrystalline silicon film 14 into which impurities are not implanted are sequentially deposited on the entire surface of the semiconductor substrate 11, and N-type impurities (Phosphorus) and PMOS are deposited in the NMOS region. P-type impurities (Boron) are implanted into the region to form dual poly.
도 1c에 도시한 바와 같이, 상기 다결정 실리콘막(14)상에 게이트 금속층(15), 질화막(16)을 차례로 증착하고, 게이트가 형성되는 부분을 감광막으로 패터닝한 후 감광막을 마스크로 사용하여 트랜지스터가 형성되는 부분 이외의 질화막(16), 게이트 금속층(15) 및 다결정 실리콘막(14), 게이트 산화막(13)을 선택적으로 건식 식각하여 게이트 전극(17)을 형성한다.As shown in FIG. 1C, a gate metal layer 15 and a nitride film 16 are sequentially deposited on the polycrystalline silicon film 14, and a portion where the gate is formed is patterned with a photoresist film, and then the photoresist film is used as a mask. The gate electrode 17 is formed by selectively dry etching the nitride film 16, the gate metal layer 15, the polycrystalline silicon film 14, and the gate oxide film 13 except for the portion where the is formed.
도 1d에 도시한 바와 같이, 상기 게이트 전극(17) 양측의 반도체 기판(11)표면내에 선택적으로 저농도 n형 및 p형 불순물 이온을 주입하여 LDD(Lightly Doped Drain) 영역(18)을 형성한다.As shown in FIG. 1D, lightly doped drain (LDD) regions 18 are formed by selectively implanting low concentration n-type and p-type impurity ions into the surface of the semiconductor substrate 11 on both sides of the gate electrode 17.
이어, 상기 게이트 전극(17)을 포함한 반도체 기판(11)의 전면에 절연막을 형성한 후 에치백 공정을 실시하여 상기 게이트 전극(17)의 양측면에 절연막 측벽(19)을 형성한다.Subsequently, an insulating film is formed on the entire surface of the semiconductor substrate 11 including the gate electrode 17, and then an etch back process is performed to form insulating film sidewalls 19 on both sides of the gate electrode 17.
그리고 상기 게이트 전극(17) 및 절연막 측벽(19)을 마스크로 이용하여 고농도 n형 및 p형 불순물 이온을 선택적으로 주입하여 상기 LDD 영역(18)과 연결되는 소오스/드레인 불순물 영역(20)을 형성함으로서 종래의 CMOS 소자를 완성한다.In addition, high concentration n-type and p-type impurity ions are selectively implanted using the gate electrode 17 and the insulating layer sidewall 19 as a mask to form a source / drain impurity region 20 connected to the LDD region 18. This completes the conventional CMOS device.
그러나 상기와 같은 종래의 반도체 소자의 제조방법에 있어서 다음과 같은 문제점이 있었다.However, in the conventional method of manufacturing a semiconductor device as described above has the following problems.
즉, PMOS 및 NMOS 트랜지스터에 동일한 두께를 갖는 게이트 산화막을 사용함으로서 PMOS 지역에서 보론 침투 문제 및 게이트 형성을 위한 다결정 실리콘막 시각시 NMOS 영역과 PMOS 영역의 폴리 도핑이 다른 물질로 이루어져 있기 때문에 식각율이 달라 잔류물이 남거나 반도체 기판이 손상된다.That is, by using the gate oxide film having the same thickness for the PMOS and NMOS transistors, the etching rate is low because the poly-doped NMOS region and PMOS region are made of different materials during boron penetration problem and polycrystalline silicon film for gate formation in PMOS region. This leaves residue or damages the semiconductor substrate.
본 발명은 상기와 같은 종래의 문제점을 해결하기 위해 안출한 것으로 듀얼 게이트 절연막 공정을 적용하여 듀얼 게이트 형성시 균일한 폴리 에치를 행함으로서 공정 개선과 제품 신뢰성을 향상시키도록 한 반도체 소자의 제조방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the conventional problems as described above, and a method of manufacturing a semiconductor device to improve the process and improve product reliability by performing a uniform poly etch when forming a dual gate by applying a dual gate insulating film process. The purpose is to provide.
도 1a 내지 도 1d는 종래의 반도체 소자의 제조방법을 나타낸 공정단면도1A to 1D are cross-sectional views illustrating a method of manufacturing a conventional semiconductor device.
도 2a 내지 도 2e는 본 발명에 의한 반도체 소자의 제조방법을 나타낸 공정단면도2A through 2E are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the present invention.
도면의 주요 부분에 대한 부호의 설명Explanation of symbols for the main parts of the drawings
21 : 반도체 기판 22 : 소자 격리막21 semiconductor substrate 22 device isolation film
23 : 제 1 게이트 절연막 24 : 제 2 게이트 절연막23: first gate insulating film 24: second gate insulating film
25 : 다결정 실리콘막 26 : 산화막25 polycrystalline silicon film 26 oxide film
27 : 게이트 금속층 28 : 질화막27 gate metal layer 28 nitride film
29 : 게이트 전극 30 : LDD 영역29 gate electrode 30 LDD region
31 : 절연막 측벽 32 : 소오스/드레인 불순물 영역31 sidewall of insulating film 32 source / drain impurity region
상기와 같은 목적을 달성하기 위한 본 발명에 의한 반도체 소자의 제조방법은 반도체 기판에 NMOS 및 PMOS 트랜지스터가 형성될 영역을 정의하는 단계와, 상기 NMOS 영역과 PMOS 영역에 각각 p형 및 n형 분순물 이온을 주입하는 단계와, 상기 NMOS 영역과 PMOS 영역의 반도체 기판상에 서로 다른 두께를 갖는 게이트 절연막을 형성하는 단계와, 상기 반도체 기판의 전면에 언도우프트 다결정 실리콘막 및 산화막을 차례로 형성하는 단계와, 상기 산화막을 선택적으로 제거하여 게이트 영역을 정의하는 단계와, 상기 게이트가 형성될 다결정 실리콘막에 p형 및 n형 불순물 이온을 선택적으로 주입하는 단계와, 상기 산화막을 제거하고 다결정 실리콘막상에 게이트 금속층 및 절연막을 차례로 형성하는 단계와, 상기 절연막, 게이트 금속층, 다결정 실리콘막, 게이트 절연막을 선택적으로 제거하여 게이트 전극을 형성하는 단계와, 상기 게이트 전극 양측의 반도체 기판 표면내에 소오스/드레인 불순물 영역을 형성하는 단계를 포함하여 형성함을 특징으로 한다.According to an aspect of the present invention, there is provided a method of fabricating a semiconductor device, the method including: defining a region in which an NMOS and a PMOS transistor are to be formed in a semiconductor substrate, and p-type and n-type impurities in the NMOS region and the PMOS region, respectively Implanting ions, forming a gate insulating film having a different thickness on the semiconductor substrates of the NMOS region and the PMOS region, and sequentially forming an undoped polycrystalline silicon film and an oxide film on the entire surface of the semiconductor substrate. And selectively removing the oxide film to define a gate region, selectively implanting p-type and n-type impurity ions into the polycrystalline silicon film on which the gate is to be formed, and removing the oxide film on the polycrystalline silicon film. Forming a gate metal layer and an insulating film in sequence, and forming the insulating film, the gate metal layer, a polycrystalline silicon film, and a gate section. And selectively removing the smoke layer to form a gate electrode, and forming a source / drain impurity region in a surface of the semiconductor substrate on both sides of the gate electrode.
이하, 첨부된 도면을 참고하여 본 발명에 의한 반도체 소자의 제조방법을 상세히 설명하면 다음과 같다.Hereinafter, a method of manufacturing a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2e는 본 발명에 의한 반도체 소자의 제조방법을 나타낸 공정단면도이다.2A to 2E are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the present invention.
도 2a에 도시한 바와 같이, 활성 영역과 필드 영역으로 정의된 반도체 기판(21)의 필드 영역을 선택적으로 제거하여 소정 깊이를 갖는 트랜치(trench)를 형성하고, 상기 트랜치의 내부에 절연 물질을 매립하여 소자 격리막(22)을 형성한다.As shown in FIG. 2A, a trench having a predetermined depth is formed by selectively removing a field region of the semiconductor substrate 21 defined as an active region and a field region, and filling an insulating material in the trench. The device isolation film 22 is formed.
이어, 상기 소자 분리막(22)에 의해 정의된 p-웰 영역과 n-웰 영역에 마스킹 및 불순물 이온주입을 통해 NMOS 및 PMOS 트랜지스터가 형성될 영역을 확정한다,Subsequently, masking and implantation of impurity ions into the p-well region and the n-well region defined by the device isolation layer 22 determine the region where the NMOS and PMOS transistors are to be formed.
그리고 상기 반도체 기판(21)상에 제 1 게이트 절연막(23)을 형성한다.A first gate insulating film 23 is formed on the semiconductor substrate 21.
도 2b에 도시한 바와 같이, 포토 및 식각 공정을 통해 상기 NMOS 영역의 제 1 게이트 절연막(23)을 선택적으로 제거한다.As shown in FIG. 2B, the first gate insulating layer 23 of the NMOS region is selectively removed through a photo and etching process.
이어, 상기 반도체 기판(21)의 전면에 제 2 게이트 절연막(24)을 형성한다.Next, a second gate insulating film 24 is formed on the entire surface of the semiconductor substrate 21.
이때 PMOS 영역에도 제 1 게이트 절연막(23)이 잔류하고 있어 제 2 게이트 절연막(24)이 그 위에 형성됨으로 NMOS 영역에 형성되는 제 2 게이트 절연막(24)보다 두꺼운 게이트 절연막이 형성된다.At this time, the first gate insulating film 23 remains in the PMOS region, and the second gate insulating film 24 is formed thereon, thereby forming a gate insulating film thicker than the second gate insulating film 24 formed in the NMOS region.
도 2c에 도시한 바와 같이, 상기 반도체 기판(21)의 전면에 불순물이 주입되지 않는 다결정 실리콘막(25) 및 산화막(26)을 차례로 증착하고, 포토 및 식각 공정을 통해 상기 산화막(26)을 선택적으로 제거하여 게이트 영역을 정의한다.As shown in FIG. 2C, the polycrystalline silicon film 25 and the oxide film 26 to which impurities are not implanted are sequentially deposited on the entire surface of the semiconductor substrate 21, and the oxide film 26 is formed through photo and etching processes. Selectively remove to define the gate area.
이어, 상기 선택적으로 제거된 산화막(26)을 마스크로 이용하여 노출된 다결정 실리콘막(25)의 NMOS 영역에는 N형 불순물(Phosphorus), PMOS 트랜지스터 영역에는 P형 불순물(Boron)을 각각 주입한다.Subsequently, N-type impurities (Phosphorus) are injected into the NMOS region and P-type impurities (Boron) are injected into the PMOS transistor region, respectively, using the selectively removed oxide film 26 as a mask.
도 2d에 도시한 바와 같이, 상기 산화막(26)을 습식 식각(wet etch)으로 제거하고, 상기 다결정 실리콘막(25)상에 게이트 금속층(27) 및 질화막(28)을 차례로 증착한다.As shown in FIG. 2D, the oxide layer 26 is removed by wet etching, and a gate metal layer 27 and a nitride layer 28 are sequentially deposited on the polycrystalline silicon layer 25.
여기서 상기 게이트 금속층(27)은 WSi, TiSix 및 W 등을 사용하고, 상기 게이트 금속층(27)상에 형성되는 질화막(28) 대신에 산화막, 산화 질화막 등을 사용할 수도 있다.The gate metal layer 27 may be formed of WSi, TiSix, W, or the like, and an oxide film, an oxynitride film, or the like may be used instead of the nitride film 28 formed on the gate metal layer 27.
이어, 게이트가 형성되는 부분을 감광막으로 패터닝한 후 감광막을 마스크로 사용하여 질화막(28), 게이트 금속층(27) 및 다결정 실리콘막(25), 제 1, 제 2 게이트 절연막(23,24)을 선택적으로 건식 식각하여 게이트 전극(29)을 형성한다.Subsequently, after the gate is patterned with the photoresist layer, the nitride layer 28, the gate metal layer 27, the polycrystalline silicon layer 25, and the first and second gate insulating layers 23 and 24 are formed using the photoresist layer as a mask. Selectively dry etching to form the gate electrode 29.
도 2e에 도시한 바와 같이, 상기 게이트 전극(29) 양측의 반도체 기판(21) 표면내에 선택적으로 저농도 n형 및 p형 불순물 이온을 주입하여 LDD(Lightly Doped Drain) 영역(30)을 형성한다.As shown in FIG. 2E, lightly doped drain (LDD) regions 30 are formed by selectively implanting low concentration n-type and p-type impurity ions into the surface of the semiconductor substrate 21 on both sides of the gate electrode 29.
이어, 상기 게이트 전극(29)을 포함한 반도체 기판(21)의 전면에 절연막을 형성한 후 에치백 공정을 실시하여 상기 게이트 전극(29)의 양측면에 절연막 측벽(31)을 형성한다.Subsequently, an insulating film is formed on the entire surface of the semiconductor substrate 21 including the gate electrode 29 and an etch back process is performed to form insulating film sidewalls 31 on both sides of the gate electrode 29.
그리고 상기 게이트 전극(29) 및 절연막 측벽(31)을 마스크로 이용하여 고농도 n형 및 p형 불순물 이온을 선택적으로 주입하여 상기 LDD 영역(30)과 연결되는 소오스/드레인 불순물 영역(32)을 형성함으로서 본 발명에 의한 CMOS 소자를 완성한다.A high concentration of n-type and p-type impurity ions are selectively implanted using the gate electrode 29 and the insulating film sidewall 31 as a mask to form a source / drain impurity region 32 connected to the LDD region 30. This completes the CMOS device according to the present invention.
이상에서 설명한 바와 같이 본 발명에 의한 반도체 소자의 제조방법은 다음과 같은 효과가 있다.As described above, the method for manufacturing a semiconductor device according to the present invention has the following effects.
첫째, 듀얼 게이트 절연막을 적용하여 CMOS 소자와 같은 듀얼 게이트 형성시 안정적으로 불순물이 도핑되지 않은 다결정 실리콘막의 불순물 이온의 도핑 증가 및 열처리 추가를 실행할 수 있다.First, by applying the dual gate insulating film, it is possible to increase the doping of the impurity ions of the polycrystalline silicon film that is not doped with impurities stably and to add heat treatment when forming a dual gate such as a CMOS device.
둘째, NMOS 및 PMOS 트랜지스터 영역의 게이트 산화막을 각각 다르게 형성하여 소자의 신뢰성을 향상시킬 수 있다.Second, the gate oxide films of the NMOS and PMOS transistor regions may be formed differently to improve the reliability of the device.
셋째, 다결정 실리콘막에 베리어 산화막을 형성한 후 패터닝하여 게이트를 형성할 때 식각할 부분만 도핑되지 않도록 함으로서 식각율이 달라 폴리 잔류물이 남거나 기판이 손상되는 것을 방지할 수 있다.Third, when the barrier oxide film is formed on the polycrystalline silicon film and patterned, only the portion to be etched is formed when the gate is formed to prevent the poly residue or the substrate from being damaged due to different etching rates.
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| KR100763710B1 (en) * | 2006-08-31 | 2007-10-04 | 동부일렉트로닉스 주식회사 | Method for forming dual gate of semiconductor device and structure of dual gate |
| KR100840684B1 (en) * | 2001-10-29 | 2008-06-24 | 매그나칩 반도체 유한회사 | method for manufacturing of semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100840684B1 (en) * | 2001-10-29 | 2008-06-24 | 매그나칩 반도체 유한회사 | method for manufacturing of semiconductor device |
| KR100763710B1 (en) * | 2006-08-31 | 2007-10-04 | 동부일렉트로닉스 주식회사 | Method for forming dual gate of semiconductor device and structure of dual gate |
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