CN102332398B - Method for manufacturing two high-K gate dielectric/metal gate structures - Google Patents
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Abstract
The invention provides a method for manufacturing two high-K gate dielectric/metal gate structures, which comprises the following steps of: providing a semiconductor substrate with shallow trench isolation (STI), forming a first covering layer, a first high-K dielectric layer, a first metal gate material layer and a first polycrystalline silicon layer on the semiconductor substrate and the STI in turn, and etching the four layers to expose a part of semiconductor substrate and a part of first covering layer; forming a second covering layer, a second high-K dielectric layer, a second metal gate material layer and a second polycrystalline silicon layer on the residual layers in turn; removing the second covering layer, the second high-K dielectric layer, the second metal gate material layer and the second polycrystalline silicon layer which cover the first polycrystalline silicon layer in turn; removing the layers which cover the STI in turn; and forming the high-K gate dielectric/metal gate structures on two sides of the STI. By the manufacturing method, the STI is prevented from being damaged, a short circuit caused by the damage of the STI is further avoided, and product yield is improved.
Description
Technical field
The present invention relates to the manufacturing technology field of semiconductor integrated circuit, relate in particular to the manufacture method of a kind of pair of high-K gate dielectric/metal-gate structures.
Background technology
The integrated circuit especially main devices in the very lagre scale integrated circuit (VLSIC) is metal-oxide semiconductor fieldeffect transistor (metal oxide semiconductor field effect transistor is called for short MOS transistor).Since metal-oxide-semiconductor was invented, its physical dimension was constantly being dwindled always, and its characteristic size has got into the 45nm scope at present.Under this size situation, basic restriction and technological challenge begin to occur, device size further dwindle the more and more difficult that just becomes.Wherein, in the preparation of MOS transistor device and circuit, tool is challenging to be that the traditional cmos device is in the process of dwindling, because the thickness of gate oxide medium reduces to bring high grid Leakage Current in polysilicon/SiO2 structure or the polysilicon/SiCN structure.
For this reason, the solution that has proposed is to adopt metal gate and high-k (K) gate medium to substitute traditional heavily doped polysilicon grid and SiO2 (or SiON) gate medium.In order to reach adjustment NMOS and the PMOS needs of work function separately; The formation method of metal gate and high K medium is divided into a variety of; Corresponding multiple formation structure has the two high K mediums (DMDD) of bimetal gate, the two high K mediums (SMDD) of monometallic grid, bimetal gate list high K medium structures such as (DMSD).Wherein using is DMDD more widely; With reference to Figure 1A～1C; Have shallow trench isolation at first the deposit first high K medium layer 12, the first metal gate material layer 13 and first polysilicon layer 14 on 11 the Semiconductor substrate 10; Optionally carry out etching then; Make the remaining first high K medium layer 12, the first metal gate material layer 13 and first polysilicon layer 14 cover a part of Semiconductor substrate 10; Afterwards at first polysilicon layer 14, shallow trench isolation from 11 and Semiconductor substrate 10 surfaces that are not capped the deposit second high K medium layer 12 ', the second metal gate material layer 13 ' and second polysilicon layer 14 ' successively, vertically highly bigger owing to the second high K medium layer 12 ' that covers the first high K medium layer 12, the first metal gate material layer 13 and first polysilicon layer, 14 sides and the second metal gate material layer 13 ', therefore; Form in the process of first high-K gate dielectric/metal-gate structures and second high-K gate dielectric/metal-gate structures in the later stage etching; The etching effect that this vertical effect of altitude is whole makes other vertically highly less etched portions early accomplish etching, and therefore sustains damage 15 easily at vertically highly less infratectal shallow trench isolation from 11; Serious meeting causes shallow trench isolation to leave 11 inefficacy, forms short circuit; Even without serious loss, also the process window to wet method and dry etching has very big restriction, has increased technology difficulty.
Summary of the invention
Technical problem to be solved by this invention has provided the manufacture method of a kind of pair of high-K gate dielectric/metal-gate structures, is isolated in the problem that sustains damage easily in the process of etching to solve shallow trench.
In order to solve the problems of the technologies described above; Technical scheme of the present invention is: the manufacture method that a kind of pair of high-K gate dielectric/metal-gate structures is provided; Comprise: provide to have the Semiconductor substrate that shallow trench isolation leaves; Leave at said Semiconductor substrate and said shallow trench isolation and to form first cover layer, the first high K dielectric layer, the first metal gate material layer and first polysilicon layer successively; Said first cover layer of etching, the said first high K dielectric layer, the said first metal gate material layer and said first polysilicon layer, said first cover layer of said Semiconductor substrate of exposed portions serve and part, and said first cover layer of the part of exposing covers said shallow trench isolation and leaves; Forming second cover layer, the second high K dielectric layer, the second metal gate material layer and second polysilicon layer successively on remaining first polysilicon layer, said first cover layer that exposes and on the said Semiconductor substrate of exposing; Remove and cover said second cover layer, the said second high K dielectric layer, the said second metal gate material layer and said second polysilicon layer on said first polysilicon layer successively; Remove and cover said shallow trench isolation successively from last said first cover layer, said second cover layer, the said second high K dielectric layer, the said second metal gate material layer and second polysilicon layer; Form first high-K gate dielectric/metal-gate structures and second high-K gate dielectric/metal-gate structures respectively in the both sides that said shallow trench isolation leaves.
Further; Utilize photoetching and etching technics to remove and cover said second cover layer, the said second high K dielectric layer, the said second metal gate material layer and said second polysilicon layer on said first polysilicon layer successively, keep said second cover layer, the said second high K dielectric layer, the said second metal gate material layer and said second polysilicon layer that cover the said first polysilicon layer side successively.
Further, utilize photoetching and etching technics to remove and cover said shallow trench isolation successively from last said first cover layer, said second cover layer, the said second high K dielectric layer, the said second metal gate material layer and second polysilicon layer.
Further, be formed with first silicon oxide layer between said first cover layer and the said Semiconductor substrate, be formed with second silicon oxide layer between said second cover layer and the said Semiconductor substrate.
Further, the said first tectal material is a lanthana.
Further, the said second tectal material is a lanthana.
Further, the said first tectal thickness is 10nm～50nm.
Further, the said second tectal thickness is 10nm～50nm.
Further, the material of the said first metal gate material layer is a titanium nitride.
Further, the material of the said second metal gate material layer is a tantalum nitride.
Further, the material of said first polysilicon layer and said second polysilicon layer is polysilicon.
Further; Remove and cover said shallow trench isolation successively after last said first cover layer, said second cover layer, the said second high K dielectric layer, the said second metal gate material layer and second polysilicon layer; Deposit spathic silicon cap layer utilizes photoetching and etching technics to form said first high-K gate dielectric/metal-gate structures and said second high-K gate dielectric/metal-gate structures.
The manufacture method of provided by the invention pair of high-K gate dielectric/metal-gate structures; Cover shallow trench isolation successively from last first cover layer and second cover layer; Can avoid shallow trench isolation from sustaining damage as etching barrier layer; Further avoided because the short circuit that the shallow trench isolation damage causes has improved the product yield.
Description of drawings
Figure 1A～1C is the pairing cross-sectional view of manufacture method of two high-K gate dielectric/metal-gate structures in the prior art;
Fig. 2 is the flow chart of steps of the manufacture method of two high-K gate dielectric/metal-gate structures of providing of the embodiment of the invention;
Fig. 3 A～3F is the pairing cross-sectional view of manufacture method of two high-K gate dielectric/metal-gate structures of providing of the embodiment of the invention.
Embodiment
Below in conjunction with accompanying drawing and specific embodiment the manufacture method of a kind of pair of high-K gate dielectric/metal-gate structures of the present invention's proposition is done further explain.According to following explanation and claims, advantage of the present invention and characteristic will be clearer.What need explanation is, accompanying drawing all adopts the form of simplifying very much and all uses non-ratio accurately, only is used for conveniently, the purpose of the aid illustration embodiment of the invention lucidly.
Core concept of the present invention is; The manufacture method of the two high-K gate dielectric/metal-gate structures that provide; Cover shallow trench isolation successively from last first cover layer and second cover layer; Can avoid shallow trench isolation from sustaining damage as etching barrier layer, further avoid because the short circuit that the shallow trench isolation damage causes has improved the product yield.
Fig. 2 is the flow chart of steps of the manufacture method of two high-K gate dielectric/metal-gate structures of providing of the embodiment of the invention.With reference to Fig. 2, the manufacture method of a kind of pair of high-K gate dielectric/metal-gate structures that provides comprises:
S21, provide and have the Semiconductor substrate that shallow trench isolation leaves; Leave at said Semiconductor substrate and said shallow trench isolation and to form first cover layer, the first high K dielectric layer, the first metal gate material layer and first polysilicon layer successively; Said first cover layer of etching, the said first high K dielectric layer, the said first metal gate material layer and said first polysilicon layer; Said first cover layer of said Semiconductor substrate of exposed portions serve and part, and said first cover layer of the part of exposing covers said shallow trench isolation and leaves;
S22, forming second cover layer, the second high K dielectric layer, the second metal gate material layer and second polysilicon layer successively on remaining first polysilicon layer, said first cover layer that exposes and on the said Semiconductor substrate of exposing;
S23, removal cover said second cover layer, the said second high K dielectric layer, the said second metal gate material layer and said second polysilicon layer on said first polysilicon layer successively;
S24, removal cover said shallow trench isolation successively from last said first cover layer, said second cover layer, the said second high K dielectric layer, the said second metal gate material layer and second polysilicon layer;
S25, form first high-K gate dielectric/metal-gate structures and second high-K gate dielectric/metal-gate structures respectively in the both sides that said shallow trench isolation leaves.
To combine cross-sectional view that the manufacture method of of the present invention pair of high-K gate dielectric/metal-gate structures is described in more detail below; The preferred embodiments of the present invention have wherein been represented; Should be appreciated that those skilled in the art can revise the present invention described here, and still realize advantageous effects of the present invention.
Fig. 3 A～3F is the pairing cross-sectional view of manufacture method of two high-K gate dielectric/metal-gate structures of providing of the embodiment of the invention.With reference to Fig. 3 A and integrating step S21; Provide and have shallow trench isolation from 31 Semiconductor substrate 30; On 31, form the high K dielectric layer of first cover layer 38, first 32, the first metal gate material layer 33 and first polysilicon layer 34 successively at said Semiconductor substrate 30 and said shallow trench isolation; The high K dielectric layer of said first cover layer 38, said first of etching 32, the said first metal gate material layer 33 and said first polysilicon layer 34; Said Semiconductor substrate 30 of exposed portions serve and said first cover layer 38 of part, and said first cover layer 38 of the part of exposing covers said shallow trench isolation from 31.
With reference to Fig. 3 B and integrating step S22, forming the high K dielectric layer of second cover layer 38 ', second 32 ', the second metal gate material layer 33 ' and second polysilicon layer 34 ' on remaining first polysilicon layer 34, said first cover layer 38 that exposes and on the said Semiconductor substrate of exposing 30 successively.
With reference to Fig. 3 C and integrating step S23; Utilize photoetching and etching technics to remove to cover successively the high K dielectric layer of said second cover layer 38 ', said second on said first polysilicon layer 34 32 ', the said second metal gate material layer 33 ' and said second polysilicon layer 34 ', keep the high K dielectric layer of said second cover layer 38, said second that covers said first polysilicon layer, 34 sides successively 32 ', the said second metal gate material layer 33 ' and said second polysilicon layer 34 '.
With reference to Fig. 3 D and integrating step S24; Adopt photoetching and etching technics to remove to cover successively the high K dielectric layer of said first cover layer 38 of said shallow trench isolation on 31, said second cover layer 38 ', said second 32, the said second metal gate material layer 33 ' and second polysilicon layer 34 ', to form groove 37.In the present embodiment; The thickness of first cover layer 38 is 10nm～50nm; The thickness of second cover layer 38 ' is 10nm～50nm, and the material of first cover layer 38 and second cover layer 38 ' is lanthana, and first cover layer 38 and second cover layer 38 ' can be avoided shallow trench isolation to leave 31 as etching barrier layer sustaining damage; Further avoided because shallow trench isolation from the short circuit that 31 damages cause, has improved the product yield.Will be understood by those skilled in the art that the material of said first cover layer 38 and second cover layer 38 ' not only is confined to lanthana, can also be such as materials such as holimium oxides.
With reference to Fig. 3 E, Fig. 3 F and integrating step S25; Deposit spathic silicon cap layer 35 on first polysilicon layer 34 and second polysilicon layer 34 ' and in the groove 37 utilizes photoetching and etching technics to form first high-K gate dielectric/metal-gate structures 36 and second high-K gate dielectric/metal-gate structures 36 ' at said shallow trench isolation from 31 both sides.
In the present embodiment, the material of the said first metal gate material layer 33 is titanium nitrides, and the material of the said second metal gate material layer 33 ' is a tantalum nitride, and the material of said first polysilicon layer 34 and said second polysilicon layer 34 ' is polysilicon.
Further; Be formed with first silicon oxide layer between the said first high K dielectric layer 32 and the said Semiconductor substrate 30; Be formed with second silicon oxide layer between the said second high K dielectric layer 32 ' and the said Semiconductor substrate 30, in the present embodiment, said first silicon oxide layer and said second silicon oxide layer be not shown in the drawings; But said first silicon oxide layer and said second silicon oxide layer exist, and those of ordinary skills should know knowledge.First silicon oxide layer makes that the adhesiveness between the said first high K dielectric layer 32 and the said Semiconductor substrate 30 is better, and second silicon oxide layer makes that the adhesiveness between the said second high K dielectric layer 32 ' and the said Semiconductor substrate 30 is better.And first cover layer 38 on first silicon oxide layer can prevent the first high K dielectric layer 32 to the diffusion of first silicon oxide layer, and second cover layer 38 ' on second silicon oxide layer can prevent that the second high K dielectric layer 32 ' from spreading to second silicon oxide layer.
Obviously, those skilled in the art can carry out various changes and modification to invention and not break away from the spirit and scope of the present invention.Like this, belong within the scope of claim of the present invention and equivalent technologies thereof if of the present invention these are revised with modification, then the present invention also is intended to comprise these changes and modification interior.
Claims (12)
1. the manufacture method of two high-K gate dielectric/metal-gate structures is characterized in that, comprising:
Provide and have the Semiconductor substrate that shallow trench isolation leaves; Leave at said Semiconductor substrate and said shallow trench isolation and to form first cover layer, the first high K dielectric layer, the first metal gate material layer and first polysilicon layer successively; Said first cover layer of etching, the said first high K dielectric layer, the said first metal gate material layer and said first polysilicon layer; Said first cover layer of said Semiconductor substrate of exposed portions serve and part, and said first cover layer of the part of exposing covers said shallow trench isolation and leaves;
Forming second cover layer, the second high K dielectric layer, the second metal gate material layer and second polysilicon layer successively on remaining first polysilicon layer, said first cover layer that exposes and on the said Semiconductor substrate of exposing;
Remove and cover said second cover layer, the said second high K dielectric layer, the said second metal gate material layer and said second polysilicon layer on said first polysilicon layer successively;
Remove and cover said shallow trench isolation successively from last said first cover layer, said second cover layer, the said second high K dielectric layer, the said second metal gate material layer and second polysilicon layer;
Form first high-K gate dielectric/metal-gate structures and second high-K gate dielectric/metal-gate structures respectively in the both sides that said shallow trench isolation leaves.
2. the manufacture method of pair high-K gate dielectric/metal-gate structures according to claim 1; It is characterized in that; Utilize photoetching and etching technics to remove and cover said second cover layer, the said second high K dielectric layer, the said second metal gate material layer and said second polysilicon layer on said first polysilicon layer successively, keep said second cover layer, the said second high K dielectric layer, the said second metal gate material layer and said second polysilicon layer that cover the said first polysilicon layer side successively.
3. the manufacture method of pair high-K gate dielectric/metal-gate structures according to claim 1; It is characterized in that, utilize photoetching and etching technics to remove and cover said shallow trench isolation successively from last said first cover layer, said second cover layer, the said second high K dielectric layer, the said second metal gate material layer and second polysilicon layer.
4. the manufacture method of pair high-K gate dielectric/metal-gate structures according to claim 1; It is characterized in that; Be formed with first silicon oxide layer between said first cover layer and the said Semiconductor substrate, be formed with second silicon oxide layer between said second cover layer and the said Semiconductor substrate.
5. the manufacture method of pair high-K gate dielectric/metal-gate structures according to claim 1 is characterized in that, the said first tectal material is a lanthana.
6. the manufacture method of pair high-K gate dielectric/metal-gate structures according to claim 1 is characterized in that, the said second tectal material is a lanthana.
7. the manufacture method of pair high-K gate dielectric/metal-gate structures according to claim 1 is characterized in that, the said first tectal thickness is 10nm～50nm.
8. the manufacture method of pair high-K gate dielectric/metal-gate structures according to claim 1 is characterized in that, the said second tectal thickness is 10nm～50nm.
9. the manufacture method of pair high-K gate dielectric/metal-gate structures according to claim 1 is characterized in that, the material of the said first metal gate material layer is a titanium nitride.
10. the manufacture method of pair high-K gate dielectric/metal-gate structures according to claim 1 is characterized in that, the material of the said second metal gate material layer is a tantalum nitride.
11. the manufacture method of according to claim 1 pair of high-K gate dielectric/metal-gate structures is characterized in that, the material of said first polysilicon layer and said second polysilicon layer is polysilicon.
12. the manufacture method of according to claim 1 pair of high-K gate dielectric/metal-gate structures; It is characterized in that; Remove and cover said shallow trench isolation successively after last said first cover layer, said second cover layer, the said second high K dielectric layer, the said second metal gate material layer and second polysilicon layer; Deposit spathic silicon cap layer utilizes photoetching and etching technics to form said first high-K gate dielectric/metal-gate structures and said second high-K gate dielectric/metal-gate structures.
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| US6787421B2 (en) * | 2002-08-15 | 2004-09-07 | Freescale Semiconductor, Inc. | Method for forming a dual gate oxide device using a metal oxide and resulting device |
| US8021939B2 (en) * | 2007-12-12 | 2011-09-20 | International Business Machines Corporation | High-k dielectric and metal gate stack with minimal overlap with isolation region and related methods |
| JP2010073985A (en) * | 2008-09-19 | 2010-04-02 | Toshiba Corp | Semiconductor device |
| JP5336814B2 (en) * | 2008-10-27 | 2013-11-06 | ルネサスエレクトロニクス株式会社 | Semiconductor device and manufacturing method thereof |
| US8309419B2 (en) * | 2009-02-04 | 2012-11-13 | Freescale Semiconductor, Inc. | CMOS integration with metal gate and doped high-K oxides |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101051638A (en) * | 2006-04-03 | 2007-10-10 | 台湾积体电路制造股份有限公司 | Semiconductor part |
| CN101783316A (en) * | 2009-01-16 | 2010-07-21 | 台湾积体电路制造股份有限公司 | Method of implantation |
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| Guohua Wang等.Process challenges in CMOS FEOL for 32nm node.《Proceedings of 2008 9th International Conference on Solid-State and Integrated-Circuit Technology 》.2008,第1135-1138页. |
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