CN103855077A - Semiconductor structure with contact plugs and forming method thereof - Google Patents
Semiconductor structure with contact plugs and forming method thereof Download PDFInfo
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- CN103855077A CN103855077A CN201210517708.5A CN201210517708A CN103855077A CN 103855077 A CN103855077 A CN 103855077A CN 201210517708 A CN201210517708 A CN 201210517708A CN 103855077 A CN103855077 A CN 103855077A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
- H01L23/5283—Cross-sectional geometry
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
- H01L2221/1068—Formation and after-treatment of conductors
Abstract
The invention discloses a semiconductor structure with contact plugs and a forming method thereof. The semiconductor structure comprises a substrate, a transistor, a first inner dielectric layer, a second inner dielectric layer, the first contact plug, the second contact plug and the third contact plug. The transistor is arranged on the substrate and comprises a grid and a source/drain area. The first inner dielectric layer is arranged on the transistor. The first contact plug is arranged in the first inner dielectric layer, and the top surface of the first contact plug is higher than the first top surface of the grid. The second inner dielectric layer is arranged on the first inner dielectric layer. The second contact plug is arranged in the second inner dielectric layer so as to be electrically connected with the first contact plug. The third contact plug is arranged in the first inner dielectric layer and the second inner dielectric layer so as to be electrically connected with the grid.
Description
Technical field
The present invention relates to a kind of semiconductor structure and its formation method with contact plug, special, relate to a kind of semiconductor structure, wherein the end face of the first contact plug is higher than the end face of grid.
Background technology
In existing semiconductor industry, polysilicon is widely used in semiconductor element as in metal-oxide semiconductor (MOS) (metal-oxide-semiconductor, MOS) transistor, selects as the grid material of standard.But, along with MOS transistor size micro constantly, tradition polysilicon gate reduces because boron penetration (boronpenetration) effect causes element efficiency, and the problem such as the depletion effects that is difficult to avoid (depletioneffect), make that equivalent gate dielectric layer thickness increases, grid capacitance value declines, and then cause the predicament such as decline of element drives ability.Therefore, semiconductor industry is more tasted with new grid material, for example utilize work function (work function) metal to replace traditional polysilicon gate, in order to the control electrode as coupling high-k (high-k) gate dielectric.
In addition, existing formation has after the transistor fabrication technique of metal gates, also can form external circuit thereon to be electrically connected respectively transistorized metal gates and source/drain regions, as with the input/output terminal of external electronic signal.But in existing manufacture craft, connect the external circuit of source/drain regions and conventionally can comprise multiple connected contact plugs up and down, this makes external circuit exist the problem of too high in resistance.And along with day by day dwindling of component size, the contact plug that connects source/drain regions easily contacts the situation that produces short circuit with metal gates, cause element quality to decline, and become the problem that needs solve.
Summary of the invention
The object of the present invention is to provide a kind of have contact plug semiconductor structure with and forming method thereof, to promote the electrical performance of overall semiconductor structure.
For reaching above-mentioned purpose, according to an embodiment of the invention, the invention provides a kind of semiconductor structure with contact plug, comprise a substrate, a transistor, one first inner layer dielectric layer, one second inner layer dielectric layer, one first contact plug, one second contact plug and one the 3rd contact plug.Transistor is arranged in substrate, and transistor comprises a grid and source/drain region.The first inner layer dielectric layer is arranged on transistor.The first contact plug is arranged in the first inner layer dielectric layer, the first contact plug electrical connection source/drain regions, and the end face of the first contact plug is higher than an end face of grid.The second inner layer dielectric layer is arranged on the first inner layer dielectric layer.Second contact plug in the second inner layer dielectric layer to be electrically connected the first contact plug.The 3rd contact plug is located in the first inner layer dielectric layer and the second inner layer dielectric layer with electrical connection grid.
Execution mode according to another preferred, the invention provides a kind of formation and has the method for semiconductor structure of contact plug.First one substrate is provided, then forms a transistor in substrate, transistor comprises a grid and source/drain region.Then form one first inner layer dielectric layer on transistor.Form one first contact plug in the first inner layer dielectric layer, the first contact plug electrical connection source/drain regions, and the end face of the first contact plug is higher than an end face of grid.Form one second inner layer dielectric layer on the first inner layer dielectric layer.Finally, form one second contact plug in the second inner layer dielectric layer to be electrically connected the first contact plug, with form one the 3rd contact plug in the first inner layer dielectric layer and the second inner layer dielectric layer be electrically connected grid.
Accompanying drawing explanation
Fig. 1 is to Figure 10 shows that a kind of formation of the present invention has the step schematic diagram of the semiconductor structure of contact plug.
Main element symbol description
300 substrate 324 second barrier layers
302 shallow trench isolations are from 326 second metal levels
304 contact hole etching stopping layer 328 second contact plugs
306 dielectric layers 330 the 3rd contact plug
308 first inner layer dielectric layer 400 transistors
310 first opening 402 grids
311 first barrier layer 403 end faces
312 the first metal layer 404 gate dielectrics
314 first contact plug 406 clearance walls
316 etching stopping layer 408 source/drain regions
318 second inner layer dielectric layer 408a source/drain regions
320 first opening 409 metal silicide layers
322 second opening 409a metal silicide layers
Embodiment
For making the general technology person who has the knack of the technical field of the invention can further understand the present invention, below spy enumerates several preferred embodiment of the present invention, and coordinates appended accompanying drawing, describe in detail constitution content of the present invention and effect of wanting to reach.
Please refer to Fig. 1 to Figure 10, illustrate has the step schematic diagram of semiconductor structure of contact plug for a kind of formation of the present invention, and wherein Fig. 2 is the generalized section along AA ' tangent line in Fig. 1, and Fig. 9 is the generalized section along AA tangent line in Figure 10.As shown in Figures 1 and 2, first provide a substrate 300, and in substrate 300, form multiple shallow trench isolations from (shallow trench isolation, STI) 302.Substrate 300 can be for example silicon base (silicon substrate), epitaxial silicon (epitaxial silicon substrate), SiGe semiconductor base (silicon germanium substrate), silicon carbide substrate (silicon carbidesubstrate) or silicon-coated insulated (silicon-on-insulator, SOI) substrate, but be not limited with above-mentioned.Then in substrate 300, form a transistor 400.Transistor 400 has a grid 402 and source/drain region 408.In preferred embodiment of the present invention, transistor 400 is to form the transistor 400 with metal gates 402 by a rear grid (gate last) semiconductor fabrication process.For instance, rear gate fabrication process is first to form a dummy gate (not shown) in substrate 300, sequentially form again a clearance wall 406, source/drain region 408, a contact hole etching stopping layer (contact etch stop layer, CESL) 304 and a dielectric layer 306, then remove dummy gate to form a groove (not shown), finally in groove, insert a gate dielectric 404 and a grid 402, then carry out a planarization manufacture craft one end face 403 of grid 402 is flushed with dielectric layer 306.In one embodiment, as shown in Figure 2, gate dielectric 404 has one " U-shaped " section, and its material can comprise silicon dioxide, also can comprise high-k (high-K) material; Grid 402 can comprise one or more layers metal material, for example, comprise a workfunction layers (work function metal layer), a barrier layer (barrier layer) and a low resistance metal layer.
It should be noted that, each element in transistor 400 can have according to different designs different enforcement aspects, for instance, as shown in Figure 2, source/drain regions 408 can comprise with selective epitaxial growth (selective epitaxial growth, SEG) germanium silicide (SiGe) or the carborundum (SiC) that form, to be applicable to respectively P-type mos transistor (PMOS) or N-type metal oxide semiconductor transistor (NMOS).In preferred embodiment of the present invention, the epitaxial loayer that source/drain regions 408 comprises can project upwards in substrate 300, and extends downward in substrate 300.In one embodiment, epitaxial loayer has hexahedron (hexagon is again sigma Σ) or octahedra (octagon) cross sectional shape, and has the bottom surface of a flat.In another embodiment, this epitaxial loayer can further extend to clearance wall 406 belows, for increasing the required stress of 402 times square channels of grid (channel).Or as shown in Figure 3, source/drain regions 408 also can Implantation etc. mode form source/drain regions 408a, and the shape of source/drain regions 408 also can be adjusted according to 402 times required stress of square channel of grid; And in another embodiment, contact hole etching stopping layer 304 also can have a stress.And in another embodiment of the present invention, as shown in Figure 3, being different from gate dielectric 404 in the embodiment of Fig. 2 is to form (being that gate dielectric 404 is formation removing dummy gate after) with " rear high dielectric constant layer (high-klast) " manufacture craft, in the embodiment of Fig. 3, gate dielectric 404a forms (being that gate dielectric is to form before dummy gate) with " first high dielectric number of plies layer (high-k first) " manufacture craft, therefore gate dielectric 404a has " type " section, on the other hand, in the embodiment of Fig. 3, on the 408a of source/drain regions, also can there is a metal silicide layer (silicide) layer 409a.Above-mentioned execution mode is only example, and transistor 400 of the present invention can have the various different aspects of implementing, and does not repeat one by one at this.Following examples are described the enforcement aspect with transistor in Fig. 2 400.
As shown in Figure 4, in substrate 300, form one first inner layer dielectric layer 308 comprehensively.Then in dielectric layer 306 and the first inner layer dielectric layer 308, form one first opening 310, wherein the first opening 310 can expose source/drain regions 408.The mode that forms the first opening 310 for example forms one first mask layer (not shown) and one first photoresist layer (not shown) on the first inner layer dielectric layer 308, and utilize at least one lithography step and at least one etching step to distinguish patterning the first photoresist layer and the first mask layer, then remove the first photoresist layer, and utilize the first mask layer after patterning to carry out etching the first inner layer dielectric layer 308 and dielectric layer 306 for mask, to form the first opening 310.In one embodiment of this invention, the first photoresist layer and the first mask layer can have different selections depending on Manufacturing Techniques, for instance, the first photoresist layer is for example the photoresist material that is applicable to 193 nanometers (nm) wavelength, and the first photoresist layer below can optionally comprise an end anti-reflecting layer (bottom anti-reflection coating, BARC); The first mask layer can be the various materials that are suitable as hard mask, it can comprise one or more layers mask material, these materials are for example silicon nitride (silicon nitride, SiN), silicon oxynitride (silicon oxynitride, SiON), carborundum (siliconcarbide, SiC) be or the organic material of carbon containing, for example the advanced patterned film (advanced pattern film, APF) that Applied Materials provides.In a preferred embodiment, siliceous anti-reflecting layer (the silicon-containing hard-mask bottom anti-reflection coating that mask layer is for example provided by chemical company of TaiWan, China SHIN-ETSU HANTOTAI (Shin-Etsu Chemical Co.Ltd.), SHB) with organic dielectric layer (organic dielectric layer, ODL), wherein SHB layer is located immediately under photoresist layer, can be used as end anti-reflecting layer and a mask layer, ODL layer is the mask layer final as.
In one embodiment of this invention, after formation the first opening 310, can carry out a self-aligned metal silicate (salicide) manufacture craft, to form a metal silicide layer 409 on the source/drain regions 408 being exposed at the first opening 310, for example, it is a nickle silicide (NiSi) layer.And in another embodiment of the present invention, if according to the enforcement aspect of Fig. 3, it is upper that metal silicide layer 409a has been formed on source/drain regions 408a, this step that forms metal silicide can be omitted.
Then as shown in Figure 5, in the first opening 310, form one first contact plug 314.Form the method for the first contact plug 314, for example first in substrate 300, form one first barrier layer 311 and a first metal layer 312, wherein the first barrier layer 311 conformally (conformally) be filled in the first opening 310, and the first metal layer 312 fills up the first opening 310 completely.In one embodiment of this invention, the first barrier layer 311 is for example titanium (Ti), titanium nitride (TiN), tantalum titanium (TaN) or can comprises multilayer different metal material, such as titanium/titanium oxide etc., but not as limit.The first metal layer 312 comprises various low-resistance metal materials, for example the materials such as aluminium (Al), titanium (Ti), tantalum (Ta), tungsten (W), niobium (Nb), molybdenum (Mo), copper (Cu), be preferably tungsten or copper, the best is tungsten, to form suitable ohmic contact (Ohmic contact) with the source/drain regions 408 of metal silicide layer 409 or below.In one embodiment of this invention, the first contact plug 314 can have suitable stress, for example make the first metal layer 312 form and have compression or stretching stress, this stress can increase the electrical performance of transistor 400 while being applied on source/drain regions 408.In one embodiment, if transistor 400 is NMOS, the first metal layer 312 can have stretching stress.Follow-up, carry out a planarization manufacture craft, for example cmp (chemical mechanical polish, CMP) manufacture craft, etching process or both combinations, to remove the first barrier layer 311 and the first metal layer 312 beyond the first opening 310, and further remove the first inner layer dielectric layer 308 to one predetermined thickness T.As shown in Figure 5, carrying out after planarization manufacture craft, the end face 403 of grid 402 is not exposed, and is also coated with the first inner layer dielectric layer 308 and has predetermined thickness T.In one embodiment of this invention, predetermined thickness T can be greater than 100 dusts, and better meeting is between 100 dust to 500 dusts, best between 100 dust to 300 dusts.
As shown in Figure 6, in substrate 300, form an etching stopping layer 316 and one second inner layer dielectric layer 318 comprehensively.In preferred embodiment of the present invention, etching stopping layer 316 is for example a nitrogenous layer (nitrogen containing layer) or one carbon-containing bed (carbon containing layer), particularly, can be silicon nitride (SiN), carborundum (SiC) or carbonitride of silicium (SiCN).The second 318 of inner layer dielectric layers can comprise one or more layers dielectric layer structure, it can form by a chemical gaseous phase Shen long-pending (chemicalvapor deposition, CVD), rotary coating (spin-coating) or any manufacture craft that forms dielectric material that supplies.And in one embodiment of this invention, also can omit etching stopping layer 316, namely directly the second inner layer dielectric layer 318 is formed on the first inner layer dielectric layer 308.
As shown in Figure 7, carry out a photoetching and etching step, to form one second opening 320 in the second inner layer dielectric layer 318 and etching stopping layer 316, to expose the first contact plug 314.In one embodiment of this invention, the mode that forms the second opening 320 comprises formation one second mask layer (not shown) and one second photoresist layer (not shown), wherein the execution mode of the second photoresist layer and the second mask layer is similar to the first photoresist layer and the first mask layer, does not repeat them here.In one embodiment of this invention, the width of the second opening 320 can be greater than the width of the first contact plug 314, makes follow-up can minimizing while inserting conductive layer aim at failed probability, to increase the margin of manufacture craft.
Then as shown in Figure 8, carry out another photoetching and etching step, to form one the 3rd opening 322 in the second inner layer dielectric layer 318, etching stopping layer 316 and the first inner layer dielectric layer 308, wherein the 3rd opening 322 can expose the end face 403 of grid 402.In one embodiment of this invention, the mode that forms the 3rd opening 322 comprises formation one the 3rd mask layer (not shown) and one the 3rd photoresist layer (not shown), and wherein the execution mode of the 3rd photoresist layer and the 3rd mask layer is similar to the first photoresist layer and the first mask layer.And it should be noted that, in one embodiment, because the 3rd photoresist layer and the 3rd mask layer are to have adopted photoresist layer/SHB/ODL three-decker, wherein the ODL layer of below has the good hole ability of filling out, and therefore can effectively insert in the second opening 320.Forming after the 3rd opening 322, photoresist layer/SHB/ODL three-decker is being removed.Follow-up, also optionally carry out a cleaning manufacture craft, for example with argon gas (Ar), the surface of the second opening 320 and the 3rd opening 322 is cleaned.
As shown in Figures 9 and 10, in substrate 300, form one second barrier layer 324 and one second metal level 326, wherein the second barrier layer 324 can conformally form along the surface of the second opening 320 and the 3rd opening 322, and the second metal level 326 can fill up the second opening 320 and the 3rd opening 322 completely.In one embodiment of this invention, the second barrier layer 324 can be the material of single or multiple lift, for example, be titanium (Ti), titanium nitride (TiN), tantalum titanium (TaN), titanium/titanium oxide or above-mentioned combination; The second metal level 326 comprises various low-resistance metal materials, for example, be the materials such as aluminium, titanium, tantalum, tungsten, niobium, molybdenum, copper, is preferably tungsten or copper, and the best is copper, to reduce and grid 402 and first resistance value contacting between plug 314 of below.Then, carry out a planarization manufacture craft to remove the second barrier layer 324 and the second metal level 324 beyond the second opening 320 and the 3rd opening 322.As shown in Figure 9, the second barrier layer 324 that is arranged in the second opening 320 has formed second with the second metal level 324 and has contacted plug 328, contacts plug 330 and the second barrier layer 324 that is arranged in the 3rd opening 322 has also formed the 3rd with the second metal level 324 simultaneously.
In the other embodiment of the present invention, in the second opening 320 and the 3rd opening 322, also can insert different barrier layers and metal level.For instance, can first the 3rd opening 322 be inserted after a sacrifice layer, the second opening 320 is inserted to one second barrier layer and the second metal level, follow-up sacrifice layer in the 3rd opening 322 is removed, then cover on the second opening 320 with an other sacrifice layer in selectivity, then the 3rd opening 322 is inserted to one the 3rd barrier layer and one the 3rd metal level.Finally carry out again a planarization manufacture craft.Under these circumstances, the first contact plug 314, the second contact plug 328 and the 3rd contact plug 330 can have different metal levels separately.In one embodiment, the metal level in the first contact plug 314 and the second contact plug 328 can comprise tungsten, and the 3rd metal level contacting in plug 330 can comprise copper.In an other embodiment, the metal level of the first contact plug 314 comprises tungsten, and the metal level of the second contact plug 328 and the 3rd contact plug 330 comprises copper.
Finally, can carry out a metal interconnecting manufacture craft, on the second inner layer dielectric layer 318, form a metal interconnecting system (metal interconnection system) (not shown), it comprises multiple layer metal interlayer dielectric layer (inter-metal dielectric layer, IMD layer) and multiple layer metal layer (be so-called metal1, metal 2 ... Deng).Metal interconnecting system can be by the 3rd contact plug 330 to be electrically connected the grid 402 of transistor 400, and contact the source/drain regions 408 of plug 314 with electrical connection transistor 400 by the second contact plug 328 and first, so that the I/O of transistor 400 to external signal to be provided.
By method proposed by the invention, can and form in the second inner layer dielectric layer 318 at dielectric layer 306, the first inner layer dielectric layer 308 and first contact plug 314, the second contact plug 328 has contacted plug 330 (being 0 layer of so-called Metal) with the 3rd.As shown in Figure 9, the invention provides a kind of semiconductor structure with contact plug, include a substrate 300, a transistor 400, one first inner layer dielectric layer 308, one second inner layer dielectric layer 318, one first contact plug 314, one second contact plug 328 and one the 3rd contact plug 330.Transistor 400 is arranged in substrate 300, and comprises a grid 402 and source/drain region 408.The first inner layer dielectric layer 308 is arranged on transistor 400.The first contact plug 314 is arranged in the first inner layer dielectric layer 308, and the first contact plug 314 is electrically connected source/drain regions 408, and the end face of the first contact plug 314 is higher than the end face 403 of grid 402.The second inner layer dielectric layer 318 is arranged on the first inner layer dielectric layer 308.Second contact plug 328 in the second inner layer dielectric layer 318 be electrically connected this first contact plug 314.The 3rd contact plug 330 is located in the first inner layer dielectric layer 308 and the second inner layer dielectric layer 318 with electrical connection grid 402.
One of them feature of the present invention is, carrying out if the planarization manufacture craft of Fig. 5 is when forming the first contact plug 314, the end face 403 of grid 402 can't come out, but also can have the first inner layer dielectric layer 308 of a thickness T.Compare with existing technology; the planarization manufacture craft of prior art can be ground to the end face of grid conventionally; therefore while grinding, can easily damage grid 402; and in grinding manufacture craft, the element of necessary simultaneous grinding grid, gate dielectric, the first contact plug etc., is a test for the selection of lapping liquid.The present invention is by above-mentioned step, not only can avoid the shortcoming of above-mentioned prior art, on the other hand, in the time that formation the second contact plug 328 contacts the first contact plug 314, as shown in Figure 9, the end face 403 of the distance from bottom grid 402 of the second contact plug 328 also has a height T (i.e. the predetermined thickness T of the first inner layer dielectric layer 308), this makes to be not easy to produce short circuit with grid 402 at formation the second contact plug 328, therefore can increase manufacture craft allowance (process window).And different the second contact plug 328 and the 3rd contact plugs 330 of the follow-up formation degree of depth that such manufacture craft also makes, the second contact plug 328 can be arranged in the second inner layer dielectric layer 318 and etching stopping layer 316, and the 3rd contact plug 330 can be arranged in the second inner layer dielectric layer 318, etching stopping layer 316 and the first inner layer dielectric layer 308.
In this external one embodiment of the invention, the first contact plug 314 can have suitable stress, therefore the present invention is except reducing the grinding consume of the first contact plug 314, also there is the stress that other benefit is to retain the first contact plug 314, to increase the electrical performance of transistor 400.
Another one feature of the present invention is, forms the second opening 320 contact plug 314 directly to expose first with a photoetching and etching process, then forms the 3rd opening 322 directly to expose grid 402 with another photoetching and etching process.By the formation step of this two-part, can promote the positioning accurate accuracy of the second contact plug 328 and the 3rd contact plug 330.In addition, in another embodiment of the present invention, the order that forms the second opening 320 and the 3rd opening 322 can be exchanged, for example first form the 3rd opening 322 directly to expose grid 402 with a photoetching and etching process, then contact plug 314 directly to expose first forming the second opening 320 with an other photoetching and etching process.On the other hand, the present invention can be applied to other semiconductor products, the manufacture craft of the non-planar transistor (non-planarFET) such as such as fin formula field-effect transistor (finFET) and three gate field effect transistors (tri-gate FET), those embodiment all belong to the scope that the present invention is contained.
The foregoing is only preferred embodiment of the present invention, all equalizations of doing according to the claims in the present invention change and modify, and all should belong to covering scope of the present invention.
Claims (20)
1. formation has a method for the semiconductor structure of contact plug, comprises:
One substrate is provided;
Form a transistor in this substrate, this transistor comprises a grid and source/drain region;
Form one first inner layer dielectric layer on this transistor;
Form one first contact plug in this first inner layer dielectric layer, this first contact plug is electrically connected this source/drain regions, and the end face of this first contact plug is higher than an end face of this grid;
Form one second inner layer dielectric layer on this first inner layer dielectric layer; And
Form one second contact plug in this second inner layer dielectric layer be electrically connected this first contact plug, with form one the 3rd contact plug in this first inner layer dielectric layer and this second inner layer dielectric layer to be electrically connected this grid.
2. formation as claimed in claim 1 has the method for the semiconductor structure of contact plug, wherein forms this second contact plug and comprises with the 3rd step that contacts plug:
In this second inner layer dielectric layer, form one second opening to expose this first contact plug;
In this second inner layer dielectric layer and this first inner layer dielectric layer, form one the 3rd opening to expose this grid; And
In this second opening and the 3rd opening, insert one second metal level.
3. formation as claimed in claim 2 has the method for the semiconductor structure of contact plug, wherein first forms this second opening, then forms the 3rd opening.
4. formation as claimed in claim 2 has the method for the semiconductor structure of contact plug, wherein first forms the 3rd opening, then forms this second opening.
5. formation as claimed in claim 1 has the method for the semiconductor structure of contact plug, and the step that wherein forms this first contact plug comprises:
In this first inner layer dielectric layer, form one first opening to expose this source/drain regions;
In this first opening, insert a first metal layer; And
One planarization manufacture craft.
6. formation as claimed in claim 5 has the method for the semiconductor structure of contact plug, wherein carries out after this planarisation step, also has this first inner layer dielectric layer of a predetermined thickness on this end face of this grid.
7. formation as claimed in claim 6 has the method for the semiconductor structure of contact plug, and wherein this predetermined thickness is greater than 100 dusts.
8. formation as claimed in claim 5 has the method for the semiconductor structure of contact plug, wherein before inserting this first metal layer, also comprise an auto-alignment metal silicide production technique, to form a metal silicide layer in this source/drain regions exposing in this first opening.
9. formation as claimed in claim 1 has the method for the semiconductor structure of contact plug, and wherein this first contact plug has a stress.
10. formation as claimed in claim 1 has the method for the semiconductor structure of contact plug, also comprises and forms an etching stopping layer between this first inner layer dielectric layer and this second inner layer dielectric layer.
11. 1 kinds have the semiconductor structure of contact plug, comprise:
Substrate;
Transistor, is arranged in this substrate, and this transistor comprises a grid and source/drain region;
The first inner layer dielectric layer, is arranged on this transistor;
The first contact plug, is arranged in this first inner layer dielectric layer, and this first contact plug is electrically connected this source/drain regions, and the end face of this first contact plug is higher than an end face of this grid;
The second inner layer dielectric layer, is arranged on this first inner layer dielectric layer;
The second contact plug, is arranged in this second inner layer dielectric layer to be electrically connected this first contact plug; And
The 3rd contact plug, in this first inner layer dielectric layer and this second inner layer dielectric layer to be electrically connected this grid.
12. semiconductor structures with contact plug as claimed in claim 11, wherein this first inner layer dielectric layer on this grid has a predetermined thickness.
13. semiconductor structures with contact plug as claimed in claim 12, wherein this predetermined thickness is greater than 100 dusts.
14. semiconductor structures with contact plug as claimed in claim 11, wherein this source/drain regions comprises an epitaxial loayer, protrudes from this substrate.
15. semiconductor structures with contact plug as claimed in claim 11, wherein this transistor also comprises a metal silicide layer, is arranged between this first contact plug and this source/drain regions.
16. semiconductor structures with contact plug as claimed in claim 11, wherein this second contact plug contacts plug and all comprises one second metal level with the 3rd.
The semiconductor structure with contact plug described in 17. claims 16, wherein this first metal layer comprises tungsten, aluminium, copper, titanium, tantalum, tungsten, niobium or molybdenum.
The semiconductor structure with contact plug described in 18. claims 16, wherein this first contact plug comprises a first metal layer, and this first metal layer and this second metal level are unlike material.
The semiconductor structure with contact plug described in 19. claims 11, wherein this first contact plug comprises a first metal layer, this second plug comprises one second metal level, the 3rd plug comprises one the 3rd metal level, and this first metal layer, this second metal level and the 3rd metal level are unlike material.
The semiconductor structure with contact plug described in 20. claims 11, wherein also comprises an etching stopping layer, is arranged between this first inner layer dielectric layer and this second inner layer dielectric layer.
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| CN106098775A (en) * | 2015-04-30 | 2016-11-09 | 三星电子株式会社 | Semiconductor device |
| CN106887463A (en) * | 2015-12-16 | 2017-06-23 | 台湾积体电路制造股份有限公司 | Semiconductor devices and its manufacture method |
| CN108122982A (en) * | 2016-11-29 | 2018-06-05 | 台湾积体电路制造股份有限公司 | The forming method of semiconductor device |
| CN112582405A (en) * | 2019-09-30 | 2021-03-30 | 台湾积体电路制造股份有限公司 | Semiconductor device and method of forming the same |
| CN113284892A (en) * | 2014-07-08 | 2021-08-20 | 联华电子股份有限公司 | Semiconductor element and manufacturing method thereof |
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| CN113284892A (en) * | 2014-07-08 | 2021-08-20 | 联华电子股份有限公司 | Semiconductor element and manufacturing method thereof |
| CN113284892B (en) * | 2014-07-08 | 2023-08-15 | 联华电子股份有限公司 | Semiconductor element and manufacturing method thereof |
| CN106098775A (en) * | 2015-04-30 | 2016-11-09 | 三星电子株式会社 | Semiconductor device |
| CN106098775B (en) * | 2015-04-30 | 2021-02-02 | 三星电子株式会社 | Semiconductor device with a plurality of transistors |
| CN106887463A (en) * | 2015-12-16 | 2017-06-23 | 台湾积体电路制造股份有限公司 | Semiconductor devices and its manufacture method |
| US10756192B2 (en) | 2015-12-16 | 2020-08-25 | Taiwan Semiconductor Manufacturing Company Limited | Semiconductor device and method for manufacturing the same |
| CN108122982A (en) * | 2016-11-29 | 2018-06-05 | 台湾积体电路制造股份有限公司 | The forming method of semiconductor device |
| CN108122982B (en) * | 2016-11-29 | 2022-12-02 | 台湾积体电路制造股份有限公司 | Method for forming semiconductor device |
| CN112582405A (en) * | 2019-09-30 | 2021-03-30 | 台湾积体电路制造股份有限公司 | Semiconductor device and method of forming the same |
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| CN103855077B (en) | 2018-07-10 |
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