CN102332397A - Method for manufacturing two high-K gate dielectric/metal gate structures - Google Patents
Method for manufacturing two high-K gate dielectric/metal gate structures Download PDFInfo
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- CN102332397A CN102332397A CN201110327922A CN201110327922A CN102332397A CN 102332397 A CN102332397 A CN 102332397A CN 201110327922 A CN201110327922 A CN 201110327922A CN 201110327922 A CN201110327922 A CN 201110327922A CN 102332397 A CN102332397 A CN 102332397A
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Abstract
The invention provides a method for manufacturing two high-K gate dielectric/metal gate structures, which comprises the following steps of: providing a semiconductor substrate with shallow trench isolation (STI), forming a first high-K dielectric layer, a first metal gate material layer and a first polycrystalline silicon layer on the semiconductor substrate and the STI in turn, and etching the three layers to expose a part of semiconductor substrate; forming a second high-K dielectric layer, a second metal gate material layer and a second polycrystalline silicon layer on the first polycrystalline silicon layer and the exposed semiconductor substrate in turn; removing the first high-K dielectric layer, the first metal gate material layer and the first polycrystalline silicon layer which cover the STI in turn; and forming a first high-K gate dielectric/metal gate structure and a second high-K gate dielectric/metal gate structure on two sides of the STI. By the manufacturing method, the STI is prevented from being damaged, a short circuit caused by the damage of the STI is further avoided, and product yield is improved.
Description
Technical field
The present invention relates to the manufacturing technology field of semiconductor integrated circuit, relate in particular to the manufacture method of a kind of pair of high-K gate dielectric/metal-gate structures.
Background technology
The integrated circuit especially main devices in the very lagre scale integrated circuit (VLSIC) is metal-oxide semiconductor fieldeffect transistor (metal oxide semiconductor field effect transistor is called for short MOS transistor).Since metal-oxide-semiconductor was invented, its physical dimension was constantly being dwindled always, and its characteristic size has got into the 45nm scope at present.Under this size situation, basic restriction and technological challenge begin to occur, device size further dwindle the more and more difficult that just becomes.Wherein, in the preparation of MOS transistor device and circuit, tool is challenging to be that the traditional cmos device is in the process of dwindling, because the thickness of gate oxide medium reduces to bring high grid Leakage Current in polysilicon/SiO2 structure or the polysilicon/SiCN structure.
For this reason, the solution that has proposed is to adopt metal gate and high-k (K) gate medium to substitute traditional heavily doped polysilicon grid and SiO2 (or SiON) gate medium.In order to reach adjustment NMOS and the PMOS needs of work function separately; The formation method of metal gate and high K medium is divided into a variety of; Corresponding multiple formation structure has the two high K mediums (DMDD) of bimetal gate, the two high K mediums (SMDD) of monometallic grid, bimetal gate list high K medium structures such as (DMSD).Wherein using is DMDD more widely; With reference to Figure 1A～1C; Have shallow trench isolation at first the deposit first high K medium layer 12, the first metal gate material layer 13 and first polysilicon layer 14 on 11 the Semiconductor substrate 10; Optionally carry out etching then; Make the remaining first high K medium layer 12, the first metal gate material layer 13 and first polysilicon layer 14 cover a part of Semiconductor substrate 10; Afterwards at first polysilicon layer 14, shallow trench isolation from 11 and Semiconductor substrate 10 surfaces that are not capped the deposit second high K medium layer 12 ', the second metal gate material layer 13 ' and second polysilicon layer 14 ' successively, vertically highly bigger owing to the second high K medium layer 12 ' that covers the first high K medium layer 12, the first metal gate material layer 13 and first polysilicon layer, 14 sides and the second metal gate material layer 13 ', therefore; Form in the process of first high-K gate dielectric/metal-gate structures and second high-K gate dielectric/metal-gate structures in the later stage etching; The etching effect that this vertical effect of altitude is whole makes other vertically highly less etched portions early accomplish etching, and therefore sustains damage 15 easily at vertically highly less infratectal shallow trench isolation from 11; Serious meeting causes shallow trench isolation to leave 11 inefficacy, forms short circuit; Even without serious loss, also the process window to wet method and dry etching has very big restriction, has increased technology difficulty.
Summary of the invention
Technical problem to be solved by this invention has provided the manufacture method of a kind of pair of high-K gate dielectric/metal-gate structures, is isolated in the problem that sustains damage easily in the process of etching to solve shallow trench.
In order to solve the problems of the technologies described above; Technical scheme of the present invention is: the manufacture method that a kind of pair of high-K gate dielectric/metal-gate structures is provided; Comprise: provide to have the Semiconductor substrate that shallow trench isolation leaves; Leave at said Semiconductor substrate and said shallow trench isolation and to form the first high K dielectric layer, the first metal gate material layer and first polysilicon layer successively, the etching said first high K dielectric layer, the said first metal gate material layer and said first polysilicon layer, the said Semiconductor substrate of exposed portions serve; On remaining first polysilicon layer and the said Semiconductor substrate exposed, form the second high K dielectric layer, the second metal gate material layer and second polysilicon layer successively; Remove and cover the said second high K dielectric layer on said first polysilicon layer, the said second metal gate material layer and said second polysilicon layer successively, keep covering the said second high K dielectric layer of the said first polysilicon layer side, the said second metal gate material layer and said second polysilicon layer successively; Remove and cover said shallow trench isolation successively from the last said first high K dielectric layer, the said first metal gate material layer and said first polysilicon layer; Form first high-K gate dielectric/metal-gate structures and second high-K gate dielectric/metal-gate structures respectively in the both sides that said shallow trench isolation leaves.
Further; Utilize photoetching and etching technics to remove and cover the said second high K dielectric layer on said first polysilicon layer, the said second metal gate material layer and said second polysilicon layer successively, keep covering the said second high K dielectric layer of the said first polysilicon layer side, the said second metal gate material layer and said second polysilicon layer successively.
Further, utilize photoetching and etching technics to remove and cover said shallow trench isolation successively from the last said first high K dielectric layer, the said first metal gate material layer and said first polysilicon layer.
Further, be formed with first silicon oxide layer between the said first high K dielectric layer and the said Semiconductor substrate, be formed with second silicon oxide layer between the said second high K dielectric layer and the said Semiconductor substrate.
Further, the material of the said first metal gate material layer is a titanium nitride.
Further, the material of the said second metal gate material layer is a tantalum nitride.
Further, the material of said first polysilicon layer and said second polysilicon layer is polysilicon.
Further; Remove and cover said shallow trench isolation successively after the last said first high K dielectric layer, the said first metal gate material layer and said first polysilicon layer; Deposit spathic silicon cap layer utilizes photoetching and etching technics to form said first high-K gate dielectric/metal-gate structures and said second high-K gate dielectric/metal-gate structures.
The manufacture method of provided by the invention pair of high-K gate dielectric/metal-gate structures; It is all even from the thickness of the last first high K dielectric layer, the first metal gate material layer and first polysilicon layer to cover shallow trench isolation; Therefore it is even to guarantee that etching is removed shallow trench isolation etch rate when the first last high K dielectric layer, the first metal gate material layer and first polysilicon layer; Avoid shallow trench isolation from sustaining damage; Further avoided because the short circuit that the shallow trench isolation damage causes has improved the product yield.
Description of drawings
Figure 1A～1C is the pairing cross-sectional view of manufacture method of two high-K gate dielectric/metal-gate structures in the prior art;
Fig. 2 is the flow chart of steps of the manufacture method of two high-K gate dielectric/metal-gate structures of providing of the embodiment of the invention;
Fig. 3 A～3F is the pairing cross-sectional view of manufacture method of two high-K gate dielectric/metal-gate structures of providing of the embodiment of the invention.
Embodiment
Below in conjunction with accompanying drawing and specific embodiment the manufacture method of a kind of pair of high-K gate dielectric/metal-gate structures of the present invention's proposition is done further explain.According to following explanation and claims, advantage of the present invention and characteristic will be clearer.What need explanation is, accompanying drawing all adopts the form of simplifying very much and all uses non-ratio accurately, only is used for conveniently, the purpose of the aid illustration embodiment of the invention lucidly.
Core concept of the present invention is; The manufacture method of the two high-K gate dielectric/metal-gate structures that provide; It is all even from the thickness of the last first high K dielectric layer, the first metal gate material layer and first polysilicon layer to cover shallow trench isolation; Therefore it is even to guarantee that etching is removed shallow trench isolation etch rate when the first last high K dielectric layer, the first metal gate material layer and first polysilicon layer; Avoid shallow trench isolation from sustaining damage, further avoided because the short circuit that the shallow trench isolation damage causes has improved the product yield.
Fig. 2 is the flow chart of steps of the manufacture method of two high-K gate dielectric/metal-gate structures of providing of the embodiment of the invention.With reference to Fig. 2, the manufacture method of a kind of pair of high-K gate dielectric/metal-gate structures that provides comprises:
S21, provide and have the Semiconductor substrate that shallow trench isolation leaves; Leave at said Semiconductor substrate and said shallow trench isolation and to form the first high K dielectric layer, the first metal gate material layer and first polysilicon layer successively; The etching said first high K dielectric layer, the said first metal gate material layer and said first polysilicon layer, the said Semiconductor substrate of exposed portions serve;
S22, on remaining first polysilicon layer and the said Semiconductor substrate exposed, form the second high K dielectric layer, the second metal gate material layer and second polysilicon layer successively;
S23, removal cover the said second high K dielectric layer on said first polysilicon layer, the said second metal gate material layer and said second polysilicon layer successively, keep covering the said second high K dielectric layer of the said first polysilicon layer side, the said second metal gate material layer and said second polysilicon layer successively;
S24, removal cover said shallow trench isolation successively from the last said first high K dielectric layer, the said first metal gate material layer and said first polysilicon layer;
S25, form first high-K gate dielectric/metal-gate structures and second high-K gate dielectric/metal-gate structures respectively in the both sides that said shallow trench isolation leaves.
To combine cross-sectional view that the manufacture method of of the present invention pair of high-K gate dielectric/metal-gate structures is described in more detail below; The preferred embodiments of the present invention have wherein been represented; Should be appreciated that those skilled in the art can revise the present invention described here, and still realize advantageous effects of the present invention.
Fig. 3 A～3F is the pairing cross-sectional view of manufacture method of two high-K gate dielectric/metal-gate structures of providing of the embodiment of the invention.With reference to Fig. 3 A and integrating step S21; Provide and have shallow trench isolation from 31 Semiconductor substrate 30; On 31, form the first high K dielectric layer 32, the first metal gate material layer 33 and first polysilicon layer 34 successively at said Semiconductor substrate 30 and said shallow trench isolation; The high K dielectric layer of etching said first 32, the said first metal gate material layer 33 and said first polysilicon layer 34; The said Semiconductor substrate 30 of exposed portions serve, said shallow trench isolation is covered by the first high K dielectric layer 32, the first metal gate material layer 33 and first polysilicon layer 34 from 31 successively.
With reference to Fig. 3 B and integrating step S22, on remaining first polysilicon layer 34 and the said Semiconductor substrate 30 exposed, form the second high K dielectric layer 32 ', the second metal gate material layer 33 ' and second polysilicon layer 34 ' successively.
With reference to Fig. 3 C and integrating step S23; Adopt photoetching and etching technics to remove to cover successively the said second high K dielectric layer 32 ' on said first polysilicon layer 34, the said second metal gate material layer 33 ' and said second polysilicon layer 34 ', keep covering the said second high K dielectric layer 32 ' of said first polysilicon layer, 34 sides, the said second metal gate material layer 33 ' and said second polysilicon layer 34 ' successively.
With reference to Fig. 3 D and integrating step S24, adopt photoetching and etching technics to remove to cover successively said first high K dielectric layer 32, said first metal gate material layer 33 and said first polysilicon layer 34 of said shallow trench isolation on 31, to form groove 37.Because the said first high K dielectric layer 32 of shallow trench isolation on 31, the said first metal gate material layer 33 and said first polysilicon layer, 34 every layer thickness are even; Therefore etching is removed in this process of three layers successively; The etch rate of each layer of etching is all identical at sustained height; The degree of depth that can guarantee etching when each layer of etching is identical, therefore after getting rid of last one deck first high K dielectric layer 32, can avoid being damaged to shallow trench isolation from 31.
With reference to Fig. 3 E, Fig. 3 F and integrating step S25; Deposit spathic silicon cap layer 35 on first polysilicon layer 34 and second polysilicon layer 34 ' and in the groove 37 utilizes photoetching and etching technics to form first high-K gate dielectric/metal-gate structures 36 and second high-K gate dielectric/metal-gate structures 36 ' at said shallow trench isolation from 31 both sides.
In the present embodiment, the material of the said first metal gate material layer 33 is titanium nitrides, and the material of the said second metal gate material layer 33 ' is a tantalum nitride, and the material of said first polysilicon layer 34 and said second polysilicon layer 34 ' is polysilicon.
Further; Be formed with first silicon oxide layer between the said first high K dielectric layer 32 and the said Semiconductor substrate 30; Be formed with second silicon oxide layer between the said second high K dielectric layer 32 ' and the said Semiconductor substrate 30, in the present embodiment, said first silicon oxide layer and said second silicon oxide layer be not shown in the drawings; But said first silicon oxide layer and said second silicon oxide layer exist, and those of ordinary skills should know knowledge.First silicon oxide layer makes that the adhesiveness between the said first high K dielectric layer 32 and the said Semiconductor substrate 30 is better, and second silicon oxide layer makes that the adhesiveness between the said second high K dielectric layer 32 ' and the said Semiconductor substrate 30 is better.
Obviously, those skilled in the art can carry out various changes and modification to invention and not break away from the spirit and scope of the present invention.Like this, belong within the scope of claim of the present invention and equivalent technologies thereof if of the present invention these are revised with modification, then the present invention also is intended to comprise these changes and modification interior.
Claims (8)
1. the manufacture method of two high-K gate dielectric/metal-gate structures is characterized in that, comprising:
Provide and have the Semiconductor substrate that shallow trench isolation leaves; Leave at said Semiconductor substrate and said shallow trench isolation and to form the first high K dielectric layer, the first metal gate material layer and first polysilicon layer successively; The etching said first high K dielectric layer, the said first metal gate material layer and said first polysilicon layer, the said Semiconductor substrate of exposed portions serve;
On remaining first polysilicon layer and the said Semiconductor substrate exposed, form the second high K dielectric layer, the second metal gate material layer and second polysilicon layer successively;
Remove and cover the said second high K dielectric layer on said first polysilicon layer, the said second metal gate material layer and said second polysilicon layer successively;
Remove and cover said shallow trench isolation successively from the last said first high K dielectric layer, the said first metal gate material layer and said first polysilicon layer;
Form first high-K gate dielectric/metal-gate structures and second high-K gate dielectric/metal-gate structures respectively in the both sides that said shallow trench isolation leaves.
2. the manufacture method of pair high-K gate dielectric/metal-gate structures according to claim 1; It is characterized in that; Utilize photoetching and etching technics to remove and cover the said second high K dielectric layer on said first polysilicon layer, the said second metal gate material layer and said second polysilicon layer successively, keep covering the said second high K dielectric layer of the said first polysilicon layer side, the said second metal gate material layer and said second polysilicon layer successively.
3. the manufacture method of pair high-K gate dielectric/metal-gate structures according to claim 1; It is characterized in that, utilize photoetching and etching technics to remove and cover said shallow trench isolation successively from the last said first high K dielectric layer, the said first metal gate material layer and said first polysilicon layer.
4. the manufacture method of pair high-K gate dielectric/metal-gate structures according to claim 1; It is characterized in that; Be formed with first silicon oxide layer between the said first high K dielectric layer and the said Semiconductor substrate, be formed with second silicon oxide layer between the said second high K dielectric layer and the said Semiconductor substrate.
5. the manufacture method of pair high-K gate dielectric/metal-gate structures according to claim 1 is characterized in that, the material of the said first metal gate material layer is a titanium nitride.
6. the manufacture method of pair high-K gate dielectric/metal-gate structures according to claim 1 is characterized in that, the material of the said second metal gate material layer is a tantalum nitride.
7. the manufacture method of pair high-K gate dielectric/metal-gate structures according to claim 1 is characterized in that, the material of said first polysilicon layer and said second polysilicon layer is polysilicon.
8. the manufacture method of pair high-K gate dielectric/metal-gate structures according to claim 1; It is characterized in that; Remove and cover said shallow trench isolation successively after the last said first high K dielectric layer, the said first metal gate material layer and said first polysilicon layer; Deposit spathic silicon cap layer utilizes photoetching and etching technics to form said first high-K gate dielectric/metal-gate structures and said second high-K gate dielectric/metal-gate structures.
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US6833596B2 (en) * | 2002-03-27 | 2004-12-21 | Kabushiki Kaisha Toshiba | Semiconductor device and method of manufacturing the same |
| JP2006339210A (en) * | 2005-05-31 | 2006-12-14 | Sanyo Electric Co Ltd | Process for fabricating semiconductor device and semiconductor device |
| CN101051638A (en) * | 2006-04-03 | 2007-10-10 | 台湾积体电路制造股份有限公司 | Semiconductor part |
| US20090108368A1 (en) * | 2007-10-31 | 2009-04-30 | Kenshi Kanegae | Semiconductor device and method for manufacturing the same |
| US20090152650A1 (en) * | 2007-12-12 | 2009-06-18 | International Business Machines Corporation | High-k dielectric and metal gate stack with minimal overlap with isolation region and related methods |
| US20100207214A1 (en) * | 2009-02-18 | 2010-08-19 | United Microelectronics Corp. | Semiconductor device and method of fabricating the same |
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Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6833596B2 (en) * | 2002-03-27 | 2004-12-21 | Kabushiki Kaisha Toshiba | Semiconductor device and method of manufacturing the same |
| JP2006339210A (en) * | 2005-05-31 | 2006-12-14 | Sanyo Electric Co Ltd | Process for fabricating semiconductor device and semiconductor device |
| CN101051638A (en) * | 2006-04-03 | 2007-10-10 | 台湾积体电路制造股份有限公司 | Semiconductor part |
| US20090108368A1 (en) * | 2007-10-31 | 2009-04-30 | Kenshi Kanegae | Semiconductor device and method for manufacturing the same |
| US20090152650A1 (en) * | 2007-12-12 | 2009-06-18 | International Business Machines Corporation | High-k dielectric and metal gate stack with minimal overlap with isolation region and related methods |
| US20100207214A1 (en) * | 2009-02-18 | 2010-08-19 | United Microelectronics Corp. | Semiconductor device and method of fabricating the same |
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Application publication date: 20120125 |