CN116130431B - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereof Download PDFInfo
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- CN116130431B CN116130431B CN202310382824.9A CN202310382824A CN116130431B CN 116130431 B CN116130431 B CN 116130431B CN 202310382824 A CN202310382824 A CN 202310382824A CN 116130431 B CN116130431 B CN 116130431B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 60
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 46
- 239000010410 layer Substances 0.000 claims abstract description 444
- 239000011229 interlayer Substances 0.000 claims abstract description 100
- 229910052751 metal Inorganic materials 0.000 claims abstract description 86
- 239000002184 metal Substances 0.000 claims abstract description 86
- 230000004888 barrier function Effects 0.000 claims abstract description 72
- 239000000463 material Substances 0.000 claims abstract description 42
- 230000000903 blocking effect Effects 0.000 claims abstract description 32
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 32
- 229920005591 polysilicon Polymers 0.000 claims description 21
- 238000002161 passivation Methods 0.000 claims description 13
- 238000000034 method Methods 0.000 claims description 12
- 150000002500 ions Chemical class 0.000 claims description 9
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 9
- 239000005380 borophosphosilicate glass Substances 0.000 claims description 8
- 238000005530 etching Methods 0.000 claims description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 238000006243 chemical reaction Methods 0.000 description 7
- 230000008569 process Effects 0.000 description 6
- 230000000694 effects Effects 0.000 description 5
- 229910004298 SiO 2 Inorganic materials 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 230000008021 deposition Effects 0.000 description 4
- 238000000151 deposition Methods 0.000 description 4
- 230000003628 erosive effect Effects 0.000 description 4
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- 238000007254 oxidation reaction Methods 0.000 description 4
- 235000012239 silicon dioxide Nutrition 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
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- 238000010586 diagram Methods 0.000 description 2
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- 238000002955 isolation Methods 0.000 description 2
- 239000000155 melt Substances 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000035515 penetration Effects 0.000 description 2
- 229910005883 NiSi Inorganic materials 0.000 description 1
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
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- 229910001415 sodium ion Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/562—Protection against mechanical damage
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
- H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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Abstract
The application provides a semiconductor device and a manufacturing method of the semiconductor device, and relates to the technical field of semiconductors. The semiconductor device comprises a first type epitaxial wafer, wherein a second type well region and a first type doping region positioned in the well region are arranged on the epitaxial wafer, a first metal layer positioned on the back of the epitaxial wafer, a gate oxide layer positioned on the front of the epitaxial wafer and contacted with the first type doping region, a contact layer positioned on the front of the epitaxial wafer and except the gate oxide layer, a polycrystalline silicon layer positioned on one side of the gate oxide layer far away from the epitaxial wafer, a stress buffer layer positioned on one side of the polycrystalline silicon layer far away from the epitaxial wafer, a blocking layer positioned on one side of the stress buffer layer and the contact layer far away from the epitaxial wafer, and a second metal layer positioned on one side of the blocking layer far away from the epitaxial wafer; the stress buffer layer is used for reducing interlayer stress of the semiconductor device material, and the barrier layer is used for isolating the second metal layer. The device has the advantage of improving the reliability of the device under the condition of short circuit or surge.
Description
Technical Field
The application relates to the technical field of semiconductors, in particular to a semiconductor device and a manufacturing method of the semiconductor device.
Background
In the conventional SiC MOSFET device structure, siO is generally adopted 2 As an interlayer dielectric layer, aluminum metal is used as a top thick metal layer, the aluminum metal is in direct contact with the interlayer dielectric layer, when a short circuit problem occurs or large surge current is generated in the device, the device generates extremely high temperature, and after the high temperature exceeds the melting point (660 ℃) of Al, the source metal Al of the SiC MOSFET can be melted and reacts with other materials, such as the interlayer dielectric layer, an ohmic contact layer and the like.
Meanwhile, al metal melts into a liquid state, so that abrupt change of thermal expansion coefficient is caused, and huge stress is generated between interlayer dielectric layers due to thermal mismatch, so that cracks are generated, melted Al penetrates into a grid electrode through crack erosion, short circuit failure and surge failure are caused, and the reliability of a device is seriously affected.
In summary, the prior art has the problem of poor reliability of the device in the case of short circuit or surge.
Disclosure of Invention
The invention aims to provide a semiconductor device and a manufacturing method of the semiconductor device, which are used for solving the problem of poor stability of the device under the condition of short circuit or surge in the prior art.
In order to solve the above problems, the present application provides the following technical solutions:
in one aspect, embodiments of the present application provide a semiconductor device, including:
the epitaxial wafer comprises a first type epitaxial wafer, wherein a second type well region and a first type doped region positioned in the well region are arranged on the epitaxial wafer;
the first metal layer is positioned on the back surface of the epitaxial wafer;
the gate oxide layer is positioned on the front surface of the epitaxial wafer and is in contact with the first type doped region;
the contact layer is positioned on the front surface of the epitaxial wafer and is positioned in a region except the gate oxide layer;
the polycrystalline silicon layer is positioned on one side of the gate oxide layer far away from the epitaxial wafer;
the stress buffer layer is positioned on one side of the polycrystalline silicon layer away from the epitaxial wafer;
the blocking layer is positioned on one side of the stress buffer layer and one side of the contact layer, which is far away from the epitaxial wafer;
the second metal layer is positioned on one side of the barrier layer away from the epitaxial wafer; wherein,,
the stress buffer layer is used for reducing interlayer stress of the semiconductor device material, and the barrier layer is used for isolating the second metal layer.
Optionally, the stress buffer layer includes:
the first interlayer dielectric layer is positioned on one side of the gate oxide layer far away from the epitaxial wafer;
the second interlayer dielectric layer is positioned on one side of the first interlayer dielectric layer far away from the epitaxial wafer;
the third interlayer dielectric layer is positioned on one side of the second interlayer dielectric layer far away from the epitaxial wafer; wherein,,
the first interlayer dielectric layer and the second interlayer dielectric layer are used for blocking water vapor and ions; the third interlayer dielectric layer is used for reducing the stress of the semiconductor device.
Optionally, the first interlayer dielectric layer includes a silicon oxynitride layer, the second interlayer dielectric layer includes an HTO layer, and the third interlayer dielectric layer includes a BPSG layer.
Optionally, the barrier layer includes:
the blocking dielectric layer is positioned on one side of the stress buffer layer away from the epitaxial wafer;
the barrier metal layer is positioned on one side of the barrier dielectric layer and the contact layer away from the epitaxial wafer; wherein,,
the barrier metal layer is used for isolating the second metal layer from the contact layer;
the blocking dielectric layer is used for isolating the blocking metal layer and the stress buffer layer.
Optionally, the material of the blocking dielectric layer includes at least one of SiN, siCN, siNH, siCH, siCNH; the material of the barrier metal layer comprises at least one of TiN and TaN; the material of the contact layer includes Ni, and the material of the second metal layer includes Al.
Optionally, the semiconductor device further includes:
and a passivation layer between the polysilicon layer and the stress buffer layer.
Optionally, the first type is N-type, and the second type is P-type; or alternatively, the first and second heat exchangers may be,
the first type is P type, and the second type is N type.
On the other hand, the embodiment of the application also provides a manufacturing method of the semiconductor device, which comprises the following steps:
providing a first type epitaxial wafer, wherein a second type well region and a first type doping region positioned in the well region are arranged on the epitaxial wafer;
manufacturing a gate oxide layer based on the area which is in contact with the first type doped area and is on the front surface of the epitaxial wafer;
manufacturing a polycrystalline silicon layer on the basis of one side, far away from the epitaxial wafer, of the gate oxide layer;
manufacturing a stress buffer layer on the basis of one side, far away from the epitaxial wafer, of the polycrystalline silicon layer;
etching and removing the redundant gate oxide layer and the stress buffer layer;
manufacturing a contact layer based on the front surface of the epitaxial wafer and the area except the gate oxide layer;
manufacturing a barrier layer on the basis of the stress buffer layer and one side, far away from the epitaxial wafer, of the contact layer;
manufacturing a second metal layer on the basis of one side, far away from the epitaxial wafer, of the barrier layer and manufacturing a first metal layer on the basis of the back surface of the epitaxial wafer; wherein,,
the stress buffer layer is used for reducing interlayer stress of the semiconductor device material, and the barrier layer is used for isolating the second metal layer.
Optionally, the step of fabricating a stress buffer layer based on a side of the polysilicon layer away from the epitaxial wafer includes:
manufacturing a first interlayer dielectric layer on the basis of one side, far away from the epitaxial wafer, of the gate oxide layer;
manufacturing a second interlayer dielectric layer based on one side of the first interlayer dielectric layer far away from the epitaxial wafer;
manufacturing a third interlayer dielectric layer based on one side, far away from the epitaxial wafer, of the second interlayer dielectric layer; wherein,,
the first interlayer dielectric layer and the second interlayer dielectric layer are used for blocking water vapor and ions; the third interlayer dielectric layer is used for reducing the stress of the semiconductor device.
Optionally, the step of fabricating a barrier layer based on the stress buffer layer and the side of the contact layer away from the epitaxial wafer includes:
manufacturing a blocking dielectric layer on the basis of one side, far away from the epitaxial wafer, of the stress buffer layer;
manufacturing a barrier metal layer on the basis of the barrier dielectric layer and the side, far away from the epitaxial wafer, of the contact layer; wherein,,
the barrier metal layer is used for isolating the second metal layer from the contact layer;
the blocking dielectric layer is used for isolating the blocking metal layer and the stress buffer layer.
Compared with the prior art, the embodiment of the application has the following beneficial effects:
the application provides a semiconductor device and a manufacturing method of the semiconductor device, wherein the semiconductor device comprises a first type epitaxial wafer, a second type well region and a first type doping region which is positioned in the well region are arranged on the epitaxial wafer, a first metal layer which is positioned on the back of the epitaxial wafer, a gate oxide layer which is positioned on the front of the epitaxial wafer and is contacted with the first type doping region, a contact layer which is positioned on the front of the epitaxial wafer and is in a region except the gate oxide layer, a polycrystalline silicon layer which is positioned on one side of the gate oxide layer, which is far away from the epitaxial wafer, a stress buffer layer which is positioned on one side of the polycrystalline silicon layer, which is far away from the epitaxial wafer, a blocking layer which is positioned on one side of the stress buffer layer and the contact layer, and a second metal layer which is positioned on one side of the blocking layer, which is far away from the epitaxial wafer; the stress buffer layer is used for reducing interlayer stress of the semiconductor device material, and the barrier layer is used for isolating the second metal layer. Because this application has add barrier layer and stress buffer layer on traditional device structure, and barrier layer and stress buffer layer can play the effect that reduces device material interlaminar stress and keep apart second metal layer, consequently when short circuit or surge condition appear, the condition of crackle or inefficacy is difficult to appear has promoted the reliability of device under short circuit or surge condition.
In order to make the above objects, features and advantages of the present application more comprehensible, preferred embodiments accompanied with figures are described in detail below.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered limiting in scope, and that other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic cross-sectional view of a prior art MOSFET device.
Fig. 2 is a schematic cross-sectional material diagram of a MOSFET device in the prior art.
Fig. 3 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present application.
Fig. 4 is a schematic cross-sectional material diagram of a semiconductor device according to an embodiment of the present application.
Fig. 5 is an exemplary flowchart of a method for fabricating a semiconductor device in an embodiment of the present application.
Fig. 6 is a schematic cross-sectional view corresponding to S101 in the embodiment of the present application.
Fig. 7 is a schematic cross-sectional view of a passivation layer formed by high temperature oxidation of a polysilicon layer in an embodiment of the present application.
In the figure:
101-a substrate; 102-an epitaxial layer; 103-a second type well region; 104-a first type doped region; 105-gate oxide layer; 106 a contact layer; 107-a polysilicon layer; 108-a passivation layer; 109-a first interlayer dielectric layer; 110-a second interlayer dielectric layer; 111-a third interlayer dielectric layer; 112-a blocking dielectric layer; 113-a barrier metal layer; 114-a second metal layer; 115-p+ region; 116-a first metal layer.
Detailed Description
For the purposes of making the objects, technical solutions and advantages of the embodiments of the present application more clear, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments. The components of the embodiments of the present application, which are generally described and illustrated in the figures herein, may be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the present application, as provided in the accompanying drawings, is not intended to limit the scope of the application, as claimed, but is merely representative of selected embodiments of the application. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.
It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only to distinguish the description, and are not to be construed as indicating or implying relative importance.
It is noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.
In the description of the present application, it should be noted that, the terms "upper," "lower," "inner," "outer," and the like indicate an orientation or a positional relationship based on the orientation or the positional relationship shown in the drawings, or an orientation or a positional relationship conventionally put in use of the product of the application, merely for convenience of description and simplification of the description, and do not indicate or imply that the apparatus or element to be referred to must have a specific orientation, be configured and operated in a specific orientation, and therefore should not be construed as limiting the present application.
Some embodiments of the present application are described in detail below with reference to the accompanying drawings. The following embodiments and features of the embodiments may be combined with each other without conflict.
As described in the background art, the existing SiC MOSFET device has a problem of poor reliability in the case of a short circuit or a surge.
Please refer to fig. 1 and 2, which are schematic cross-sectional views of conventional MOSFET devices in the prior art. Wherein, in the device structure, the material of the interlayer dielectric layer is typically SiO 2 The material of the ohmic contact layer may be Ni. When the device has short circuit problem or generates large surge current, the device generates extremely high temperature, and once the temperature of the device is higher than 660 ℃ of the melting point of metal Al, the source metal Al of the SiC MOSFET can be caused to melt and react with other materials, such as an interlayer medium SiO 2 The ohmic contact layer reacts to influenceDevice reliability. And melting Al metal into liquid state, which causes abrupt change of thermal expansion coefficient and interlayer dielectric SiO 2 And huge stress is generated due to thermal mismatch, so that cracks are generated, melted Al infiltrates into the grid electrode through crack erosion, short circuit failure and surge failure are caused, and the reliability of the device is seriously affected.
In view of the above, the present application provides a semiconductor device, in which an interlayer stress buffer layer and a barrier layer are added to achieve interlayer stress buffer of a material and to avoid a reaction between metallic Al and materials of other levels.
The following is an exemplary description of a semiconductor device provided in the present application:
as an alternative implementation, referring to fig. 3, the semiconductor device includes: the epitaxial wafer comprises a first type epitaxial wafer, wherein a second type well region 103 and a first type doped region 104 positioned in the well region are arranged on the epitaxial wafer; a first metal layer 116 located on the back of the epitaxial wafer; a gate oxide layer 105 located on the front surface of the epitaxial wafer and in contact with the first type doped region 104; the contact layer 106 is positioned on the front surface of the epitaxial wafer and is positioned in a region except the gate oxide layer 105; a polysilicon layer 107 located on a side of the gate oxide layer 105 remote from the epitaxial wafer; a stress buffer layer located on a side of the polysilicon layer 107 remote from the epitaxial wafer; a barrier layer on a side of the stress buffer layer and the contact layer 106 away from the epitaxial wafer; a second metal layer 114 on a side of the barrier layer away from the epitaxial wafer; wherein the stress buffer layer is used to reduce the interlayer stress of the semiconductor device material and the barrier layer is used to isolate the second metal layer 114.
Compared with the traditional semiconductor device shown in fig. 1, in the semiconductor device provided by the application, the stress buffer layer and the barrier layer are additionally arranged, and the stress buffer layer can realize stress buffer of the semiconductor device, so that even when the second metal layer 114 melts due to high temperature, the stress between the second metal layer 114 and the interlayer dielectric layer can be relatively smaller, cracks are not easy to generate on the interlayer dielectric layer, and further, the situation that molten metal permeates into a grid through crack erosion is avoided. By providing the barrier layer, the second metal layer 114 can be prevented from being in direct contact with the interlayer dielectric layer and the ohmic contact layer 106, so that direct reaction between the second metal layer 114 and other materials in a high-temperature state is avoided, and the reliability of the semiconductor device in the high-temperature state is improved.
It should be noted that, the first type and the second type refer to N type and P type, and when the first type is N type, the second type is P type; when the first type is P-type, the second type is N-type. Referring to fig. 4, in this application, the first type is N-type and the second type is P-type.
On the basis, the substrate 101 and the epitaxial layer 102 can be made of N-type SiC materials, a P well region and a P+ region 115 are arranged on the epitaxial wafer, and a P well region and an N-type doped region are arranged in the P well region.
The gate oxide layer 105 is typically formed of a silicon dioxide material, and the N-doped polysilicon layer 107 is used as a conductive layer. In one implementation, the semiconductor device further includes a passivation layer 108 between the polysilicon layer 107 and the stress buffer layer. The passivation layer 108 may be a silicon dioxide layer, and illustratively, a silicon dioxide film is fabricated on the surface of the polysilicon layer 107 by using a high-temperature oxidation method. Therefore, the passivation layer 108 provided by the application is stronger in compactness, better in blocking characteristic, and capable of improving the effect of preventing ion contamination, and meanwhile, the residual internal stress after the polysilicon etching is released can be relieved at high temperature, so that the appearance of the device is stabilized.
As an implementation manner, the stress buffer layer may include a three-layer structure, that is, a first interlayer dielectric layer 109 located on a side of the gate oxide layer 105 away from the epitaxial wafer, a second interlayer dielectric layer 110 located on a side of the first interlayer dielectric layer 109 away from the epitaxial wafer, and a third interlayer dielectric layer 111 located on a side of the second interlayer dielectric layer 110 away from the epitaxial wafer. The first interlayer dielectric layer 109 and the second interlayer dielectric layer 110 are used for blocking water vapor and ions; the third interlayer dielectric layer 111 is used to reduce stress of the semiconductor device.
Wherein the first interlayer dielectric layer 109 comprises a silicon oxynitride layer, the second interlayer dielectric layer 110 comprises an HTO layer, and the third interlayer dielectric layer 111 comprises a BPSG layer.
It should be noted that, the first interlayer dielectric layer 109 is made of SiON material, the temperature in the preparation process is relatively low, the thickness is relatively thin, and the SiON material has good thermal stability, so that the film stress can be reduced; and SiON can effectively prevent upper layer B, P, na ions and water vapor from penetrating into the device region, and meanwhile, nitrogen atoms in the film play a passivation role, so that the interface characteristic can be improved, the magnitude order of hot carriers can be effectively reduced, the grid electrode of the substrate 101 and the gate oxide layer 105 are protected, the Vt stability of threshold voltage is improved, the failure rate of gate oxide is reduced, and the reliability of the device is improved.
The second interlayer dielectric layer 110 is a high temperature deposited HTO material, i.e., a high temperature oxide layer, which is also a silicon dioxide layer, and is formed by high temperature deposition of SiO 2 The film has better compactness and better effect of blocking water vapor and movable ions.
Here, it should be emphasized that, among three layers (the passivation layer 108, the first interlayer dielectric layer 109 and the second interlayer dielectric layer 110) that are in layer-by-layer contact, the passivation layer 108 is formed by high-temperature oxidation, the second interlayer dielectric layer 110 is formed by high-temperature deposition, and the first interlayer dielectric layer 109 is formed at a lower temperature, so that the three-layer structure forms a "sandwich" structure, so that the overall stress is lower, and the compactness of the passivation layer 108 and the second interlayer dielectric layer 110 is better, and by the arrangement of the three-layer structure, the blocking characteristic can be better.
The third interlayer dielectric layer 111 is a BPSG layer, namely borophosphosilicate glass, and has the characteristics of strong high-temperature flowing capability and small stress, so that the problem of interlayer dielectric layer crack penetration failure caused by high-temperature thermal mismatch stress during short circuit or under high surge current is solved, and the short circuit tolerance is improved.
Based on the above, in the three-layer stress buffer layer, the first interlayer dielectric layer 109 and the second interlayer dielectric layer 110 are mainly used for blocking water vapor and ions, and the third interlayer dielectric layer 111 is mainly used for reducing stress.
As one implementation, the barrier layer includes two layers, namely a barrier dielectric layer 112 located at one side of the stress buffer layer away from the epitaxial wafer, and a barrier metal layer 113 located at one side of the barrier dielectric layer 112 and the contact layer 106 away from the epitaxial wafer; wherein the barrier metal layer 113 is used to isolate the second metal layer 114 from the contact layer 106; the barrier dielectric layer 112 is used to isolate the barrier metal layer 113 from the stress buffer layer.
It can be understood that the materials of the barrier metal layer 113 and the barrier dielectric layer 112 are selected so that the barrier metal layer 113 and the second metal layer 114 and the contact layer 106 are not easy to react at high temperature, and the barrier dielectric layer 112 and the isolation barrier metal layer 113 and the third interlayer dielectric layer 111 are not easy to react at high temperature.
As an example, the material of the blocking dielectric layer 112 includes at least one of SiN, siCN, siNH, siCH, siCNH; the material of the barrier metal layer 113 includes at least one of TiN and TaN; the material of the contact layer 106 comprises Ni and the material of the second metal layer 114 comprises Al.
Based on the above structure, it can be understood that the barrier metal layer 113 is added between the second metal layer 114 and the interlayer dielectric layer to prevent aluminum and SiO at high temperature 2 Or NiSi x And (3) reacting. Meanwhile, the barrier metal layer 113 is also bonded with SiO under high temperature conditions 2 The possibility of reaction is increased, so that the blocking dielectric layer 112 is additionally arranged, isolation between the blocking metal layer 113 and the third interlayer dielectric layer 111 is realized, no reaction between adjacent layers of the semiconductor device is ensured under the high temperature condition, and the high temperature stability of the device is improved.
Through the semiconductor device that this application provided, can realize preventing the reaction of Al high temperature melting back and other materials, passivation protection effect is better, effectively prevents liquid Al under the high temperature to the erosion and infiltration of interlaminar medium, and overall structure's high temperature stress buffering is effectual simultaneously, can make the electrical property more stable, and gate oxide failure rate is lower to and improve the short circuit and the surge reliability of device.
Based on the above implementation, referring to fig. 5, an embodiment of the present application further provides a method for manufacturing a semiconductor device, where the method includes:
s101, providing a first type epitaxial wafer, wherein a second type well region 103 and a first type doped region 104 positioned in the well region are arranged on the epitaxial wafer;
s102, manufacturing a gate oxide layer 105 based on the region which is in contact with the first type doped region 104 and is on the front surface of the epitaxial wafer;
s103, manufacturing a polycrystalline silicon layer 107 based on one side of the gate oxide layer 105 away from the epitaxial wafer;
s104, manufacturing a stress buffer layer on the basis of one side, far away from the epitaxial wafer, of the polycrystalline silicon layer 107;
s105, etching and removing the redundant gate oxide layer 105 and the stress buffer layer;
s106, manufacturing a contact layer 106 based on the front surface of the epitaxial wafer and the area except the gate oxide layer 105;
s107, manufacturing a barrier layer on the basis of the stress buffer layer and one side, far away from the epitaxial wafer, of the contact layer 106;
s108, manufacturing a second metal layer 114 on the basis of the side, away from the epitaxial wafer, of the barrier layer;
s109, manufacturing a first metal layer 116 based on the back surface of the epitaxial wafer;
wherein the stress buffer layer is used to reduce the interlayer stress of the semiconductor device material and the barrier layer is used to isolate the second metal layer 114.
Wherein S105 includes:
manufacturing a first interlayer dielectric layer 109 based on the side of the gate oxide layer 105 away from the epitaxial wafer;
manufacturing a second interlayer dielectric layer 110 based on the side of the first interlayer dielectric layer 109 away from the epitaxial wafer;
manufacturing a third interlayer dielectric layer 111 based on the side of the second interlayer dielectric layer 110 away from the epitaxial wafer; wherein,,
the first interlayer dielectric layer 109 and the second interlayer dielectric layer 110 are used for blocking water vapor and ions; the third interlayer dielectric layer 111 is used to reduce stress of the semiconductor device.
S106 includes:
manufacturing a blocking dielectric layer 112 on the basis of one side of the stress buffer layer away from the epitaxial wafer;
a barrier metal layer 113 is manufactured on the basis of the barrier dielectric layer 112 and the side, far away from the epitaxial wafer, of the contact layer 106; wherein,,
the barrier metal layer 113 is used to isolate the second metal layer 114 from the contact layer 106;
the barrier dielectric layer 112 is used to isolate the barrier metal layer 113 from the stress buffer layer.
Specifically, referring to fig. 6, a first type epitaxial wafer is provided, where the first type is N-type and the second type is P-type. In a specific process, the epitaxial layer 102 is grown along the surface of the substrate 101, then ion implantation is performed in a specific region of the epitaxial layer 102 to form the second type well region 103, then ion implantation is performed in the second type well region 103, further the first type doped region 104 is formed in the second type well region 103, and the second type doped region, that is, the p+ region 115 is formed in the second type well region 103, and then a high temperature annealing process is performed.
Thereafter, a gate oxide layer 105 and a polysilicon layer 107 are formed on the epitaxial wafer. Also, referring to fig. 7, a passivation layer 108 is formed on the polysilicon surface by a polysilicon oxidation process. The high-temperature oxide layer can passivate the protective grid; and the residual internal stress of the etched polysilicon can be released at high temperature, so that the appearance of the device is stabilized.
Then, when the stress buffer layer is manufactured, the thickness of the first interlayer dielectric layer 109 can be 400-500 angstrom, the material can be SiON, and SiH is subjected to chemical reaction 4 +N 2 O+He is formed by reaction.
For the second interlayer dielectric layer 110, its thickness may be 7000 to 8000 angstroms, the material may be HTO, and the second interlayer dielectric layer is formed by high temperature deposition, specifically, DCS (SiH 2 Cl 2 ) +n2o is formed by high temperature deposition.
The thickness of the third interlayer dielectric layer 111 may be 8000-9000 angstrom, and the material may be BPSG through TEOS+O 3 +TEB +TEPO. In the subsequent treatment, the mixture may be heated to 660 ℃ and then treated with N 2 And carrying out reflow planarization treatment on the BPSG under the atmosphere. The BPSG has strong high-temperature flow capability and small stress, reduces the problem of ILD crack penetration failure caused by high-temperature mismatch stress during short circuit or under high surge current, and improves the short circuit tolerance.
And etching and removing the redundant gate oxide layer 105 and the stress buffer layer, and manufacturing a contact layer 106 based on the front surface of the epitaxial wafer and the area except the gate oxide layer 105.
Next, a PECVD process is used to fabricate a 1000-2000 angstrom barrier dielectric layer 112 comprising SiN/SiCN/SiNH/SiCH/SiNH. And then a PVD process is adopted to manufacture a 2000-3000 angstrom barrier metal layer 113, finally a PVD process is adopted to deposit 4000-5000 angstrom metal aluminum as a second metal layer 114, and a first metal layer 116 is manufactured based on the back surface of the epitaxial wafer, wherein the first metal layer 116 is used as a device drain electrode.
In summary, the present application provides a semiconductor device and a method for manufacturing a semiconductor device, where the semiconductor device includes a first type epitaxial wafer, where a second type well region 103 and a first type doped region 104 located in the well region are disposed on the epitaxial wafer, a first metal layer 116 located on the back of the epitaxial wafer, a gate oxide layer 105 located on the front of the epitaxial wafer and in contact with the first type doped region 104, a contact layer 106 located on the front of the epitaxial wafer and in a region other than the gate oxide layer 105, a polysilicon layer 107 located on a side of the gate oxide layer 105 away from the epitaxial wafer, a stress buffer layer located on a side of the polysilicon layer 107 away from the epitaxial wafer, a barrier layer located on a side of the stress buffer layer and the contact layer 106 away from the epitaxial wafer, and a second metal layer 114 located on a side of the barrier layer away from the epitaxial wafer; wherein the stress buffer layer is used to reduce the interlayer stress of the semiconductor device material and the barrier layer is used to isolate the second metal layer 114. Because this application has add barrier layer and stress buffer layer on traditional device structure, and barrier layer and stress buffer layer can play the effect of reducing the interlaminar stress of device material and keeping apart second metal layer 114, consequently when short circuit or surge condition appear, the condition of crackle or inefficacy is difficult to appear, has promoted the reliability of device under short circuit or surge condition.
The foregoing description is only of the preferred embodiments of the present application and is not intended to limit the same, but rather, various modifications and variations may be made by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application should be included in the protection scope of the present application.
It will be evident to those skilled in the art that the present application is not limited to the details of the foregoing illustrative embodiments, and that the present application may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The present embodiments are, therefore, to be considered in all respects as illustrative and not restrictive, the scope of the application being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.
Claims (9)
1. A semiconductor device, the semiconductor device comprising:
a first type epitaxial wafer, wherein a second type well region (103) and a first type doped region (104) positioned in the well region are arranged on the epitaxial wafer;
a first metal layer (116) located on the back side of the epitaxial wafer;
the grid oxide layer (105) is positioned on the front surface of the epitaxial wafer and is in contact with the first type doped region (104);
a contact layer (106) located on the front surface of the epitaxial wafer and in a region other than the gate oxide layer (105);
a polysilicon layer (107) positioned on one side of the gate oxide layer (105) away from the epitaxial wafer;
a stress buffer layer positioned on one side of the polycrystalline silicon layer (107) away from the epitaxial wafer;
a barrier layer positioned on one side of the stress buffer layer and the contact layer (106) away from the epitaxial wafer;
a second metal layer (114) located on a side of the barrier layer away from the epitaxial wafer; wherein,,
the stress buffer layer is used for reducing interlayer stress of the semiconductor device material, and the barrier layer is used for isolating the second metal layer (114);
the stress buffer layer includes:
a first interlayer dielectric layer (109) positioned on one side of the gate oxide layer (105) far away from the epitaxial wafer;
a second interlayer dielectric layer (110) positioned on one side of the first interlayer dielectric layer (109) away from the epitaxial wafer;
a third interlayer dielectric layer (111) located on one side of the second interlayer dielectric layer (110) away from the epitaxial wafer; wherein,,
the first interlayer dielectric layer (109) and the second interlayer dielectric layer (110) are used for blocking water vapor and ions; the third interlayer dielectric layer (111) is used for reducing stress of the semiconductor device.
2. The semiconductor device of claim 1, wherein the first interlayer dielectric layer (109) comprises a silicon oxynitride layer, the second interlayer dielectric layer (110) comprises an HTO layer, and the third interlayer dielectric layer (111) comprises a BPSG layer.
3. The semiconductor device of claim 1, wherein the barrier layer comprises:
a blocking dielectric layer (112) positioned on one side of the stress buffer layer away from the epitaxial wafer;
a blocking metal layer (113) located on one side of the blocking dielectric layer (112) and the contact layer (106) away from the epitaxial wafer; wherein,,
the barrier metal layer (113) is used for isolating the second metal layer (114) from the contact layer (106);
the barrier dielectric layer (112) is used for isolating the barrier metal layer (113) from the stress buffer layer.
4. The semiconductor device of claim 3, wherein the material of the blocking dielectric layer (112) comprises at least one of SiN, siCN, siNH, siCH, siCNH; the material of the barrier metal layer (113) comprises at least one of TiN and TaN; the material of the contact layer (106) comprises Ni and the material of the second metal layer (114) comprises Al.
5. The semiconductor device according to claim 1, wherein the semiconductor device further comprises:
a passivation layer (108) located between the polysilicon layer (107) and the stress buffer layer.
6. The semiconductor device of claim 1, wherein the first type is N-type and the second type is P-type; or alternatively, the first and second heat exchangers may be,
the first type is P type, and the second type is N type.
7. A method for manufacturing a semiconductor device according to any one of claims 1 to 6, comprising:
providing a first type epitaxial wafer, wherein a second type well region (103) and a first type doped region (104) positioned in the well region are arranged on the epitaxial wafer;
-fabricating a gate oxide layer (105) based on a region of the front surface of the epitaxial wafer in contact with the first type doped region (104);
manufacturing a polysilicon layer (107) on the basis of the side, away from the epitaxial wafer, of the gate oxide layer (105);
fabricating a stress buffer layer based on a side of the polysilicon layer (107) away from the epitaxial wafer;
etching and removing the redundant gate oxide layer (105) and the stress buffer layer;
manufacturing a contact layer (106) based on the front surface of the epitaxial wafer and the region except the gate oxide layer (105);
fabricating a barrier layer based on the stress buffer layer and a side of the contact layer (106) away from the epitaxial wafer;
fabricating a second metal layer (114) based on a side of the barrier layer away from the epitaxial wafer and a first metal layer (116) based on a back side of the epitaxial wafer; wherein,,
the stress buffer layer is used for reducing interlayer stress of the semiconductor device material, and the barrier layer is used for isolating the second metal layer (114).
8. The method of manufacturing a semiconductor device according to claim 7, wherein the step of manufacturing a stress buffer layer based on a side of the polysilicon layer (107) remote from the epitaxial wafer comprises:
manufacturing a first interlayer dielectric layer (109) on the basis of one side, far away from the epitaxial wafer, of the gate oxide layer (105);
manufacturing a second interlayer dielectric layer (110) on the basis of the side, away from the epitaxial wafer, of the first interlayer dielectric layer (109);
manufacturing a third interlayer dielectric layer (111) on the basis of one side, far away from the epitaxial wafer, of the second interlayer dielectric layer (110); wherein,,
the first interlayer dielectric layer (109) and the second interlayer dielectric layer (110) are used for blocking water vapor and ions; the third interlayer dielectric layer (111) is used for reducing stress of the semiconductor device.
9. The method of manufacturing a semiconductor device according to claim 7, wherein the step of manufacturing a barrier layer based on the stress buffer layer and a side of the contact layer (106) away from the epitaxial wafer comprises:
manufacturing a blocking dielectric layer (112) on the basis of one side of the stress buffer layer away from the epitaxial wafer;
manufacturing a barrier metal layer (113) on the basis of the barrier dielectric layer (112) and the side, far away from the epitaxial wafer, of the contact layer (106); wherein,,
the barrier metal layer (113) is used for isolating the second metal layer (114) from the contact layer (106);
the barrier dielectric layer (112) is used for isolating the barrier metal layer (113) from the stress buffer layer.
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