JP2011129750A - Method of manufacturing high breakdown voltage semiconductor element and structure thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a high breakdown voltage semiconductor element which is improved in adhesion between an interlayer insulating film of the high breakdown voltage semiconductor element and a metal film formed on the interlayer insulating film, and a structure thereof. <P>SOLUTION: The method of manufacturing the high breakdown voltage semiconductor element includes steps of forming an MOS 2 on the surface of a semiconductor substrate 1, forming an interlayer insulating film 3 on the semiconductor substrate having the MOS 2, forming a silicon film 4 on the interlayer insulating film, forming a silicon oxide film 5 by oxidizing the deposited silicon film 4 in an oxidizing atmosphere having a predetermined temperature, forming an opening which penetrates the silicon oxide film 5 and the interlayer insulating film 3, and making the metal film 6 adhere to the silicon oxide film and the interior of the opening and forming the electrode film 7 on the metal film 6. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a high voltage semiconductor element and its structure, and more particularly to a method for manufacturing a high voltage semiconductor element having improved adhesion between an interlayer insulating film of the high voltage semiconductor element and a metal film formed thereon. And its structure.

  High voltage semiconductor devices used in switching power supplies, inverter devices, etc. are power MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) to achieve high-speed switching characteristics and low on-voltage in response to demands for high efficiency and miniaturization of devices. Further improvements have been made from SIT (Static Induction Thyristor) to IGBT (Insulated Gate Bipolar Transistor). In these conventional devices, optimization of the structure is energetically advanced.

  In such a situation, in a structure in which a silicon oxide insulating film such as an interlayer insulating film (BPSG film) is formed on a silicon substrate and an Al-based electrode wiring is provided, diffusion occurs at the interface between the insulating film and the electrode wiring. A barrier layer, that is, a barrier metal film (metal film) is laminated.

  However, since this barrier metal film has a double film structure of a Ti film and a TiN film, heat treatment for reducing contact resistance, or heat, pressure, vibration, etc. on the lead wire on the electrode wiring side, etc. Due to the external force, peeling occurs near the interface between the BPSG film and the barrier metal film.

  Further, since the interlayer insulating film is formed by CVD or the like, the film density is low. In particular, in the case of a BPSG film, the impurity concentration of boron and phosphorus contained therein is high. Therefore, the adhesive force with the metal film laminated | stacked on an upper layer becomes low. If this adhesion force is low, there is a problem that peeling occurs when a physical force is applied in a subsequent process such as dicing or bonding.

As a result, a defective bonding or a peeled pattern on the dicing line becomes a foreign substance, which deteriorates the quality of the product.
For this reason, there is a semiconductor device disclosed in Patent Document 1, for example, because it is necessary to improve the adhesion of the barrier metal film on the insulating film.

This semiconductor device includes a silicon oxide insulating film on a semiconductor substrate, a metal silicide film formed thereon, a barrier metal film on the metal silicide film, and an electrode wiring formed thereon. ing. The metal silicide film is a Ti-Si compound film, and the barrier metal film is formed of either a TiN / Ti film or a TiN film.
For this reason, the barrier metal film adheres to the BPSG film with the Ti-Si film interposed therebetween, and does not directly adhere to the BPSG film, so that peeling near the interface can be prevented.

  In Patent Document 2, a thin film made of an Al-based metal is formed by a sputtering method in a recess such as a hole or a groove formed on a substrate of a semiconductor device, and then a high-temperature and high-pressure treatment is performed to place the Al-based metal in the recess. In the semiconductor device, the wiring of the semiconductor device is filled and the electrical resistivity is low, and the denseness of the film and the adhesion with the insulating film are improved.

  Patent Document 3 discloses a method of forming a metal barrier with improved adhesion of a barrier layer to a dielectric on a base by forming an adhesion / interlayer region of a semiconductor element before depositing the barrier layer. ing.

  In this method, before sputtering metal on a semiconductor substrate element, a silicon plasma is used to form a bonding region on the dielectric layer of the semiconductor substrate element so that nitrogen plasma or alternatively a process gas ion of an argon and nitrogen mixture is mixed with silicon dioxide. : A nitrogen adhesion region or an intermediate layer is formed on the surface of the dielectric layer. The thin adhesion / interlayer region of this treated ILD can act as an adhesion interface, resulting in an improved adhesion function at the surface of the dielectric layer.

  Then, after forming the adhesion / interlayer region, a refractory metal barrier layer such as tantalum, titanium, or tungsten is sputtered onto the surface of the semiconductor substrate element.

  In the embodiment of Patent Document 3, an inlaid interconnect structure 400 of a conductive layer 402 of a semiconductor substrate element is formed through an interlayer dielectric layer (ILD) 404 as shown in FIG. The interlayer dielectric layer 404 has a trench 408 formed by etching or the like, and an opening 406 that penetrates the ILD layer 402 and reaches the conductive layer 402 is formed in the trench. Further, as shown in FIG. 2B, a thin adhesion / interlayer region 410 is formed on the surface of the dielectric layer 404, and then a barrier layer 412 is formed.

Japanese Patent Laid-Open No. 06-314722 JP 2005-340640 A JP 2001-230256 A

  In the prior art, for example, a Ti—Si film is interposed between the interlayer insulating film and the barrier metal film to improve the adhesion, but such a Ti—Si alloy film, that is, a silicide alloy film, is used. The processability of the silicide film causes a decrease in wiring reliability and a deterioration in electrical connectivity with the lower layer wiring.

  The reason is that the processing of metal silicide has the property that it is difficult to dry-etch, and this compound remains in the place to be removed, and these have conductivity, which may deteriorate the reliability of wiring etc. There is.

In addition, the metal wiring needs to be electrically connected to a lower layer wiring or a silicon substrate. In the conventional method, it is necessary to obstruct or select a more complicated process. For example, in the case of bonding to a silicon substrate, an impurity that becomes P-type (boron or the like) is deposited on a deposited silicon layer, a P-type semiconductor layer, and an N-type semiconductor layer so as not to be a Schottky junction. N-type impurities (phosphorus, arsenic, etc.) must be introduced in advance.
Further, since the titanium silicide layer is interposed between the wirings at the junction with the lower metal wiring, the resistance of the metal wiring is increased.

  In addition, the interlayer insulating film generally has a low film density, and particularly in the case of a BPSG film, since the impurity concentration of boron and phosphorus contained in the film is high, the adhesion with the metal film formed thereover is high. Low. Further, a silicon oxide film formed by CVD such as an interlayer insulating film has a low film density.

  When the adhesion is reduced in this way, the silicon oxide film and the metal film are peeled off during the subsequent dicing or bonding process, and the bonding failure or the part where the pattern on the dicing line is peeled off becomes a foreign substance, resulting in a high withstand voltage. The quality of the semiconductor element is degraded.

  Further, in the formation of the adhesion / interlayer region disclosed in Patent Document 3 described above, the processing can be continuously performed in the apparatus for forming the barrier metal, but the formed adhesion / interlayer region is interdiffusion of dielectric material. Therefore, it may be conductive. Further, as described above, it becomes a problem of reliability of wiring and the like. In the present invention, the effect of improving the adhesion is expected to be due to the modification of the resurface layer of the underlayer or the effect of a small amount of deposits, such as tantalum (Ta) having weak adhesion to the silicon oxide film. This is considered to be one of attempts to improve the adhesion to metal.

  The present invention has been made in view of the above-described problems, and acts on a subsequent processing step of forming a metal layer and an electrode by oxidizing a silicon film once formed on an interlayer insulating film. It is an object of the present invention to provide a method for manufacturing a high voltage semiconductor device that maintains high adhesion to force and a structure thereof.

In order to achieve the above object, a method of manufacturing a high voltage semiconductor device according to claim 1 comprises:
Forming a MOS part on the surface of the semiconductor substrate;
Forming an interlayer insulating film on the semiconductor substrate having the MOS portion;
Forming a silicon film on the interlayer insulating film;
In a oxidizing atmosphere at a predetermined temperature, the silicon film formed is oxidized to form a silicon oxide film,
Forming an opening penetrating the silicon oxide film and the interlayer insulating film;
The method includes the steps of depositing a metal film on the silicon oxide film and in the opening and forming an electrode film on the metal film.

In addition, a method for manufacturing a high voltage semiconductor element according to claim 2 comprises:
Forming a MOS part having a planar or trench type gate structure on the surface of the semiconductor substrate;
Forming an interlayer insulating film on the semiconductor substrate having the MOS portion;
A silicon film is formed on the interlayer insulating film by CVD or sputtering,
In a oxidizing atmosphere at a predetermined temperature, the silicon film formed is oxidized to form a silicon oxide film,
Forming an opening penetrating the silicon oxide film and the interlayer insulating film;
The method includes the steps of depositing a metal film on the silicon oxide film and in the opening and forming an electrode film on the metal film.

  According to a preferred configuration of claim 3, the predetermined temperature of the oxidizing atmosphere is at least 750 ° C. or higher.

  According to the configuration described in claim 4, the metal film includes titanium nitride, titanium, tantalum, tantalum nitride, a laminated film of titanium nitride and tantalum (TiN / Ti), and a laminated film of tantalum nitride and titanium (TaN / Ti). It is selected from the group of.

Furthermore, the structure of the high breakdown voltage semiconductor element according to claim 5 is a MOS part having a planar or trench type gate structure formed on the surface of a semiconductor substrate.
An interlayer insulating film formed on the semiconductor substrate having the MOS portion;
A silicon oxide film formed by oxidizing a silicon film formed on the interlayer insulating film in an oxidizing atmosphere at a predetermined temperature;
Forming an opening penetrating the silicon oxide film and the interlayer insulating film, a metal film deposited on and in the silicon oxide film, and
It has an electrode film formed on the upper layer of the metal film.

  According to the first aspect of the present invention, after forming a silicon film on the interlayer insulating film formed on the semiconductor substrate, the silicon film is oxidized in an oxidizing atmosphere, so that the film density is high and the impurities are A dense silicon oxide film having a low concentration is formed. As a result, the bonding surface between the silicon oxide film and the metal film has a high film density and a low impurity concentration, so that the metal film secures a high adhesion to the base and prevents quality deterioration due to the low adhesion. Can do.

  According to a second aspect of the present invention, in the high breakdown voltage semiconductor device having a trainer gate type or trench gate type MOS structure, a silicon film is formed on the interlayer insulating film by CVD or sputtering, and a process after the silicon oxide film is formed. That is, it is possible to maintain adhesion to the metal film without peeling off against a very large force such as dicing or bonding, and to improve the adhesion to the strength (about 1 GPa) at which the silicon oxide film breaks. Can do.

  According to the invention of claim 3, the predetermined temperature of the oxidizing atmosphere is at least 750 ° C. or higher as compared with the temperature of about 400 ° C. to 500 ° C. in the conventional CVD method, and the film forming gas component remains. In the process of oxidizing the deposited silicon, the silicon structure is recombined, the crystallization proceeds, and a silicon oxide film having a high film density can be formed.

  According to the invention of claim 4, the metal film can be selected from titanium, tantalum, and compounds thereof, and various metal films can be used for bonding with the interlayer insulating film.

  According to the invention of claim 5, a silicon film is formed on the interlayer insulating film, and this film is oxidized to form a silicon oxide film, which is crystallized between the interlayer insulating film and the metal film. Since an insulating film having a high film density is formed, the structure of a high voltage semiconductor device with improved adhesion to the metal film can be obtained, and the purpose is to insulate the metal film from the trench gate of the MOS portion. The film thickness of the interlayer insulating film can be reduced.

FIGS. 2A and 2B show a process procedure of an embodiment according to the present invention, in which FIG. 1A is a cross-sectional view showing a completed state of formation of a silicon film, and FIG. It is a sectional view, and (c) is a sectional view showing a completed state of barrier metal and electrode film formation. (a) is a cross-sectional view in which an opening and a trench are formed in a conventional interconnect structure, and (b) is a cross-sectional view of an interconnect structure in which a metal layer is formed on an adhesion / interlayer region.

  In the present invention, a barrier metal film is formed on a silicon oxide film formed by forming a silicon film on an interlayer insulating film (such as BPSG) of a high voltage semiconductor element by a CVD process or the like and oxidizing the formed silicon film. (Titanium / TiN) and an electrode film (aluminum) are provided.

Embodiments of the present invention will be described below with reference to the drawings.
A representative view of the present invention is shown in FIG. FIGS. 1A to 1C are cross-sectional views of a manufacturing process of an insulated gate bipolar transistor 10 (IGBT) as a high breakdown voltage semiconductor element. The semiconductor substrate 1 and the MOS portion 2 (trench gate 2 ′) are sequentially formed from the lower layer. ), Formation of interlayer insulating film 3, silicon film 4, contact pattern, silicon oxide film 5, metal film (barrier metal film) 6, and electrode film 7 until the completion of filling.

FIG. 1A shows a completed state of the formation of the trench gate 2 ′, the interlayer insulating film 3, and the formation of the silicon film 4.
In this step, first, the MOS portion 2 having a gate structure of, for example, a planar gate or a trench gate is formed on the semiconductor substrate 1. FIG. 1 shows a trench gate.

  Next, an interlayer insulating film 3 made of a silicon oxide film is formed on the semiconductor substrate 1. The interlayer insulating film 3 is for insulating the semiconductor substrate 1 and the electrode film 7.

For example, when the chemical vapor deposition method (CVD) is used, the interlayer insulating film 3 is formed by using a gas having a growth temperature of 450 ° C. and a composition of SiH ₄ / PH ₃ / B ₃ H ₆ and B (boron). ) When the concentration = 2.6% and the P (phosphorus) concentration = 6.0%, a BPSG film having a thickness of 5000 mm is formed.

In this step, for example, the silicon film 5 is formed using SiH ₄ / N ₂ O and a pressure of 1.5 Torr as a working gas. In the above embodiment, the silicon film 4 is formed by using the CVD method, but the silicon film 4 can also be formed by the sputtering method as another method.
The interlayer insulating film is formed of, for example, a silicon oxide film, a silicon nitride film, BSG, PSG, or BPSG. Thus, the interlayer insulating film can be configured as an insulating film having various characteristics.

FIG. 1 (b) shows that silicon formed earlier after FIG. 1 (a) in an atmosphere of at least 750 ° C. or more, particularly an oxygen atmosphere (O ₂ ), preferably in an oxidizing atmosphere of 950 ° C. or more. A state in which the film 4 is oxidized to form a silicon oxide film 5 is shown.

Oxidizing atmosphere, there are various types, set temperature, for example, in an atmosphere with oxygen (O _2), 850 ℃ above, an atmosphere of hydrogen and oxygen (H _2, O ₂₎ at, 750 ° C. or higher, ozone atmosphere (O ₃ ) is 400 ° C. or higher.

In the oxidizing atmosphere of the present invention, the set temperature in the oxidation formation of the processing gas and the silicon film differs depending on the oxidizing power of the atmosphere, so that the temperature (energy) required for the reaction to proceed is different, so the lower limit temperature differs depending on the oxidizing atmosphere. .
In addition, although the upper limit temperature is not particularly defined, it is generally 1200 ° C. or less in current facilities because it accelerates the deterioration of the oxidation treatment apparatus and its components.

  The film thickness of the silicon oxide film 5 to be formed varies depending on the subsequent thermal history in order to prevent the diffusion of impurities when, for example, a large amount of impurities such as a BPSG film is included. For example, the heat treatment at 950 ° C. for 60 minutes requires 10 nm or more. The upper limit of the film thickness is not particularly limited, and is determined by an appropriate set temperature and processing time.

In the present invention, the set temperature in the oxidizing atmosphere is higher than that in the case where the silicon oxide film is formed by the CVD method, and the silicon oxide film obtained by crystallizing the silicon film with higher adhesion is formed by the oxidation treatment. be able to.
In the present invention, since the silicon oxide film is formed of the same insulator as the interlayer insulating film (BPSG or the like), a conductive material or the like is to be removed by a process such as etching, as in a conventional metal silicide alloy film. Therefore, the reliability of the subsequent wiring can be maintained.

FIG. 1C shows a desired portion of the silicon oxide film 5 and the interlayer insulating film 3 after the formation of FIG. 1B, that is, after the formation of the silicon oxide film 5, using a photolithography technique and a dry etching technique. The figure shows a state where a metal film 6 (barrier metal, for example, titanium / TiN) and an electrode film 7 (aluminum) are formed after being opened through.
As the metal film, titanium nitride, titanium, tantalum, tantalum nitride, a laminated film of titanium nitride and tantalum (TiN / Ti), or a laminated film of tantalum nitride and titanium (TaN / Ti) is selected.

  Further, as a method for forming an electrode such as a high voltage MOS, a sputtering method is used, and the following two structures are generally used as the structure of the electrode film 7.

(1) Al-Si (1%) single layer structure About 1 weight percent of silicon is contained in aluminum, and good ohmic characteristics are obtained while suppressing aluminum diffusion into excess silicon.

(2) Al / TiN / Ti laminated structure A TiN / Ti film called a barrier metal prevents Al diffusion into silicon and forms an alloy layer of titanium and silicon to obtain good ohmic characteristics.

  The adhesion between the metal film 6 by sputtering and the silicon oxide film 5 is a weak bond due to an intermolecular force or the like, unlike a chemical bond with a high adhesion. In particular, if the oxide film has a low film density such as a CVD film, the adhesion is further reduced.

  However, according to the present invention, since the silicon oxide film 5 is formed by oxidizing the silicon film 4 formed on the interlayer insulating film 3 in the oxidizing atmosphere, the bonding surface between the silicon oxide film 5 and the metal film 6 is formed. High adhesion can be secured. For this reason, after that, in the subsequent process of applying physical force such as opening to the interlayer insulating film 3 and electrode formation, that is, dicing or bonding, peeling of the metal film 6 is suppressed, and the quality is high. A structure of a high voltage semiconductor element can be made.

The procedure of the manufacturing process in the present invention is performed as follows, for example.
(a) A planar gate or trench gate MOS structure is formed on the surface of a semiconductor substrate.
(b) A silicon oxide film (interlayer insulating film) for the purpose of insulating the semiconductor substrate and the electrode is formed.
(c) A silicon film is formed on the interlayer insulating film using CVD or sputtering.
(d) The previously formed silicon film is oxidized in an oxidizing atmosphere at an ambient temperature of about 950.degree.
(e) A contact pattern is formed using a photo method and processed using an etching method.
(f) A titanium and titanium nitride film (barrier metal) is formed.
(g) An aluminum electrode film is formed by sputtering or the like (FIG. 1C), and wiring is patterned by using a photo and etching method.
(h) After the wiring process is completed, a passivation film for forming a film is formed and processed in order to protect the surface from external damage.

  Such a manufacturing method of the present invention can be used as a method for forming an insulating film under a high-voltage semiconductor device, particularly an insulated gate bipolar transistor (IGBT) and a power MOS, and a diode electrode.

  As described above, according to the present invention, a silicon film is formed on an interlayer insulating film, and the silicon oxide film is formed by oxidizing the silicon film. Therefore, silicon is directly formed on the interlayer insulating film by a conventional CVD method. Compared with the case of forming an oxide film, a silicon oxide film formed by oxidation in an oxidizing atmosphere undergoes recombination of the silicon structure during the oxidation process, crystallization proceeds, and the silicon film in the oxidizing atmosphere The hydrogen inside reacts with oxygen and is discharged as water vapor. As a result, a substantially crystallized silicon oxide film having a high film density can be formed. Since the high film density is directly linked to the high adhesion, this point is advantageous.

  1: Semiconductor substrate, 2: MOS part, 3: Interlayer insulating film, 4: Silicon film, 5: Silicon oxide film, 6: Metal film (barrier metal film), 7: Electrode film, 10: IGBT,

Claims (5)

Forming a MOS part on the surface of the semiconductor substrate;
Forming an interlayer insulating film on the semiconductor substrate having the MOS portion;
Forming a silicon film on the interlayer insulating film;
In a oxidizing atmosphere at a predetermined temperature, the silicon film formed is oxidized to form a silicon oxide film,
Forming an opening penetrating the silicon oxide film and the interlayer insulating film;
A method of manufacturing a high voltage semiconductor device, comprising: a step of depositing a metal film on the silicon oxide film and in the opening, and forming an electrode film on the metal film. Forming a MOS part having a planar or trench type gate structure on the surface of the semiconductor substrate;
Forming an interlayer insulating film on the semiconductor substrate having the MOS portion;
A silicon film is formed on the interlayer insulating film by CVD or sputtering,
In a oxidizing atmosphere at a predetermined temperature, the silicon film formed is oxidized to form a silicon oxide film,
Forming an opening penetrating the silicon oxide film and the interlayer insulating film;
A method of manufacturing a high voltage semiconductor device, comprising: a step of depositing a metal film on the silicon oxide film and in the opening, and forming an electrode film on the metal film.   The manufacturing method according to claim 1, wherein the predetermined temperature of the oxidizing atmosphere is a high temperature of at least 750 ° C. or more.   The metal film is selected from the group consisting of titanium nitride, titanium, tantalum, tantalum nitride, a laminated film of titanium nitride and tantalum (TiN / Ti), and a laminated film of tantalum nitride and titanium (TaN / Ti). The manufacturing method according to any one of claims 1 to 3. A MOS part having a planar or trench type gate structure formed on the surface of a semiconductor substrate;
An interlayer insulating film formed on the semiconductor substrate having the MOS portion;
A silicon oxide film formed on the interlayer insulating film by oxidizing the silicon film formed on the interlayer insulating film in an oxidizing atmosphere at a predetermined temperature;
Forming an opening penetrating the silicon oxide film and the interlayer insulating film, a metal film deposited on and in the silicon oxide film, and
A structure of a high voltage semiconductor element, comprising an electrode film formed on an upper layer of the metal layer.

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