JP2012039019A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enhance yield and reliability of a semiconductor device by improving embedment of Cu in a Cu interconnection without sacrifice of the diffusion prevention function of a barrier film in a Cu interconnection having a damascene structure.SOLUTION: In a semiconductor device having a damascene structure, a TaN film 7 and a Ti film 8 composed of Ti exhibiting good wettability to Cu are formed respectively, as a barrier layer, on the inside walls of a wiring groove G2 and a via hole V2 formed in a second interlayer insulating film 6, so that a Cu seed film 9a can be formed uniformly on the Ti film 8. Consequently, an air gap can be prevented from being formed in the wiring groove G2 and via hole V2 when a Cu film 9 is formed by electric field plating using the Cu seed film 9a as an electrode.

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a technique effective when applied to a semiconductor device having a copper wiring and a manufacturing method thereof.

  In the advanced LSI (Large Scale Integration), the wiring material used for the purpose of supplying a predetermined potential to a semiconductor element or transmitting an electric signal is made of Al (aluminum) for the purpose of reducing the resistance of the wiring. Cu (copper) has come to be widely used instead of alloy materials (such as Al—Cu alloys) mainly composed of a). By introducing copper, in the wiring formation process, instead of directly processing the wiring material using dry etching, grooves and holes to be wiring and vias are formed in the interlayer insulating film in advance, and then the wiring material (for example, A so-called damascene method has been used in which Cu (copper)) is buried and an excess wiring material is removed by a CMP (Chemical Mechanical Polishing) method.

  In the Cu wiring structure, in order to prevent Cu (copper) from diffusing into the interlayer insulating film, it is necessary to cover the entire surface of the Cu wiring with a diffusion preventing film (barrier film, seed film). Normally, this barrier film uses a liner film which is an insulating film having a copper diffusion preventing function as an insulating film-based barrier material for the upper surface of the Cu wiring. This liner film is also used as a part of the interlayer insulating film above the Cu wiring. On the other hand, a barrier film made of a metal-based barrier material (barrier metal) is used for the side walls and bottom of the Cu wiring. Since the barrier metal is formed on the inner wall of the groove or via hole for wiring, it is used as a part of the wiring material.

  Currently, Ta (tantalum) and its compounds (for example, TaN) are widely used as barrier metals. This is because, generally, a barrier material mainly composed of Ta (tantalum) exhibits excellent prevention performance against copper diffusion.

  Japanese Patent Laid-Open No. 2004-79802 discloses a technique for suppressing an increase in resistance of a metal wiring layer due to a barrier film when the metal wiring layer is formed by a dual damascene method. Specifically, when forming a metal film to be a wiring on an organic interlayer insulating film made of an organic SOG (Spin On Glass) film, a metal carbide for preventing metal diffusion at the interface between the organic interlayer insulating film and the metal film. A film is formed as a barrier film. Accordingly, the ratio of the barrier film having a high resistance is reduced, and the resistance of the wiring layer can be lowered in a state where the barrier film has a sufficient metal diffusion preventing function.

  Here, TaC (tantalum carbide) is used as the metal film for the barrier film, but Ti (titanium) or nitride of Ti (titanium) may be used as the material for the barrier film. However, there is no description regarding the thickness of the Ti film used for the barrier film. Moreover, there is no description about the specific atomic ratio of Ti (titanium) and N (nitrogen) of the TiN film used for the barrier film. There is no description that Ti oxide is used as the material of the barrier film.

  In Patent Document 2 (Japanese Patent Laid-Open No. 2003-124313), in a multilayer wiring structure using Cu (copper) as a wiring material, while preventing contamination due to copper diffusion, adhesion to a lower wiring layer in a Cu via is disclosed. A technique for improving contact resistance and reducing contact resistance is disclosed. Specifically, a semiconductor device including a Cu wiring layer formed between interlayer insulating films by a dual damascene method, and a Cu via formed in a via hole opened in the interlayer insulating film and connected to the Cu wiring layer In this method, a TaN barrier film having adhesiveness with the interlayer insulating film and a Ta barrier film having adhesiveness with copper are laminated on the side surface of the Cu via, and only the Ta barrier film is formed on the bottom surface of the Cu via. Thereby, the Ta barrier film and the TaN barrier film prevent contamination due to diffusion of Cu, improve the adhesion between copper and the interlayer insulating film, and prevent the peeling of the Cu via. In addition, the adhesion between the bottom surface of the Cu via and the Cu wiring layer is increased, the movement of Cu atoms at the interface between the Cu via and the Cu wiring layer is suppressed, the electromigration resistance or the thermal stress resistance is increased, and the contact resistance is reduced. You can do that.

  Here, Ta (tantalum) and TaN (tantalum nitride) are used as the material of the barrier film, but a combination of Ti (titanium) and TiN (titanium nitride) may be used as the material of the barrier film. However, there is no description regarding the thickness of the Ti film used for the barrier film. Moreover, there is no description about the specific atomic ratio of Ti (titanium) and N (nitrogen) of the TiN film used for the barrier film. There is no description that Ti oxide is used as the material of the barrier film.

JP 2004-79802 A JP 2003-124313 A

  As described above, in recent years, in a semiconductor device such as an LSI having a wiring containing Cu (copper), a method of forming a barrier film containing Ta on the side wall and bottom surface of the Cu wiring is used to prevent diffusion of Cu. It is becoming.

  However, a barrier film containing Ta (tantalum) is not necessarily from the viewpoints of characteristics other than the diffusion preventing function required as a material of the metal (barrier metal) constituting the barrier film, and material costs to be noted in mass production. There are aspects that are hard to say as the best materials. For example, a barrier film containing Ta (tantalum) is a wiring material formed through a barrier film containing Ta (tantalum) in a wiring groove formed in the insulating film because the wettability with copper is not good. There is a problem that copper embedding is deteriorated and reliability is lowered.

  Here, the problem of the barrier film containing Ta (tantalum) described above will be described with reference to FIGS. 25 to 28, using Cu wiring when Ta (tantalum) and TaN (tantalum nitride) are formed as a barrier film as an example. To do. FIG. 25 is a fragmentary cross-sectional view showing the vicinity of a Cu wiring formed normally when Ta (tantalum) and TaN (tantalum nitride) are formed as a barrier film. 26 to 28 are cross-sectional views of the main part showing the manufacturing process of the dual damascene wiring when Ta (tantalum) and TaN (tantalum nitride) are formed as barrier films, respectively.

  In the semiconductor device shown in FIG. 25, wiring using a barrier metal material mainly composed of Ta (tantalum) is formed by a damascene method. That is, the semiconductor device shown as an example includes the lower interlayer wiring M1 formed by the single damascene method in the wiring groove G1 formed in the first interlayer insulating film 1 and the stopper insulating film Sf on the insulating film If, and the first interlayer insulating film. The via hole V2 formed in the liner film 5 and the second interlayer insulating film 6 on the film 1 and the wiring groove G2 formed in the second interlayer insulating film 6 are buried by the dual damascene method, and electrically connected to the lower layer wiring M1. And an upper layer wiring M2. The via hole V2 is a hole that opens at the bottom surface of the wiring groove G1 and reaches the upper surface of the lower layer wiring M1.

  The lower layer wiring M1 is mainly made of the Cu film 4, and a Ta film 3a made of Ta (tantalum) is formed between the Cu film 4 and the first interlayer insulating film 1, and the Ta film 3a and the first interlayer insulating film 1 are formed. Between the two, a TaN film 2a made of TaN (tantalum nitride) is formed. A Cu seed film 4a made of Cu (copper) is formed between the Cu film 4 and the Ta film 3a.

  Similarly, the upper wiring M2 is mainly made of the Cu film 9, and a Ta film 8a made of Ta (tantalum) is formed between the Cu film 9, the liner film 5 and the second interlayer insulating film 6, and the Ta film 8a. Between the liner film 5 and the second interlayer insulating film 6, a TaN film 7a made of TaN (tantalum nitride) is formed. A Cu seed film 9a made of Cu (copper) is formed between the Cu film 9 and the Ta film 8a. The lower layer wiring M1 is electrically connected to a semiconductor element formed on a lower semiconductor substrate than the first interlayer insulating film 1 through a contact plug Cp below the lower layer wiring M1.

  The cross-sectional view shown in FIG. 25 shows a Cu wiring in which the Ta film 8a, the TaN film 7a, the Cu seed film 9a, and the Cu film 9 are normally formed. At this time, no voids are formed in the Cu film 9, and the Cu film 9 is uniformly embedded in the wiring groove G2 and the via hole V2 via the barrier film and the Cu seed film 9a.

  However, the Ta films 3a and 8a and the TaN films 2a and 7a used as barrier films have poor wettability with the Cu seed film 9a, and the Cu seed film 9a is formed on the Ta film 8a in the wiring groove G2 and the via hole V2. It may not be uniformly formed on the surface.

  Here, FIG. 26 to FIG. 28 are cross-sectional views of main parts in the manufacturing process of the semiconductor device using a material containing Ta (tantalum) for the barrier film. In FIG. 26, after forming the lower layer wiring M1 on the upper surface of the first interlayer insulating film 1, the liner film 5 and the second interlayer insulating film 6 are formed on the first interlayer insulating film 1, and the liner film 5 and the second interlayer insulating film 1 are formed. The process of forming the TaN film 7a in the structure in which the via hole V2 penetrating the insulating film 6 is formed and the wiring groove G2 is formed is shown.

  As shown in FIG. 26, after a TaN film 7a and a Ta film 8a are sequentially formed by a PVD (Physical Vapor Deposition) method, a Cu seed film is deposited on the surface of the Ta film 8a by a PVD method. However, since Ta (tantalum) and Cu (copper) have poor wettability, the Cu seed film 9b does not extend uniformly on the surface of the Ta film 8a in the wiring groove G2 and the via hole V2, and becomes a plurality of masses. It is easy to be formed to be scattered.

  When the Cu seed film 9b is formed discontinuously in the wiring groove G2 and the via hole V2, the Cu film is formed on the Cu seed film by the electroplating method after the process of FIG. 26, as shown in FIG. As shown in FIG. 28, the void 11 is formed in the Cu film 9, or the void 11 is formed in the wiring groove G2 and the via hole V2, as shown in FIG. There is a risk that it will not be embedded in the bottom.

  After forming the Cu film 9 in the process shown in FIG. 27 or FIG. 28, the Cu film 9, the Cu seed film 9a, the Ta film 8a, and the TaN film 7a formed on the second interlayer insulating film 6 are removed by the CMP method. Then, the height of the upper surface of the Cu film 9 is aligned with the height of the upper surface of the second interlayer insulating film 6, and an upper wiring mainly composed of the Cu film 9 is formed. Thereafter, a liner film (not shown) and a third interlayer insulating film (not shown) are formed on the second interlayer insulating film 6 and the upper layer wiring, and a wiring is formed further above the upper layer wiring.

  Here, as described with reference to FIGS. 27 and 28, the Cu film 9 has poor embeddability because the Cu seed film formed discontinuously in the wiring groove G2 and the via hole V2 is used as an electrode. This is because is formed by electroplating. That is, since the Cu film 9 is formed on the surface of the Cu seed film 9a that becomes an electrode in the electroplating process, the Cu seed film 9a that is discontinuously formed on the surface of the Cu seed film 9b is formed on the surface. Cu film 9 is difficult to be formed. Therefore, as shown in FIG. 27 and FIG. 28, the air gap 11 is easily formed in the wiring groove G2 and the via hole V2, the upper layer wiring is interrupted in the middle, and the upper layer wiring and the lower layer wiring M1 are electrically connected. There is a possibility that a predetermined potential cannot be supplied from the upper layer wiring to the lower layer wiring M1 without being connected.

  Further, in the electroplating step for forming the Cu film 9, even if the Ta film 8a exposed from the Cu seed films 9a and 9b is energized and functions as an electrode, the Ta film 8a is compared with the surface of the Cu seed film 9a. Cu film 9 is difficult to be formed on the surface. This is because the resistance value of (tantalum) is higher than that of Cu (copper). As a result, the film thickness of the Cu film 9 formed in the wiring groove G2 and the via hole V2 is not uniform, and the void 11 is formed. It becomes easier to form.

  As described above, when a semiconductor device is manufactured using Ta (tantalum) as a barrier film for wiring, the yield and reliability of the semiconductor device are reduced due to the deterioration of the embedding property of the Cu wiring due to the wettability with the Cu seed film. descend.

  In addition, since Ta (tantalum) itself is a relatively expensive material, manufacturing a semiconductor device using Ta (tantalum) as a barrier film for wiring has a problem of increasing the cost of the product.

  From the above, the present inventors examined the use of Ti (titanium), which is excellent in wettability with copper, as a barrier metal instead of Ta (tantalum). However, since Ti (titanium) has the property of easily forming an alloy with copper, when a Ti film is formed as a barrier film, the resistance value is higher than that of pure copper at the interface between the Ti film and the Cu film. There is a problem that a Ti / Cu alloy film is formed and the wiring resistance is increased by the Ti / Cu alloy film.

  An object of the present invention is to improve the embedding property of a copper wiring in a semiconductor device having a wiring containing copper without reducing the diffusion preventing function of a barrier film formed on the surface of the copper wiring.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the embodiments disclosed in the present application, the outline of typical ones will be briefly described as follows.

A semiconductor device according to a preferred embodiment of the present invention includes:
An interlayer insulating film formed on the semiconductor substrate;
A wiring groove formed in the interlayer insulating film;
A metal film mainly composed of Cu formed in the wiring trench via the first barrier film;
Have
The first barrier film has a third barrier film containing Ta and a second barrier film containing Ti formed on the third barrier film in contact with the metal film.

A method for manufacturing a semiconductor device according to a preferred embodiment of the present invention includes:
(A) preparing a semiconductor substrate;
(B) forming an interlayer insulating film on the semiconductor substrate;
(C) forming a wiring groove on the upper surface of the interlayer insulating film;
(D) forming a first barrier film in the wiring trench;
(E) forming a seed film containing Cu as a main component on the surface of the first barrier film;
(F) forming a metal film containing Cu as a main component on the seed film by electroplating using the seed film as an electrode, and filling the wiring groove with the metal film;
(G) polishing an upper surface of the semiconductor substrate to expose an upper surface of the interlayer insulating film, and forming a metal wiring including the first barrier film and the metal film in the wiring groove;
Have
In the step (d), after forming a second barrier film containing Ta in the wiring trench, a second barrier film made of Ti or a Ti compound is formed on the second barrier film, whereby the second barrier film is formed. The first barrier film having a barrier film and the third barrier film is formed.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  According to a preferred embodiment of the present invention described above, in a semiconductor device having a wiring containing copper, the copper wiring can be embedded without deteriorating the diffusion preventing function of the barrier film formed on the surface of the copper wiring. Can be made.

It is principal part sectional drawing of the semiconductor device which is Embodiment 1 of this invention. It is principal part sectional drawing which shows the manufacturing method of the semiconductor device which is Embodiment 1 of this invention. FIG. 3 is a fragmentary cross-sectional view showing the manufacturing method of the semiconductor device following FIG. 2; FIG. 4 is a cross-sectional view showing a method for manufacturing the semiconductor device following FIG. 3, and is an essential part cross-sectional view showing an enlarged part of FIG. 3; FIG. 5 is a fragmentary cross-sectional view showing the manufacturing method of the semiconductor device following FIG. 4; FIG. 6 is a fragmentary cross-sectional view showing the manufacturing method of the semiconductor device following FIG. 5; FIG. 7 is a fragmentary cross-sectional view showing the manufacturing method of the semiconductor device following FIG. 6; FIG. 8 is a fragmentary cross-sectional view showing the manufacturing method of the semiconductor device following FIG. 7; FIG. 9 is a fragmentary cross-sectional view showing the manufacturing method of the semiconductor device following FIG. 8; FIG. 10 is an overhead view showing the semiconductor device in the manufacturing process of FIG. 9. FIG. 11 is a fragmentary cross-sectional view showing the manufacturing method of the semiconductor device following FIG. 10; FIG. 12 is an overhead view showing the semiconductor device in the manufacturing process of FIG. 11. FIG. 13 is a fragmentary cross-sectional view showing the manufacturing method of the semiconductor device following FIG. 12; FIG. 14 is a main part cross-sectional view showing the manufacturing method of the semiconductor device following FIG. 13; FIG. 15 is a fragmentary cross-sectional view showing the manufacturing method of the semiconductor device following FIG. 14; It is a graph which shows the resistance value of the wiring using those barrier films with respect to several types of barrier films. It is principal part sectional drawing of the semiconductor device which is Embodiment 2 of this invention. It is a graph which shows the withstand voltage between wiring of the wiring using those barrier films with respect to two types of barrier films. It is principal part sectional drawing of the semiconductor device which is Embodiment 3 of this invention. It is principal part sectional drawing which shows the manufacturing method of the semiconductor device which is Embodiment 3 of this invention. FIG. 21 is a fragmentary cross-sectional view showing the manufacturing method of the semiconductor device following FIG. 20; FIG. 22 is a fragmentary cross-sectional view showing the manufacturing method of the semiconductor device following FIG. 21; FIG. 23 is a fragmentary cross-sectional view showing the manufacturing method of the semiconductor device following FIG. 22; FIG. 24 is a main part cross-sectional view showing the manufacturing method of the semiconductor device following FIG. 23; It is principal part sectional drawing of the semiconductor device shown as a comparative example. It is principal part sectional drawing which shows the manufacturing method of the semiconductor device shown as a comparative example. FIG. 27 is a main part cross-sectional view showing the manufacturing method of the semiconductor device following FIG. 26; FIG. 27 is a main part cross-sectional view showing the manufacturing method of the semiconductor device following FIG. 26;

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted. Also, in the following embodiments, the description of the same or similar parts will not be repeated in principle unless particularly necessary.

(Embodiment 1)
An example of the structure of the damascene wiring according to the embodiment of the present invention will be described with reference to FIG. FIG. 1 is a cross-sectional view of a principal part showing a part of a semiconductor device including a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) which is a field effect transistor on a semiconductor substrate and a metal wiring formed in an interlayer insulating film on the MOSFET. is there.

  As shown in FIG. 1, the semiconductor device of the present embodiment has a MOSFET Qn formed on a semiconductor substrate SB. A gate electrode 32 is formed on the semiconductor substrate SB via a gate insulating film 33, and a pair of source / drain regions 30 are formed on the upper surface of the semiconductor substrate SB so as to sandwich the upper surface of the semiconductor substrate SB below the gate electrode 32. Is formed. Sidewalls 34 made of an insulating film are formed on the side walls of the gate electrode 32 and the gate insulating film 33, and silicide layers 31 are formed on the upper surfaces of the source / drain regions 30 and the gate electrode 32, respectively.

  MOSFET Qn is covered with stopper insulating film 35 and insulating film If, and contact hole Ch reaching the upper surface of silicide layer 31 above source / drain region 30 is formed in stopper insulating film 35 and insulating film If. . A barrier film BM is formed on the side wall and bottom surface of the contact hole Ch, and a contact plug Cp is embedded in the contact hole Ch via the barrier film BM. Here, the upper surfaces of the contact plug Cp, the barrier film BM, and the insulating film If have the same height.

  A stopper insulating film Sf is formed on the insulating film If, and a first interlayer insulating film 1 is formed on the stopper insulating film Sf. The insulating layer composed of the first interlayer insulating film 1 and the stopper insulating film Sf has a wiring groove G1 reaching the upper surfaces of the contact plug Cp, the barrier film BM, and the insulating film If, and the sidewalls in the wiring groove G1 A TaN film 2 is formed on the bottom surface. That is, in the wiring groove G1, the TaN film 2 is formed on the sidewalls of the first interlayer insulating film 1 and the stopper insulating film Sf, the contact plug Cp, the barrier film BM, and the insulating film If.

  A Ti film 3 is formed on the TaN film 2 at the bottom of the wiring groove G1 and on the side surface of the TaN film 2 that is not in contact with the first interlayer insulating film 1 and the stopper insulating film Sf. A Cu seed film 4a is formed on the Ti film 3 at the bottom of the wiring groove G1 and on the side surface of the Ti film 3 that is not in contact with the TaN film 2. The Cu film 4 is formed on the Cu seed film 4a at the bottom of the wiring groove G1 and on the side surface of the Cu seed film 4a that is not in contact with the Ti film 3, and the Cu film 4 is composed of the TaN film 2, It is buried in the wiring groove G1 through the Ti film 3 and the Cu seed film 4a.

  That is, between the Cu film 4 formed in the wiring trench G1 and the first interlayer insulating film 1, the stopper insulating film Sf, the insulating film If, the barrier film BM, and the contact plug Cp, in this order from the Cu film 4 side. A Cu seed film 4a, a Ti film 3, and a TaN film 2 are formed. The upper surfaces of the first interlayer insulating film 1, the Cu film 4, and the TaN film 2, the Ti film 3 and the Cu seed film 4a formed on the side wall of the wiring groove G1 have the same height. The film thickness of the TaN film 2 is about 5 nm, for example. The thickness of the Ti film 3 is less than 10 nm, for example, 5 nm.

  A liner film 5 is formed on the first interlayer insulating film 1, the Cu film 4, the TaN film 2 formed on the sidewall of the wiring groove G1, the Ti film 3 and the Cu seed film 4a. A second interlayer insulating film 6 is formed thereon. The second interlayer insulating film 6 has a wiring groove G2 that reaches the middle depth of the second interlayer insulating film 6, and the insulating layer composed of the second interlayer insulating film 6 and the liner film 5 is formed on the bottom surface of the wiring groove G2. The via hole V2 is opened and reaches the upper surface of the Cu film 4.

  A TaN film 7 is formed on the side wall and bottom surface in the wiring groove G2 and on the side wall and bottom surface of the via hole V2. That is, in the wiring groove G2 and the via hole V2, the Cu film on the top surface of the first interlayer insulating film 1 and the bottom surface of the via hole V2 as well as the side walls of the first interlayer insulating film 1 and the liner film 5 A TaN film 7 is formed on 4. A Ti film 8 is formed on the TaN film 7 at the bottom of the wiring trench G2 and the bottom of the via hole V2 and on the side surface of the TaN film 7 that is not in contact with the second interlayer insulating film 6 and the liner film 5. . A Cu seed film 9a is formed on the Ti film 8 at the bottom of the wiring trench G2 and the bottom of the via hole V2 and on the side surface of the Ti film 8 that is not in contact with the TaN film 7. A Cu film 9 is formed on the Cu seed film 9a at the bottom of the wiring trench G2 and the bottom of the via hole V2 and on the side surface of the Cu seed film 9a that is not in contact with the Ti film 8, and the Cu film 9 It is buried in the wiring groove G2 and the via hole V2 via the TaN film 7, Ti film 8 and Cu seed film 9a.

  In the present embodiment, the Ti films 3 and 8 are made of Ti (titanium), but the Ti films 3 and 8 are made of another Ti compound containing titanium, such as TiN (titanium nitride). May be.

  That is, between the Cu film 9 formed in the wiring trench G2 and the via hole V2 and the second interlayer insulating film 6, the liner film 5 and the Cu film 4, the Cu seed film 9a is sequentially formed from the Cu film 9 side. Ti film 8 and TaN film 7 are formed. The upper surfaces of the second interlayer insulating film 6, the Cu film 9, and the TaN film 7, the Ti film 8 and the Cu seed film 9a formed on the side wall of the wiring groove G2 have the same height.

  Further, a liner film 10 is formed on the second interlayer insulating film 6, the Cu film 9, and the TaN film 7 formed on the side wall of the wiring groove G2, the Ti film 8, and the Cu seed film 9a. . The source / drain region 30 and the Cu film 9 include a Cu seed film 9a, a Ti film 8, a TaN film 7, a Cu film 4, a Cu seed film 4a, a Ti film 3, a TaN film 2, a contact plug Cp, and a silicide layer 31. Is electrically connected.

A MOSFET Qn shown in FIG. 1 is an n-channel MOSFET having an n-type channel region, and is used, for example, as a switching element for switching an electric signal or an amplifying element for amplifying an electric signal. The semiconductor substrate SB is made of, for example, Si (silicon) and has a p-type semiconductor region on the upper surface. Each of the gate insulating film 33, the sidewall 34, and the insulating film If is made of, for example, SiO ₂ (silicon oxide). The stopper insulating film 35 is made of, for example, SiN (silicon nitride), and functions as an etching stopper film when the contact hole Ch is opened by dry etching. The gate electrode 32 is a low-resistance n-type semiconductor film (doped polysilicon film) into which an n-type impurity such as P (phosphorus) or As (arsenic) is introduced, and functions as the gate of the MOSFET Qn. . The source / drain region 30 is an n-type semiconductor region into which an n-type impurity is introduced, and functions as the source or drain of the MOSFET Qn.

The silicide layer 31 is made of, for example, NiSi (nickel silicide) which is a compound of Ni (nickel) and Si (silicon), and electrically connects the contact plug Cp made of W (tungsten) and the source / drain regions 30. Yes. The barrier film BM is made of, for example, Ti or a Ti compound, and has a function of preventing W (tungsten) in the contact plug Cp from diffusing into the insulating film If. The liner film 5 is an insulating film made of SiC (silicon carbide) formed by, for example, a CVD (Chemical Vapor Deposition) method. As a member other than SiC, SiN (silicon nitride), SiCN (silicon carbonitride), or SiOC is used. (Carbonated silicon) can be exemplified. The first interlayer insulating film 1 and the second interlayer insulating film 6 are formed of an insulating film having higher hygroscopicity than SiO ₂ (silicon oxide) and easily containing moisture. For example, the first interlayer insulating film 1 and the second interlayer insulating film 1 Each of the interlayer insulating films 6 is mainly made of SiOC.

  The TaN film 2 is a conductive metal film mainly made of TaN (tantalum nitride, tantalum nitride), and Cu (copper) in the Cu film 4 is the first interlayer insulating film 1, the stopper insulating film Sf, or the insulating film If. To prevent it from diffusing. The Ti film 3 is a conductive metal film mainly made of Ti (titanium), and Cu (copper) in the Cu film 4 diffuses into the first interlayer insulating film 1, the stopper insulating film Sf, the insulating film If, or the like. To prevent you from doing. Further, the Ti film 3 has high adhesiveness with Cu (copper), and by forming the Ti film, the Cu seed film 4a and the Cu film 4 can be formed through the TaN film 2 and the Ti film 3 without any gap in the wiring groove G1. It is supposed to be embedded. The Cu films 4 and 9 and the Cu seed films 4a and 9a are mainly Cu (copper) or Cu (copper) and another metal (for example, Al (aluminum), Si (silicon), Ge (germanium), Ga (gallium) or Sn (tin) or the like, and is a part of a conductive path for supplying a predetermined potential to the source / drain region 30.

  The liner films 5 and 10 have a function of preventing Cu (copper) in the Cu film 4 or 9 from diffusing above the Cu film 4 or 9. The liner films 5 and 10 are insulating films mainly containing at least one of SiN, SiC, SiCN and SiOC, respectively.

  Similar to the TaN film 2, the TaN film 7 is a conductive metal film mainly made of TaN (tantalum nitride, tantalum nitride), and Cu (copper) in the Cu film 9 becomes the second interlayer insulating film 6 and the like. Prevents diffusion. The Ti film 8 is a conductive metal film mainly made of Ti (titanium), and prevents Cu (copper) in the Cu film 9 from diffusing into the second interlayer insulating film 6 and the like in the same manner as the Ti film 3. Yes. Similar to the Ti film 3, the Ti film 8 improves the embedding property of the Cu seed film 9a and the Cu film 9 in the wiring groove G1.

  Next, a method for manufacturing the semiconductor device of the present embodiment will be described with reference to FIGS. 2 and 3 are cross-sectional views of the main part of the semiconductor device of the present embodiment including the MOSFET Qn. FIGS. 4 to 9, 11 and 13 to 15 show the upper part of the contact plug Cp shown in FIG. It is principal part sectional drawing which expands and shows. 10 and 12 are overhead views showing via holes and wiring grooves in the regions shown in FIGS. 9 and 11, respectively. Note that the present invention relates to a metal wiring and can be applied to other semiconductor devices such as a diode or a capacitor other than the MOSFET, and therefore, detailed description of the process for forming the MOSFET Qn is omitted here.

  First, as shown in FIG. 2, a MOSFET Qn is formed on the upper surface of the semiconductor substrate SB using a known technique. The MOSFET Qn has a gate electrode 32 formed on the upper surface of the semiconductor substrate SB via a gate insulating film 33, and a source / drain region 30 which is an n-type semiconductor region formed on the upper surface of the semiconductor substrate SB. Side walls 34 mainly made of silicon oxide are formed on the side walls of the gate electrode 32, and silicide layers 31 are formed on the upper surfaces of the gate electrode 32 and the source / drain regions 30, respectively.

  Next, a stopper insulating film 35 is formed so as to cover the main surface (entire surface) of the semiconductor substrate SB including the gate electrode 32, the source / drain region 30, the sidewall 34 and the silicide layer 31. The stopper insulating film 35 is made of, for example, a silicon nitride film, and can be formed by a plasma CVD method or the like at a film formation temperature (substrate temperature) of about 450 ° C. The stopper insulating film 35 functions as an etching stopper film when a contact hole is formed on the MOSFET Qn.

  Thereafter, an insulating film If thicker than the stopper insulating film 35 is formed on the stopper insulating film 35. The insulating film If is made of, for example, a silicon oxide film or the like, and can be formed by a plasma CVD method using TEOS at a film formation temperature of about 450 ° C. Thereafter, the upper surface of the insulating film If is planarized by polishing the surface of the insulating film If by a CMP method or the like. Even if unevenness is formed on the surface of the insulating film If due to the level difference in the base, the insulating film having a flattened surface can be obtained by polishing the surface of the insulating film If by the CMP method.

  Next, as shown in FIG. 3, the insulating film 35 and the insulating film If are dry-etched using a photoresist pattern (not shown) formed on the insulating film If as an etching mask, so that the stopper insulating film 35 and A contact hole (through hole, hole) Ch that penetrates the insulating film If is formed. At the bottom of the contact hole Ch, a part of the main surface of the semiconductor substrate SB, for example, the upper surface of the silicide layer 31 on the surface of the source / drain region 30 is exposed, and in the region not shown, it is the same layer as the gate electrode 32. The upper surface of the silicide layer on the upper surface of the gate connection portion is exposed.

  Thereafter, after forming a barrier film BM containing Ti (titanium) in the contact hole Ch and on the insulating film If, the contact hole Ch is filled with a W (tungsten) film, and the barrier film BM and the tungsten film are polished. The upper surface of the insulating film If is exposed to form a contact plug Cp.

  In order to form the contact plug Cp, for example, a barrier film (for example, titanium) is formed on the insulating film If including the inside (on the bottom and side walls) of the contact hole Ch by a plasma CVD method at a film formation temperature (substrate temperature) of about 450 ° C. Film, titanium nitride film, or a laminated film thereof) BM. Then, after forming a main conductor film made of a tungsten film or the like so as to fill the contact hole Ch on the barrier film BM by a CVD method or the like, the unnecessary main conductor film and the barrier film BM on the insulating film If are formed by CMP or etching. The contact plug Cp can be formed by removing by the back method or the like. Although illustration is omitted, at this time, a silicide layer is also formed on the upper surface of the connection portion formed integrally with the gate electrode 32 and in the same layer as the gate electrode 32, and contact is made on the connection portion via the silicide layer. A plug is formed.

  Next, as shown in FIG. 4, the stopper insulating film Sf and the first interlayer insulating film 1 for wiring formation are sequentially formed on the insulating film If in which the contact plug Cp is embedded. 4 to 9, FIG. 11, and FIG. 13 to FIG. 15 are enlarged cross-sectional views of the main part showing the region surrounded by the broken line shown in FIG. 3, and the wiring formation region above the contact plug Cp. Is shown. The stopper insulating film Sf is a film that becomes an etching stopper film when a groove is formed in the first interlayer insulating film 1, and a material having an etching selectivity with respect to the first interlayer insulating film 1 is used. The stopper insulating film Sf can be, for example, a SiN (silicon nitride) film formed by a plasma CVD method, and the first interlayer insulating film 1 can be, for example, a SiOC (silicon carbonate) film formed by a plasma CVD method. .

  Next, as shown in FIG. 5, a first layer wiring is formed by a single damascene method. First, a wiring trench that exposes the upper surfaces of the insulating film If, the contact plug Cp, and the barrier film BM in predetermined regions of the first interlayer insulating film 1 and the stopper insulating film Sf by dry etching using a resist pattern (not shown) as a mask. G1 is formed.

  Next, as shown in FIG. 6, TaN (tantalum nitride, tantalum nitride) is formed on the main surface of the semiconductor substrate SB (not shown) (that is, on the first interlayer insulating film 1 including the bottom and side walls of the wiring groove G1). The TaN film 2 that is a barrier conductor film (barrier metal film) and the Ti film 3 that is a barrier conductor film made of Ti (titanium) are sequentially formed by the PVD method. The film thickness of the TaN film 2 is about 5 nm. The thickness of the Ti film 3 is less than 10 nm, for example, 5 nm. Here, the TaN film 2 is formed under the Ti film 3 as a barrier conductor film, but instead of the TaN film 2, a Ta (tantalum) film or other tantalum compound, tantalum alloy, titanium compound, titanium alloy, tungsten In addition, a conductor film mainly containing a tungsten compound, Ru (ruthenium), a ruthenium compound, or the like can be used as the barrier conductor film.

Subsequently, a Cu seed film 4a made of Cu (copper) is formed on the Ti film 3 by the PVD method, and further the Cu film 4 is formed on the Cu seed film 4a by using an electrolytic plating method, whereby the TaN film 2 The inside of the wiring groove G1 is filled with the Ti film 3, the Cu seed film 4a, and the Cu film 4. Thereafter, the Cu seed film 4a and the Cu film 4 are integrated by heat-treating the semiconductor device in the manufacturing process in an atmosphere of an inert gas such as N ₂ (nitrogen), and the crystal grain size of Cu is grown. Enlarge. Note that the heat treatment at this time is performed in an inert gas atmosphere because it is a material that easily oxidizes copper, and it is preferable to perform the heat treatment in an atmosphere from which oxygen is removed as much as possible. When the Cu film 4 is oxidized, the conductivity of the Cu film 4 is lowered, and the reliability of the semiconductor device is lowered. Here, the Cu seed film 4a and the Cu film 4 are integrated by heat treatment, but in the figure, the Cu seed film 4a and the Cu film 4 are shown separately.

Further, before the TaN film 2 and the Ti film 3 are formed, pretreatment (preclean) such as annealing treatment or plasma treatment using H ₂ (hydrogen) gas may be performed as necessary.

  Next, as shown in FIG. 7, the Cu film 4, the Cu seed film 4a, the Ti film 3 and the TaN film 2 in regions other than the inside of the wiring groove G1 are removed by the CMP method, and the upper surface of the first interlayer insulating film 1 is removed. By exposing, a first layer metal wiring (lower layer wiring M1) composed of TaN film 2, Ti film 3, Cu seed film 4a and Cu film 4 and using copper as a main conductive material is formed.

  The above-described heat treatment for integrating the Cu seed film 4a and the Cu film 4 may be performed after the polishing process by the CMP method described with reference to FIG.

  Next, as shown in FIG. 8, on the main surface of the semiconductor substrate SB (not shown) (that is, on the first interlayer insulating film 1, on the TaN film 2, on the Ti film 3, on the Cu seed film 4a, and on the Cu film 4). On the top, a liner film 5 made of SiC (silicon carbide) and a second interlayer insulating film 6 made of SiOC (silicon carbonate) are sequentially formed by a CVD method.

  Next, as shown in FIGS. 9 and 10, a via hole V2 exposing the upper surface of the Cu film 4 is formed. FIG. 10 is an overhead view showing a cross section of the semiconductor device in the manufacturing process shown in FIG. The via hole V2 is formed in a predetermined region of the second interlayer insulating film 6 and the liner film 5 by dry etching using a resist pattern (not shown) as a mask. As shown in FIG. 10, for example, a plurality of via holes V2 are formed intermittently, and do not have a groove shape.

  Next, as shown in FIGS. 11 and 12, a wiring groove G2 for forming a second-layer wiring is formed. 12 is an overhead view showing a cross section of the semiconductor device in the manufacturing process shown in FIG. The wiring groove G2 is formed in a predetermined region of the second interlayer insulating film 6 by dry etching using a resist pattern (not shown) as a mask. The wiring groove G2 is formed by dry etching to a depth halfway of the second interlayer insulating film 6, and the upper surface of the lower Cu film 4 is not exposed.

  In this embodiment, the via hole V2 is formed in the steps shown in FIGS. 9 and 10, and then the wiring groove G2 is formed in the steps shown in FIGS. 11 and 12. However, the order of these steps may be reversed. . That is, when forming the wiring groove G2 and the via hole V2 in the semiconductor device in the manufacturing process in which the second interlayer insulating film 6 as shown in FIG. 8 is formed, the wiring groove G2 is formed and then the resist pattern is used as a mask. The via hole V2 may be formed by dry etching.

  Next, a second layer wiring is formed by the same process as the process of forming the lower layer wiring M1. Here, the second layer wiring is formed by using a dual damascene method. That is, as shown in FIG. 13, TaN is formed on the main surface of the semiconductor substrate SB (not shown) (that is, on the second interlayer insulating film 6 including the bottom and side walls of the wiring groove G2 and on the bottom and side walls of the via hole V2). A TaN film 7 which is a barrier conductor film made of (tantalum nitride, tantalum nitride) and a Ti film 8 which is a barrier conductor film made of Ti (titanium) are sequentially formed by the PVD method. The film thickness of the TaN film 7 is about 5 nm. The thickness of the Ti film 8 is less than 10 nm, for example, 5 nm. Here, the TaN film 7 is formed under the Ti film 8 as the barrier conductor film, but instead of the TaN film 7, a Ta (tantalum) film or other tantalum compound, tantalum alloy, titanium compound, titanium alloy, tungsten In addition, a conductor film mainly containing a tungsten compound, Ru (ruthenium), a ruthenium compound, or the like can be used as the barrier conductor film.

Subsequently, a Cu seed film 9a is formed on the Ti film 8 by the PVD method, and further, the Cu film 9 is formed on the Cu seed film 9a by the electrolytic plating method, whereby the TaN film 7, the Ti film 8, and the Cu film 9 are formed. The inside of the wiring trench G2 and the via hole V2 is filled with the seed film 9a and the Cu film 9. Thereafter, the Cu seed film 9a and the Cu film 9 are integrated by heat-treating the semiconductor device in the manufacturing process in an atmosphere of an inert gas such as N ₂ (nitrogen), and the crystal grain size of copper is grown. Enlarge. The reason why the heat treatment at this time is performed in an inert gas atmosphere is to prevent the copper in the Cu film 9 and the Cu seed film 9a from being oxidized, as in the process of forming the lower wiring M1.

In addition, before forming the TaN film 7 and the Ti film 8, a pretreatment (preclean) such as an annealing treatment using H ₂ (hydrogen) gas or a plasma treatment may be performed as necessary.

  Next, as shown in FIG. 14, the Cu film 9, the Cu seed film 9a, the Ti film 8 and the TaN film 7 in regions other than the wiring trench G2 and the via hole V2 are removed by CMP to form a second interlayer insulating film. 6 is exposed to form a second layer metal wiring (upper layer wiring M2) composed of TaN film 7, Ti film 8, Cu seed film 9a, and Cu film 9 and using copper as a main conductive material. .

  The above-described heat treatment for integrating the Cu seed film 9a and the Cu film 9 may be performed after the polishing process by the CMP method described with reference to FIG.

  Next, as shown in FIG. 15, on the main surface of the semiconductor substrate SB (not shown) (that is, on the second interlayer insulating film 6, on the TaN film 7, on the Ti film 8, on the Cu seed film 9a, and on the Cu film 9). A liner film 10 made of SiC (silicon carbide) is formed on the upper layer by a CVD method, whereby the semiconductor device of the present embodiment shown in FIG. 1 is completed. Although description is omitted in the present embodiment, a multilayer Cu wiring can be formed in a region higher than the upper wiring M2 by performing the same process as the upper wiring M2.

  Next, the reason why the thicknesses of the Ti films 3 and 8 are set to less than 10 nm in the barrier film forming process described with reference to FIGS. 6 and 13 and 5 nm in the present embodiment will be described with reference to FIGS. To do. FIG. 16 is a graph showing the cumulative frequency distribution obtained by measuring the resistance value of the Cu wiring when the barrier metal member and five types of barrier films having different film thicknesses are used. The horizontal axis of the graph shown in FIG. 16 indicates the resistance value of the Cu wiring, and the vertical axis of the graph shown in FIG. 16 indicates the quantile of the normal distribution in the experiment performed a plurality of times.

  As shown in FIG. 16, the barrier film is composed of a 5 nm Ti film and a 5 nm TaN film for a resistance value of Ta / TaN = 10/5 nm, which is composed of a 10 nm Ta film and a 5 nm TaN film. There is almost no difference in the resistance value of Ti / TaN = 5/5 nm. However, it can be seen that the resistance value of Ti / TaN = 10/5 nm significantly increases as compared with the resistance value of Ta / TaN = 10/5 nm. This is because Ti (titanium) easily forms an alloy with Cu (copper), and the Ti / Cu alloy has a higher resistance value than pure Cu (copper). That is, when Ti / TaN = 10/5 nm, the amount of Ti (titanium) that reacts with the Cu film to form an alloy is large, so that the resistance value is higher than that of Ti / TaN = 5/5 nm. From this, it can be seen that by making the thickness of the Ti film at the interface of the Cu film thinner than 10 nm, the influence of the substantial increase in resistance due to alloying on the wiring resistance can be suppressed to a negligible level. Therefore, in this embodiment, in order to reduce the wiring resistance, the thickness of the Ti films 3 and 8 (see FIG. 1) is set to less than 10 nm, preferably 5 nm.

  Next, effects of the semiconductor device of this embodiment will be described.

  In the prior art, as shown in Patent Documents 1 and 2, using a barrier film containing Ta (tantalum), which is a material having a high metal diffusion preventing function, Cu (copper) in Cu wiring is an interlayer insulating film. In general, the wiring structure prevents diffusion into the wiring.

  However, a barrier film mainly containing Ta (tantalum) has a metal diffusion prevention function superior to a barrier film mainly containing other metals such as Ti (titanium) or W (tungsten), but Cu (copper). The wettability is worse than that of Ti (titanium). For this reason, it is difficult to form a Cu seed film uniformly and continuously on the surface of a barrier film such as a Ta film or TaN film in the wiring trench, and as a comparative example, as shown in FIG. 26, on the surface of the Ta film 8a. There is a possibility that the Cu seed film 9b becomes a plurality of masses. That is, the surface of the Ta film 8a is not completely covered, the coating rate of the Cu seed film 9b is lowered, and the Cu seed film 9b is formed discontinuously. In this case, as shown as a comparative example in FIGS. 27 and 28, when the Cu film 9 is formed, voids 11 are easily formed in the wiring groove G2 and the via hole V2.

  Cu seed films 4a and 9a shown in FIG. 1 are films that serve as electrodes when the Cu films 4 and 9 are formed by electroplating, and have a function of forming the Cu films 4 and 9 uniformly. This is because the film thickness uniformity of the Cu films 4 and 9 formed by the electroplating method depends on the resistance value of the underlying member of the Cu films 4 and 9. Therefore, as shown in FIG. 26, if the Cu seed film 9b is not formed uniformly on the surface of the Ta film 8a in the wiring groove G2 and the via hole V2, a Ta film is formed in the electroplating process when forming the Cu film 9. Even if 8a functions as an electrode, members having different resistance values such as the Cu seed film 9b or the Ta film 8a exist under the Cu film 9. For this reason, as shown in FIG. 27 or FIG. 28, since the Cu film 9 is not formed with a uniform thickness, a void 11 is formed in some cases.

  When the air gap 11 is formed, there is a possibility that the wiring mainly composed of the Cu film 9 is interrupted in the middle, or the wiring in the via hole is interrupted so that the upper layer wiring and the lower layer wiring are not electrically connected. This leads to a decrease in yield or reliability.

  In addition, since Ta (tantalum) is expensive compared to Ti (titanium), using Ta (tantalum) as a barrier film increases the cost of products using semiconductor devices.

  Therefore, the present inventors have examined the use of a metal film mainly containing Ti (titanium) as a barrier film for wiring. In the present embodiment, as shown in FIG. 1, the Ti film 3 and the TaN film 2 under the Ti film 3 are formed as a barrier film for preventing the diffusion of copper in the lower layer wiring M1. A Ti film 8 and a TaN film 7 under the Ti film 8 are formed as a barrier film for preventing copper diffusion in M2.

  A barrier film containing Ti (titanium) is characterized by better wettability with copper than a barrier film containing Ta (tantalum) or a Ta compound. That is, when the Cu seed film 9a is formed on the surface of the Ti film 8 which is a barrier film containing Ti (titanium) by the PVD method, the Cu seed film 9a does not become a plurality of masses and extends uniformly. The seed film 9a covers the surface of the Ti film 8 without exposing it. Since the Cu film 9 is formed with a uniform film thickness on the Cu seed film 9a by electroplating, unlike the comparative example shown in FIGS. 26 to 28, the air gap 11 is formed in the wiring groove G2 and the via hole V2. It can be prevented from being formed.

  Since Ti (titanium) is a cheaper material than Ta (tantalum), Ta (tantalum) and TaN (tantalum nitride) as shown in FIG. 25 can be obtained by using a barrier film containing Ti (titanium). The cost of a product using a semiconductor device can be reduced as compared with the case where the film is used as a barrier film.

  Ti (titanium) is a material having a lower metal diffusion preventing function than Ta (tantalum). However, as shown in FIG. 1, TaN films 2 and 7 are formed under the Ti films 3 and 8. This prevents the diffusion prevention function from being lowered.

  As described above, in the semiconductor device of this embodiment, the wiring resistance is increased by using a metal film of less than 10 nm mainly containing Ti (titanium) for the barrier film of the damascene wiring mainly containing copper. Therefore, it is possible to prevent the generation of voids in the wiring, improve the yield and reliability of the semiconductor device, and reduce the cost of products using the semiconductor device.

(Embodiment 2)
In the above-described embodiment, the semiconductor device has been described in which a metal film mainly containing Ti (titanium) is used as the barrier film for the Cu wiring at the interface with the Cu film, and another barrier film is formed under the Ti film. In this embodiment mode, a semiconductor device using a TiN _x (titanium nitride) film whose number of atoms is more N (nitrogen) than Ti (titanium) as a barrier film will be described with reference to FIGS. FIG. 17 is a fragmentary cross-sectional view showing a region including MOSFET and damascene wiring in the semiconductor device of the present embodiment.

As shown in FIG. 17, the semiconductor device according to the present embodiment has substantially the same structure as that of the semiconductor device according to the first embodiment, and is manufactured in substantially the same manufacturing process as the semiconductor device according to the first embodiment. can do. In the semiconductor device of the present embodiment, a TiN _X film 12 having a metal diffusion preventing function is formed in place of the TaN film 2 and the Ti film 3 which are the barrier films shown in FIG. Instead of the film 7 and the Ti film 8, a TiN _X film 13 having a metal diffusion preventing function is formed, which is different from the semiconductor device in the first embodiment.

That is, the semiconductor device of the present embodiment has a MOSFET Qn formed on the semiconductor substrate SB, and the first interlayer insulating film 1 and the second interlayer insulating film 6 on the insulating film If formed so as to cover the MOSFET Qn. Wiring grooves G1 and G2 are formed in each of these. A barrier film of a TiN _X film 12 having a film thickness of, for example, 10 nm is formed on the side wall and the bottom of the wiring groove G1 formed in the first interlayer insulating film 1 and the stopper insulating film Sf below the first interlayer insulating film 1. In the wiring groove G1, a Cu seed film 4a is formed via a TiN _X film 12. The wiring groove G1 is filled with a Cu film 4 via a TiN _X film 12 and a Cu seed film 4a, and the lower layer wiring M1 is constituted by the Cu film 4, the Cu seed film 4a and the TiN _X film 12.

A second interlayer insulating film 6 is disposed on the first interlayer insulating film 1 and the lower layer wiring M1 via a liner film 5. The second interlayer insulating film 6 includes a wiring groove G2 and a second groove from the bottom of the wiring groove G2. A via hole V2 that penetrates through the two interlayer insulating film 6 and the liner film 5 and reaches the upper surface of the lower wiring M1 (the upper surface of the Cu film 4) is formed. In the wiring groove G2 and the via hole V2, the Cu film 9 is embedded via the TiN _X film 13 and the Cu seed film 9a having a film thickness of, for example, 10 nm, similarly to the lower layer wiring M1 in the wiring groove G1. The upper layer wiring M2 is constituted by the Cu film 9, the Cu seed film 9a, and the TiN _X film 13.

Here, the TiN _X films 12 and 13 are conductive metal films having a metal diffusion preventing function, and each film thickness is 10 nm. This is because, as shown in the graph of FIG. 16, the wiring resistance of the wiring having the barrier film of TiN = 10 nm is almost the same as the wiring resistance of the wiring having the barrier film of Ta / TaN = 10/5 nm. _By setting the film thickness of each of the _X films 12 and 13 to 10 nm or less, it is possible to prevent the wiring resistance from increasing as compared with a barrier film of Ta / TaN = 10/5 nm.

In the method of forming the semiconductor device according to the present embodiment, the TiN _X film 12 is formed instead of the TaN film 2 and the Ti film 3 in the process of forming the TaN film 2 and the Ti film 3 of the first embodiment (see FIG. 6). The method of manufacturing the semiconductor device according to the first embodiment except for the step of forming the TiN _X film 13 instead of the TaN film 7 and the Ti film 8 in the step of forming the TaN film 7 and the Ti film 8 (see FIG. 13). Since it is the same, detailed description is abbreviate | omitted.

That is, in the process described with reference to FIG. 6 in the first embodiment, on the main surface of the semiconductor substrate SB (not shown) (that is, on the first interlayer insulating film 1 including the bottom and side walls of the wiring groove G1). the TiN _X film 12 is a barrier conductive film made of TiN _X (titanium nitride) is formed by a PVD method. Subsequently, by TiN _X film 12 of Cu seed film 4a made of Cu (copper) is formed on, further forming a Cu film 4 on Cu seed film 4a by using an electrolytic plating method by a PVD method, TiN _X The wiring groove G1 is filled with the film 12, the Cu seed film 4a, and the Cu film 4. Thereafter, the Cu seed film 4a and the Cu film 4 are integrated by heat-treating the semiconductor device in the manufacturing process in an atmosphere of an inert gas such as N ₂ (nitrogen), and the crystal grain size of Cu is grown. Enlarge.

Similarly, in the step described with reference to FIG. 13 in the first embodiment, on the main surface of the semiconductor substrate SB (not shown) (that is, on the second interlayer insulating film 6 including the bottom and side walls of the wiring groove G2, and A TiN _X film 13 which is a barrier conductor film made of TiN _X (titanium nitride) is formed by PVD on the bottom and side walls of the via hole V2. Subsequently, the Cu seed film 9a is formed on the TiN _X film 13 by the PVD method, and further the Cu film 9 is formed on the Cu seed film 9a by the electrolytic plating method, whereby the TiN _X film 13 and the Cu seed film are formed. The wiring trench G2 and the via hole V2 are filled with 9a and the Cu film 9. Thereafter, the Cu seed film 9a and the Cu film 9 are integrated by heat-treating the semiconductor device in the manufacturing process in an atmosphere of an inert gas such as N ₂ (nitrogen), and the crystal grain size of copper is grown. Enlarge.

  The semiconductor device of the present embodiment shown in FIG. 17 is completed by performing the same steps as the manufacturing steps of the semiconductor device in the first embodiment except for the above steps.

Here, TiN _X (titanium nitride) constituting the TiN _X films 12 and 13 has more N (nitrogen) atoms than Ti (titanium). That is, _X representing the number of N (nitrogen) atoms with respect to one Ti (titanium) atom in TiN _X (titanium nitride) is less than 1 (X <1), for example, X = 0.5. That is, here, the ratio of the number of atoms of Ti (titanium) and N (nitrogen) is Ti: N = 2: 1.

The reason why TiN _X (X <1) is used as the material of the barrier film as described above will be described with reference to FIG. FIG. 18 shows the case where TiN _X (X = 1), in which the ratio of the number of atoms of Ti (titanium) and N (nitrogen) is 1: 1, and the case where TiN _X (X = 0.5) is used. It is the graph which showed the withstand voltage between wiring between the two metal wirings arrange | positioned maintaining a fixed distance (for example, 70 nm) when used as a barrier material. The horizontal axis of the graph shown in FIG. 18 indicates the potential difference between the wirings when the current is short-circuited when the potential difference between the wirings is increased. The vertical axis of the graph shown in FIG. The quantile of the normal distribution in the inter-wiring breakdown voltage experiment is shown. The white circles shown in FIG. 18 indicate the withstand voltage between Cu wirings using TiN _X (X = 1) as the barrier film, and the black circles indicate the Cu wiring using TiN _X (X = 0.5) as the barrier film. The withstand voltage between wires is shown.

As shown in FIG. 18, the Cu wiring using TiN _X (X = 1) as a barrier film has a potential difference lower than the inter-layer breakdown voltage of the Cu wiring using TiN _X (X = 0.5) as a barrier film. The wiring is shorted. That is, the inter-wiring voltage of Cu wiring using TiN _X (X = 0.5) as a barrier film shows a value of about 50 V, but Cu wiring using TiN _X (X = 1) as a barrier film is , The withstand voltage value between the wirings in the range of 17V to 50V. Therefore, the larger the ratio of N (nitrogen) in the TiN _X film, TiN _X film it can be seen that the interconnection between the breakdown voltage of the Cu wiring is reduced used as a barrier film.

Also, as shown in FIG. 18, Cu wiring using TiN _X (X = 1) as a barrier film has a large variation in the horizontal axis direction, and the reliability of breakdown voltage between wirings is low. On the other hand, the inter-wire breakdown voltage of Cu wiring using TiN _X (X = 0.5) as a barrier film has little variation in the horizontal axis direction, and normal quantiles are distributed in a direction substantially along the vertical axis. This shows that the reliability of the withstand voltage between wirings is high.

Therefore, the number X of N (nitrogen) atoms in TiN _X (titanium nitride) used for the barrier film indicates a wiring breakdown voltage and reliability that are almost no problem if X <1, and in this embodiment, X <1 And preferably X = 0.5. That is, the composition ratio of Ti (titanium) and N (nitrogen) in the titanium nitride film constituting the barrier film in this embodiment is Ti> N, and particularly when Ti = 1, N = 0.5. It is preferable that

As described above, when TiN _X (titanium nitride) is used for the barrier film, the metal diffusion preventing function equivalent to the case where Ta (tantalum) and TaN (tantalum nitride) are formed as the barrier film as shown in FIG. It is possible to form a barrier film having good wettability and adhesion with copper. This is because by combining N (nitrogen) with Ti (titanium), Ti (titanium) that is easily alloyed with other elements (for example, Cu (copper)) can be reduced in the barrier film.

That is, a TiN _x (titanium nitride) film in which N (nitrogen) is combined with Ti (titanium) is less likely to be alloyed with copper than a pure Ti film. Usually, Ti (titanium) and Cu (copper) are easily alloyed, and a titanium film alloyed with copper has an increased resistance value. Although it is necessary to increase the thickness of the Ti film in order to provide a sufficient diffusion preventing function to the Ti film having a lower diffusion preventing function than Ta (tantalum), the Ti film that is easily alloyed with copper is too thick. Since the resistance value is significantly increased, it cannot be used as a barrier film. Therefore, when a pure Ti film is used as a barrier film, its film thickness and diffusion preventing function are limited.

On the other hand, in this embodiment, since a TiN _X film that is difficult to be alloyed with copper due to the combination of N (nitrogen) is used as a barrier film, even if the thickness of the TiN _X film is increased, TiN _X is used. The resistance value of the _X film hardly increases. Therefore, it is possible to obtain a sufficient diffusion preventing function by increasing the thickness of the TiN _X film. In the present embodiment, the thickness of each of the TiN _X films 12 and 13 shown in FIG. 17 is set to 10 nm. However, in order to further improve the diffusion prevention function, the thickness of each of the TiN _X films 12 and 13 is set to be more than 10 nm. A thick film may be used.

  For the above reason, the value of X indicating the number of N (nitrogen) atoms for one Ti (titanium) atom may be a smaller value less than 0.5, but it must be a value greater than 0. . That is, if the number of nitrogen atoms is 0, the barrier film becomes a pure Ti film, so that the resistance value of the barrier film greatly increases due to alloying with copper, which causes a problem when used as a barrier film. Therefore, it is necessary that X> 0.

According to the present embodiment, by using a TiN _X film containing Ti (titanium) having good wettability with copper as a barrier film, the embeddability of the Cu films 4 and 9 shown in FIG. 17 is improved, and the yield is improved. The reliability of the semiconductor device can be improved. Further, by using a barrier film using Ti (titanium) which is a material cheaper than Ta (tantalum), the cost of a product using a semiconductor device can be reduced.

(Embodiment 3)
In the semiconductor device according to the first embodiment, the technique using the Ti film and the TaN film as the barrier film for the Cu wiring has been described. On the other hand, in this embodiment, when forming the barrier film, only the Ti film (or Ti alloy film) is formed, and then the titanium oxide film formed in the lower layer in the Ti film, and the Ti film A semiconductor device using a barrier film having a two-layer structure will be described with reference to FIGS.

  As shown in FIG. 19, the semiconductor device according to the present embodiment has substantially the same structure as that of the semiconductor device according to the first embodiment, and is manufactured in substantially the same manufacturing process as the semiconductor device according to the first embodiment. can do. In the semiconductor device of the present embodiment, Ti oxide films 14 and 16 having a metal diffusion preventing function are formed in place of TaN films 2 and 7 which are the barrier films shown in FIG. Instead of the Ti films 3 and 8, Ti films 15 and 17 having a metal diffusion preventing function are formed, which is different from the semiconductor device in the first embodiment.

The Ti films 15 and 17 and the Ti oxide films 14 and 16 are conductive barrier films, and the Ti oxide films 14 and 16 are specifically reaction layers made of TiO _X film or TiSi _X O _Y. The number of N (nitrogen) atoms in the TiN _X film 12 (see FIG. 17) described in the second embodiment, the number of O (oxygen) atoms in the TiO _X film of the present embodiment, and TiSi _The number X of Si (silicon) atoms in the _X O _Y film does not indicate the same value.

  Here, a manufacturing process of the semiconductor device of the present embodiment will be described. To manufacture the semiconductor device shown in FIG. 19, first, as described with reference to FIG. 5 in the first embodiment, the wiring groove G1 is formed in the stopper insulating film Sf and the first interlayer insulating film 1 on the insulating film If. After the formation, as shown in FIG. 20, a Ti film 14a is formed (deposited) on the first interlayer insulating film 1 and on the inner wall and bottom surface of the wiring groove G1 by the PVD method. The thickness of the Ti film 14a is, for example, 10 nm.

  At this time, the Ti film 14a is a film made of pure Ti (titanium) or an alloy thereof, but reacts with moisture in the first interlayer insulating film 1 due to heat (for example, about 450 ° C.) during the PVD process. It is oxidized. In this case, as shown in FIG. 21, a Ti oxide film 14 is formed on the first interlayer insulating film 1 including the interface with the first interlayer insulating film 1 and on the inner wall and bottom surface of the wiring groove G1, and the first interlayer insulating film is formed. A Ti film 15 is formed on the first interlayer insulating film 1 including the interface with 1 and on the inner wall and bottom surface of the wiring groove G1 with the Ti oxide film 14 interposed therebetween.

  The subsequent steps are performed in the same manner as in the first embodiment up to the step of forming the wiring groove G2. That is, as shown in FIG. 22, after the Cu seed film 4a and the Cu film 4 are formed on the Ti film 15, the Cu film 4, the Cu seed film 4a, and the Ti film 15 on the first interlayer insulating film 1 are formed by CMP. Then, the Ti oxide film 14 is removed, and the upper surface of the first interlayer insulating film 1 is exposed to form a lower layer wiring M1 including the Cu film 4, the Cu seed film 4a, the Ti film 15, and the Ti oxide film 14. Subsequently, as shown in FIG. 23, the liner film 5 and the second interlayer insulating film 6 are formed on the first interlayer insulating film 1 and the lower layer wiring M1, and the liner film 5 and the second interlayer insulating film 6 are penetrated. After forming the via hole V2 exposing the upper surface of the Cu film 4, a wiring groove G2 is formed on the upper surface of the second interlayer insulating film 6 to obtain the structure of FIG.

  Next, similarly to the process described with reference to FIGS. 20 and 21, after the Ti film is deposited by the PVD method, the lower Ti (titanium) in the Ti film is heated by the heat during the PVD process. By reacting with moisture in the two interlayer insulating film 6 and oxidizing, a Ti film is formed on the second interlayer insulating film 6 and on the inner wall and bottom surface of the wiring trench G2 via the Ti oxide film 16 as shown in FIG. 17 is formed.

  The subsequent steps are performed in the same manner as in the first embodiment. That is, after forming the Cu seed film 9a and the Cu film 9 on the Ti film 17, the Cu film 9, the Cu seed film 9a, the Ti film 17 and the Ti oxide film 16 on the second interlayer insulating film 6 are removed by CMP. Then, by exposing the upper surface of the second interlayer insulating film 6, the upper wiring M <b> 2 composed of the Cu film 9, the Cu seed film 9 a, the Ti film 17, and the Ti oxide film 16 is formed. Thereafter, the liner film 10 is formed on the second interlayer insulating film 6 and the upper wiring M2, and the semiconductor device shown in FIG. 19 is completed.

  In the present embodiment, when forming the barrier film of the lower layer wiring M1 and the upper layer wiring M2, there is no step of depositing a film other than the Ti film, and the bottom of the deposited Ti film is oxidized, so that Ti A barrier film having a two-layer structure of a film and an underlying Ti oxide film is formed. Here, from the graph shown in FIG. 16, when a Ti film is formed as a barrier film with a thickness of 10 nm (Ti = 10 nm), a Ti film with a thickness of 10 nm as a barrier film and a TaN film with a thickness of 5 nm are laminated (Ti / TaN = 10/5 nm), it can be seen that Ti / TaN = 10/5 nm has a higher wiring resistance than Ti = 10 nm.

  When Ti / Ta = 10/5 nm, all of the Ti film on the Ta film combines with the copper in the Cu seed film and the Cu film formed on the Ti film. A compound with Cu (copper) is formed, and the resistance value of the barrier film is greatly increased.

However, as in the present embodiment, when Ti = 10 nm in which only a Ti film is used as a barrier film, the Ti film at the interface with the interlayer insulating film is oxidized by the moisture contained in the interlayer insulating film, and TiO _X or A reaction layer made of TiSi _X O _Y is formed. That is, the amount of Ti (titanium) that can be combined with the copper in the Cu seed film and the Cu film by the reaction between the interlayer insulating film and the Ti film is smaller than that of Ti / Ta = 10/5 nm. . For this reason, the amount of the compound of Ti (titanium) and Cu (copper) formed is small, and an increase in wiring resistance can be suppressed.

  In the present embodiment, a barrier film with low wiring resistance can be formed. Therefore, unlike the first embodiment, the thickness of the Ti film can be increased. In this embodiment, the thickness of the Ti film formed in the wiring trench is 10 nm, but it may be thicker than that. Although Ti (titanium) is inferior to Ta (tantalum) in the metal diffusion preventing function, in this embodiment, the diffusion preventing function necessary for the barrier film can be obtained by increasing the thickness of the barrier film to be formed.

In this embodiment, it is desirable to form an interlayer insulating film that easily absorbs moisture (highly hygroscopic) so that the Ti film in contact with the interlayer insulating film is easily oxidized. Here, the members constituting the first interlayer insulating film 1 and the second interlayer insulating film 6 shown in FIG. 19 are members having higher hygroscopicity than SiO ₂ (silicon dioxide), for example, SiOC (silicon carbonate). Shall be used. Since SiO ₂ (silicon dioxide) has a low hygroscopicity, the Ti film in contact with the interlayer insulating film made of SiO ₂ hardly forms a Ti oxide film, and in the wiring trench formed in the interlayer insulating film made of SiO ₂ In the case where Cu wiring is formed through a Ti film, wiring resistance is significantly increased. Since SiOC is a material that easily binds to H ₂ O (water) and easily contains moisture therein, it is suitable for forming a Ti oxide film as a barrier film.

The members of the Ti film 14a formed in the wiring groove G1 in FIG. 20 and the Ti film (not shown) formed in the wiring groove G2 in FIG. 24 are not limited to films made of pure Ti (titanium). These compounds may be used. For example, a TiN film such as TiN _X (X <1) may be used.

  In this embodiment, by using a Ti film containing Ti (titanium) with good wettability with copper as a barrier film, the embeddability of the Cu films 4 and 9 shown in FIG. 19 is improved, and the yield is improved. The reliability of the semiconductor device can be improved. Further, by using a barrier film using Ti (titanium) which is a material cheaper than Ta (tantalum), the cost of a product using a semiconductor device can be reduced.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  For example, in the first to third embodiments, the wiring for supplying a predetermined potential to the MOSFET Qn formed on the semiconductor substrate has been described as shown in FIG. 1, FIG. 17, and FIG. Can be widely applied to wiring for any purpose other than upper layer wiring of MOSFET.

  The present invention is widely used for semiconductor devices having copper wiring.

DESCRIPTION OF SYMBOLS 1 1st interlayer insulation film 2 TaN film 2a TaN film 3 Ti film 3a Ta film 4 Cu film 4a Cu seed film 5 Liner film 6 2nd interlayer insulation film 7 TaN film 7a TaN film 8 Ti film 8a Ta film 9 Cu film 9a Cu seed film 9b Cu seed film 10 Liner film 11 Void 12 TiN _X film 13 TiN _X film 14 Ti oxide film 14a Ti film 15 Ti film 16 Ti oxide film 17 Ti film 30 Source / drain region 31 Silicide layer 32 Gate electrode 33 Gate Insulating film 34 Side wall 35 Stopper insulating film BM Barrier film Ch Contact hole Cp Contact plug G1, G2 Wiring trench If Insulating film M1 Lower layer wiring M2 Upper layer wiring Qn MOSFET
SB Semiconductor substrate Sf Stopper insulating film V2 Via hole

Claims (17)

An interlayer insulating film formed on the semiconductor substrate;
A wiring groove formed in the interlayer insulating film;
A metal film mainly composed of Cu formed in the wiring trench via the first barrier film;
Have
The first barrier film includes a third barrier film containing Ta, and a second barrier film containing Ti formed on the third barrier film in contact with the metal film.   2. The semiconductor device according to claim 1, wherein the thickness of the second barrier film is less than 10 nm.   The semiconductor device according to claim 1, wherein the third barrier film is made of TaN. A lower layer wiring is formed below the wiring groove,
At the bottom of the wiring groove, a via hole reaching the lower layer wiring from the bottom surface of the wiring groove is formed,
2. The first barrier film is formed on an inner wall and a bottom portion of the via hole, and the metal film formed through the first barrier film is embedded in the via hole. Semiconductor device. An interlayer insulating film formed on the semiconductor substrate;
A wiring groove formed in the interlayer insulating film;
A metal film mainly composed of Cu formed in the wiring trench through a barrier film;
Have
The semiconductor device according to claim 1, wherein the barrier film is made of TiN _X , and the number of Ti atoms in the barrier film is larger than the number of N atoms in the barrier film. The semiconductor device according to claim 5, wherein the barrier film is made of TiN _X (where X = 0.5). A lower layer wiring is formed below the wiring groove,
At the bottom of the wiring groove, a via hole reaching the lower layer wiring from the bottom surface of the wiring groove is formed,
6. The semiconductor device according to claim 5, wherein the barrier film is formed on an inner wall and a bottom portion of the via hole, and the metal film formed through the barrier film is embedded in the via hole. An interlayer insulating film formed on the semiconductor substrate;
A wiring groove formed in the interlayer insulating film;
A metal film mainly composed of Cu formed in the wiring trench through a first barrier film made of Ti or a Ti compound;
Have
A semiconductor device, wherein a reaction layer made of TiSi _X O _Y or TiO _X is further interposed at an interface between the interlayer insulating film and the first barrier film.   9. The semiconductor device according to claim 8, wherein the interlayer insulating film contains SiOC. A lower layer wiring is formed below the wiring groove,
At the bottom of the wiring groove, a via hole reaching the lower layer wiring from the bottom surface of the wiring groove is formed,
9. The first barrier film is formed on an inner wall and a bottom portion of the via hole, and the metal film formed through the first barrier film is embedded in the via hole. Semiconductor device. (A) preparing a semiconductor substrate;
(B) forming an interlayer insulating film on the semiconductor substrate;
(C) forming a wiring groove on the upper surface of the interlayer insulating film;
(D) forming a first barrier film in the wiring trench;
(E) forming a seed film containing Cu as a main component on the surface of the first barrier film;
(F) forming a metal film containing Cu as a main component on the seed film by electroplating using the seed film as an electrode, and filling the wiring groove with the metal film;
(G) polishing an upper surface of the semiconductor substrate to expose an upper surface of the interlayer insulating film, and forming a metal wiring including the first barrier film and the metal film in the wiring groove;
Have
In the step (d), after forming a second barrier film containing Ta in the wiring trench, a second barrier film made of Ti or a Ti compound is formed on the second barrier film, whereby the second barrier film is formed. A method of manufacturing a semiconductor device, comprising forming the first barrier film having a barrier film and the third barrier film.   12. The method of manufacturing a semiconductor device according to claim 11, wherein the thickness of the third barrier film formed in the step (d) is less than 10 nm.   13. The method of manufacturing a semiconductor device according to claim 12, wherein the second barrier film is made of TaN. (A) preparing the semiconductor substrate;
(B) forming an interlayer insulating film on the semiconductor substrate;
(C) forming a wiring groove on the upper surface of the interlayer insulating film;
(D) forming a barrier film made of TiN _X in the wiring trench;
(E) forming a seed film containing Cu as a main component on the surface of the barrier film;
(F) forming a metal film containing Cu as a main component on the seed film by electroplating using the seed film as an electrode, and filling the wiring groove with the metal film;
(G) polishing the upper surface of the semiconductor substrate to expose the upper surface of the interlayer insulating film, and forming a metal wiring including the barrier film and the metal film in the wiring groove;
Have
The method of manufacturing a semiconductor device, wherein the number of Ti atoms in the barrier film is larger than the number of N atoms in the barrier film. The method for manufacturing a semiconductor device according to claim 14, wherein the barrier film is made of TiN _X (where X = 0.5). (A) preparing a semiconductor substrate;
(B) forming an interlayer insulating film on the semiconductor substrate;
(C) forming a wiring groove on the upper surface of the interlayer insulating film;
(D) forming a first barrier film in the wiring trench;
(E) forming a seed film containing Cu as a main component on the surface of the first barrier film;
(F) forming a metal film containing Cu as a main component on the seed film by electroplating using the seed film as an electrode, and filling the wiring groove with the metal film;
(G) polishing an upper surface of the semiconductor substrate to expose an upper surface of the interlayer insulating film, and forming a metal wiring including the first barrier film and the metal film in the wiring groove;
Have
In the step (d), a second barrier film containing Ti is formed in the wiring trench, and the interlayer insulating film and the second barrier film are heated by heat generated in the film forming process of the second barrier film. A method of manufacturing a semiconductor device, comprising: forming a reaction layer made of TiSi _X O _Y or TiO _{X at an} interface, and forming the first barrier film made of the second barrier film and the reaction layer.   17. The method of manufacturing a semiconductor device according to claim 16, wherein in the step (b), the interlayer insulating film containing SiOC is formed.

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