JP2009170665A - Semiconductor device and manufacturing method of semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To successfully implant Cu in a fine pattern and to suppress diffusion of Cu into an interlayer insulating film. <P>SOLUTION: In a semiconductor device, lower-layer wiring 102 is formed in an insulating film 101 on the semiconductor substrate, upper-layer wiring 112 is formed in the interlayer insulating film 104 on the insulating film 101, and the lower-layer wiring 102 and upper-layer wiring 112 are connected through a via plug 111 formed in the interlayer insulating film 104. The via plug 111 and upper-layer wiring 112 each have first and second barrier metal films 107 and 108 and a Cu film 110 laminated in order, wherein the first barrier metal film 107 contains nitrogen and the second barrier metal film 108 contains platinum group metals. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device having a Cu wiring formed by a damascene method and a method for manufacturing the semiconductor device.

  In recent years, along with high integration of semiconductor integrated circuits and reduction in chip size, miniaturization and multilayering of wirings or via plugs have been promoted. However, when wirings or via plugs are miniaturized, problems such as generation of embedding defects and deterioration of reliability such as EM (Electro Migration) occur. Therefore, Ru is currently proposed as a barrier metal film material for preventing diffusion of Cu atoms into the oxide film. Since Ru has good wettability with Cu, Ru is used as the barrier metal film material. It is possible to improve the embedding characteristic and the reliability.

  The use of Ru as a barrier metal film material is described in Patent Document 1. Hereinafter, the semiconductor device described in Patent Document 1 will be described with reference to FIG.

FIG. 4 is a cross-sectional view showing a semiconductor device formed by the method of manufacturing a semiconductor device described in Patent Document 1. In this semiconductor device, an insulating film 401 is formed on a semiconductor substrate (not shown), and a via hole (not shown) is formed in the insulating film 401. A barrier metal film 406 having a stacked structure of Ta film 406a / WNC film 406b / Ru film 406c is formed on the side wall and bottom of the via hole. A film 409 is formed. As a result, a via 411 including the barrier metal film 406 and the Cu film 409 is formed in the via hole. An etching stop film 403 is formed on the insulating film 401 and the via 411. An insulating film 404 is formed on the etching stopper film 403, and a protective insulating film 405 is formed on the insulating film 404. In the etching stopper film 403, the insulating film 404, and the protective insulating film 405, a wiring groove (not shown) connected to the via 411 is formed. A barrier metal film 407 having a laminated structure of Ta film 407a / WNC film 407b / Ru film 407c is formed on the sidewall and bottom of the wiring trench. A Cu film 410 is formed on the barrier metal film 407 having a stacked structure of Ta film 407a / WNC film 407b / Ru film 407c so as to fill the wiring trench. As a result, a barrier metal film 407 having a stacked structure of Ta film 407a / WNC film 407b / Ru film 407c and a wiring 412 made of Cu film 410 are formed in the wiring trench.
JP 2007-180313 A

  However, the characteristics of Ru used for the barrier metal film of the semiconductor device formed by the manufacturing method disclosed in Patent Document 1 have the following problems. That is, although Ru used as a material for the barrier metal films 406 and 407 has an advantage of good wettability with Cu, since Ru itself is polycrystalline, diffusion of Cu atoms into the interlayer insulating film is possible. It is a problem that the barrier property against is poor. From the above, the semiconductor device disclosed in Patent Document 1 has a problem that the reliability of the semiconductor device deteriorates due to diffusion of Cu atoms into the insulating film.

  An object of the present invention is to suppress diffusion of Cu into an interlayer insulating film while improving the embedding characteristics of Cu in a fine pattern.

  In the first semiconductor device of the present invention, the first interlayer insulating film is formed on the semiconductor substrate, the first trench is formed in the first interlayer insulating film, and the first trench is formed in the first trench. The conductor is embedded to form the first wiring. A second interlayer insulating film is formed on the first wiring, and a second trench is formed in the second interlayer insulating film. A first barrier metal film and a second barrier metal film are formed in this order on the bottom and side walls of the second trench, and the second trench metal film is embedded in the second trench. Is provided with a metal film. Here, the first barrier metal film is made of a conductor containing nitrogen, and the second barrier metal film contains a platinum group element. The first barrier metal film, the second barrier metal film, and the metal film constitute a second wiring. In the second interlayer insulating film, a via hole is further formed so as to connect the first wiring and the second wiring, and a conductor is embedded in the via hole to form a via plug.

  Thereby, it is possible to suppress the diffusion of Cu into the interlayer insulating film while improving the embedding characteristics of Cu in a fine pattern.

  In the second semiconductor device of the present invention, unlike the first semiconductor device of the present invention, the first barrier metal film and the second barrier metal film are formed on the side wall of the second trench. A third barrier metal film is formed on the bottom surface of the trench, and the metal film of the second wiring is provided on the second barrier metal film and the third barrier metal film in the second trench. ing. Even in this case, it is possible to suppress the diffusion of Cu into the interlayer insulating film while improving the embedding characteristics of Cu with a fine pattern.

  In the method for manufacturing a semiconductor device of the present invention, first, a first wiring is formed by embedding a conductor in a first trench formed in a first interlayer insulating film on a semiconductor substrate (step (a)). Next, a second interlayer insulating film is formed on the first wiring (step (b)), and then a via hole is formed in the second interlayer insulating film so as to reach the first wiring (step). (C)) Then, a second trench is formed in the second interlayer insulating film so as to communicate with the via hole (step (d)), and then the sidewall and bottom of the via hole and the sidewall and bottom of the second trench are formed. A first barrier metal film made of a conductor containing nitrogen is deposited so as to cover (step (e)), and a second barrier metal film containing a platinum group element is covered so as to cover the first barrier metal film After depositing (step (f)), in the via hole and Embed copper or copper alloy in the second trench (step (g)).

  As a result, the adhesion between Cu and the barrier metal is improved and the barrier property is improved, so that it is possible to suppress the diffusion of Cu into the interlayer insulating film while improving the embedding characteristic of Cu in a fine pattern. It is.

  According to the present invention, fine pattern Cu can be embedded well, and diffusion of Cu into the interlayer insulating film can be suppressed.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the following, the same components are denoted by the same reference numerals, and the description thereof may be omitted. Further, the present invention is not limited to the following embodiment.

(First embodiment)
Hereinafter, a method for manufacturing a semiconductor device according to the first embodiment of the present invention will be described with reference to FIGS. FIG. 1A to FIG. 1G are cross-sectional views showing respective steps of a semiconductor device manufacturing method according to the first embodiment of the present invention.

  First, as shown in FIG. 1A, an insulating film (first film) made of, for example, a SiOC film is formed on a semiconductor substrate (not shown) on which elements such as transistors are formed by a CVD (Chemical Vapor Deposition) method. Interlayer insulating film) 101 is deposited. Next, a first trench is formed in the insulating film 101, and a conductor made of Cu is embedded in the first trench to form a lower layer wiring (first wiring) 102 (step (a)). At this time, a barrier metal film is preferably provided on the side wall and the bottom of the lower layer wiring 102. Here, the kind of barrier metal film and the formation method thereof will be described in detail when the cross-sectional views shown in FIGS. 1C and 1D described later are described. Thereafter, an insulating barrier film 103 is formed on the insulating film 101 and the lower wiring 102 by a CVD method. Here, as the insulating barrier film 103, a SiCO film or a SiCN film can be used. Thereafter, an interlayer insulating film (second interlayer insulating film) 104 is formed on the insulating barrier film 103 by a CVD method (step (b)). Here, a carbon-containing silicon oxide film (SiOC film) can be used as the interlayer insulating film 104.

  Next, as shown in FIG. 1B, a photoresist (not shown) having a via hole pattern is deposited on the interlayer insulating film 104 by photolithography. Thereafter, dry etching is performed using the photoresist as a mask, the interlayer insulating film 104 is removed, and a via hole 105 reaching the insulating barrier film 103 is formed (step (c)). Here, a carbon fluoride (CF) gas can be used as the etching gas. When this dry etching process is completed, the photoresist having the via hole pattern is removed by ashing. Thereafter, a photoresist (not shown) having a trench pattern is deposited on the interlayer insulating film 104 by photolithography. Thereafter, dry etching is performed using the photoresist as a mask, the interlayer insulating film 104 is removed, and a trench (second trench) 106 communicating with the via hole 105 is formed (step (d)). Here, a carbon fluoride (CF) gas can be used as the etching gas. When this dry etching process is completed, the photoresist having the trench pattern is removed by ashing. Thereafter, the insulating barrier film 103 exposed on the bottom surface of the via hole 105 is removed by dry etching. Here, a carbon fluoride (CF) gas can be used as the etching gas.

Next, as shown in FIG. 1C, a first barrier metal film 107 is deposited by sputtering so as to cover the sidewall and bottom of the via hole 105 and the sidewall and bottom of the trench 106 (step (e)). . Here, as a method of forming the first barrier metal film 107, ruthenium nitride (RuN) having an amorphous structure by a reactive sputtering method in which nitrogen (N ₂ ) gas is introduced into ruthenium (Ru) or tantalum (Ta) or the like. Alternatively, it is preferable to use a method of forming tantalum nitride (TaN) or the like. The film formation conditions for sputtering are as follows, for example.
<Sputtering conditions>
Target power: 10000W
Substrate Bias power: 500W
DC-Coil power: 0W
RF-Coil power: 2000W
Ar flow rate: 15 sccm
N flow rate: 35 sccm (when forming a RuN film)
Here, it is considered that copper moves through the barrier metal film via the grain boundary in the barrier metal film and diffuses into the interlayer insulating film. Since the atomic arrangement is irregular in the amorphous structure compared to the crystal structure, the barrier metal film in the amorphous structure has a smaller number of crystal grain boundaries in the barrier metal film than in the barrier metal film in the crystalline structure. It becomes difficult to secure. As a result, if a barrier metal film having an amorphous structure is used, it is difficult for copper to move in the barrier metal film, so that diffusion to the interlayer insulating film can be suppressed, and the barrier property against copper diffusion is enhanced.

  Further, if the first barrier metal film 107 is formed on the interlayer insulating film 104 so as to have a film thickness of 2 nm or more and 10 nm or less, the first barrier metal film 107 is formed so as to cover the side wall and bottom of the via hole 105 and the side wall and bottom of the trench 106. This barrier metal film 107 can be formed, and sufficient barrier properties against copper diffusion can be ensured. The film thickness of the first barrier metal film 107 is preferably within the above range, but a sufficient barrier property against copper diffusion can be ensured, and the side wall and bottom of the via hole 105 and the side wall and bottom of the trench 106 can be secured. If it can be covered, it is not limited to the said range.

Next, as shown in FIG. 1D, a second barrier metal film 108 is deposited on the first barrier metal film 107 by sputtering (step (f)). As the second barrier metal film 108, ruthenium (Ru) or ruthenium nitride (RuN) is preferably used. The film formation conditions for sputtering are as follows, for example.
<Sputtering conditions>
Target power: 10000W
Substrate Bias power: 500W
DC-Coil power: 0W
RF-Coil power: 2000W
Ar flow rate: 15 sccm
N flow rate: 35 sccm (when forming a RuN film)
When a RuN film is formed as the second barrier metal film 108, since the second barrier metal film 108 has an amorphous structure, its atomic arrangement becomes irregular, and the barrier property against copper diffusion becomes high as described above.

  Further, if the second barrier metal film 108 is formed on the interlayer insulating film 104 so as to have a thickness of 2 nm or more and 10 nm or less, the second barrier metal film 108 is formed so as to cover the sidewall and bottom of the via hole 105 and the sidewall and bottom of the trench 106. 2 barrier metal film 108 can be formed, and a sufficient barrier property against copper diffusion can be secured. The film thickness of the second barrier metal film 108 is preferably within the above range, but a sufficient barrier property against copper diffusion can be secured, and the side wall and bottom part of the via hole 105 and the side wall and bottom part of the trench 106 can be secured. If it can be covered, it is not limited to the said range.

  Subsequently, as shown in FIG. 1E, a Cu seed film 109 is deposited on the second barrier metal film 108 by sputtering.

  Subsequently, as shown in FIG. 1F, a Cu film (metal film) 110 is deposited so as to fill the via hole 105 and the trench 106 by electrolytic plating.

  Then, as shown in FIG. 1G, the excess Cu film 110, the first barrier metal film 107, and the second barrier metal film 108 protruding from the trench 106 are polished by CMP (Chemical Mechanical Polishing). Then, the interlayer insulating film 104 is exposed in portions other than the trench 106, and the Cu film 110 is left in the via hole 105 and the trench 106. As a result, a via plug 111 in which the first barrier metal film 107, the second barrier metal film 108, and the Cu film 110 are sequentially deposited is formed in the via hole 105, and the first barrier metal film is formed in the trench 106. An upper layer wiring 112 deposited in the order of the film 107, the second barrier metal film 108, and the Cu film 110 is formed (step (g)).

  By repeating the steps described with reference to FIGS. 1A to 1G, a semiconductor device having a multilayer wiring structure can be formed.

  In the semiconductor device formed by the semiconductor device manufacturing method according to the first embodiment, the first barrier metal film 107 and the second barrier metal film 108 improve the barrier property against copper diffusion. Here, nitrogen gas is introduced especially when the first barrier metal film 107 is formed. This nitrogen gas (N) is useful for making the first barrier metal film 107 amorphous. Has a positive effect. In other words, the introduction of nitrogen gas causes the first barrier metal film 107 to have an amorphous structure with an irregular atomic arrangement, so that the first barrier metal film 107 has fewer crystal grain boundaries, which are dominant diffusion paths. Therefore, the barrier property of Cu diffusion is improved.

  In the first embodiment, pure Cu is used as the Cu seed film 109, but a Cu alloy seed film such as Cu-Al may be used. When the Cu alloy seed film is used, the wettability between the Ru barrier and Cu is improved as compared with the case where pure Cu is used, so that the Cu embedding characteristic can be improved.

  In the first embodiment, ruthenium (Ru) or tantalum (Ta) is used as the metal used for the first barrier metal film 107, and ruthenium (Ru) is used as the metal used for the second barrier metal film 108. As the first barrier metal film 107 and the second barrier metal film 108, for example, rhodium (Rh), palladium (Pd), osmium (Os), iridium (Ir), platinum (Pt), etc. The platinum group element may be used. Since such a platinum group atom has low specific resistance and good adhesion to Cu, the same effect as the above can be expected.

(Second Embodiment)
Hereinafter, a method for manufacturing a semiconductor device according to the second embodiment of the present invention will be described with reference to FIGS. 2 (a) to 2 (i). FIG. 2A to FIG. 2I are cross-sectional views showing respective steps of a semiconductor device manufacturing method according to the second embodiment of the present invention. Here, the steps for forming the cross-sectional views shown in FIGS. 2A to 2D are the same as the steps for forming the cross-sectional views shown in FIGS. 1A to 1D, respectively. The process for forming the cross-sectional view shown in FIG. 2 (i) is the same as the process for forming the cross-sectional views shown in FIG. 1 (e) to FIG. 1 (g). A process for forming the cross-sectional view shown in FIG.

First, as shown in FIG. 2E, the first barrier metal film 107 and the second barrier metal film 108 formed on the bottom surface of the via hole 105 are removed by Ar resputtering, and the bottom surface of the via hole 105 is formed. To expose the lower layer wiring 102 (step (h)). At this time, the first barrier metal film 107 and the second barrier metal film 108 formed on the bottom surface of the trench 106 are also removed together. For example:
<Resputtering conditions>
Target power: 500W
Substrate Bias power: 400W
DC-Coil power: 0W
RF-Coil power: 1200W
Ar flow rate: 15 sccm
By this resputtering, a concave digging portion 201 is formed on the upper surface of the lower layer wiring 102. The digging portion 201 has an effect of improving the EM resistance of the via plug 111 and reducing the via resistance. This effect will be specifically described later.

Next, as shown in FIG. 2F, a third barrier metal film 113 is deposited on the bottom surface of the via hole 105, the bottom surface of the trench 106, and the second barrier metal film 108 by sputtering (step). (I)). Here, as a method of forming the third barrier metal film 113, a method of forming ruthenium nitride (RuN) or the like having an amorphous structure by a reactive sputtering method in which nitrogen (N ₂ ) gas is introduced into ruthenium (Ru) or the like. Can be used. The film formation conditions for sputtering are as follows, for example.
<Sputtering conditions>
Target power: 10000W
Substrate Bias power: 500W
DC-Coil power: 0W
RF-Coil power: 2000W
Ar flow rate: 15 sccm
N flow rate: 35 sccm (when forming RuN)
When a RuN film is formed as the third barrier metal film 113, the third barrier metal film 113 has an amorphous structure, so that the atomic arrangement thereof is irregular, and thus the barrier property against copper diffusion is enhanced.

  Further, if the third barrier metal film 113 is formed on the interlayer insulating film 104 so as to have a thickness of 2 nm or more and 10 nm or less, the third barrier metal film 113 is formed so as to cover the sidewall and bottom of the via hole 105 and the sidewall and bottom of the trench 106. This is preferable because a sufficient barrier property against copper diffusion can be secured. The film thickness of the third barrier metal film 113 is preferably within the above range, but a sufficient barrier property against copper diffusion can be ensured, and the side wall and bottom of the via hole 105 and the side wall and bottom of the trench 106 can be secured. As long as it can be covered, it may be outside the above range. Here, the sufficient barrier property against Cu diffusion means that it has a sufficient barrier property against Cu diffusion from the side wall and bottom of the trench 106.

  In the semiconductor device according to the second embodiment, unlike the semiconductor device according to the first embodiment, the first barrier metal film 107 and the second barrier are formed on the bottom of the via plug 111 and the bottom of the upper wiring 112. The metal film 108 is not formed and only the third barrier metal film 113 is formed.

  Here, when comparing a barrier metal film (such as Ru film or Ta film) and a copper film, it is known that the barrier metal film has a higher resistivity than the copper film. Therefore, it is necessary to reduce the resistance of the via plug 111 and the wiring (the lower wiring 102 and the upper wiring 112) while ensuring the barrier property against Cu diffusion. According to the semiconductor device according to the second embodiment, only one barrier metal film is formed at the bottom of the via plug 111 and the bottom of the upper wiring 112 as compared with the semiconductor device according to the first embodiment. Therefore, it is possible to further reduce the resistance of the via plug 111 and the wiring.

  A digging portion 201 is formed on the upper surface of the lower layer wiring 102. Since the digging portion 201 is formed, the bottom of the via plug 111 has a pointed shape (convex shape) compared to the bottom of the via plug 111 in the first embodiment. Accordingly, the bottom of the via plug 111 in the semiconductor device of the second embodiment has a larger surface area than the bottom of the via plug 111 in the semiconductor device of the first embodiment. As a result, since local concentration of current can be suppressed, the EM resistance can be further improved as compared with the first embodiment.

  In the second embodiment, pure Cu is used as the Cu seed film 109, but a Cu alloy seed film such as Cu-Al may be used. By using a Cu alloy seed film as the Cu seed film 109, the wettability between the Ru barrier and Cu is improved, so that the Cu embedding characteristic can be improved.

  In the second embodiment, ruthenium (Ru) or tantalum (Ta) is used as the metal used for the first barrier metal film 107, and ruthenium (Ru) is used as the metal used for the second barrier metal film 108. ) And ruthenium (Ru) was used as the metal used for the third barrier metal film 113, but the first barrier metal film 107, the second barrier metal film 108, and the third barrier metal film 113 are used. As the metal used, for example, a platinum group element such as rhodium (Rh), palladium (Pd), osmium (Os), iridium (Ir), or platinum (Pt) may be used. Since platinum group elements have low specific resistance and good adhesion to Cu, the same effects as described above can be expected.

(Third embodiment)
A method for manufacturing a semiconductor device according to the third embodiment of the present invention will be described below with reference to FIGS. 3 (a) to 3 (h). FIG. 3A to FIG. 3H are cross-sectional views showing respective steps of the method for manufacturing a semiconductor device according to the third embodiment of the present invention. Here, the process of forming the cross-sectional views shown in FIGS. 3A to 3D is the same as the process of forming the cross-sectional views shown in FIGS. 1A to 1D, and FIGS. The step of forming the cross-sectional view shown in FIG. 3 (h) is the same as the step of forming the cross-sectional views shown in FIG. 1 (e) to FIG. 1 (g). A process of forming the cross-sectional view shown in FIG.

  As shown in FIG. 3E, moisture is degassed from the interlayer insulating film 104 by heat treatment, the first barrier metal film 107 is oxidized, and the interface between the interlayer insulating film 104 and the first barrier metal film 107 is obtained. Then, a fourth barrier metal film 114 is formed (step (j)). Here, the heat treatment is preferably performed at a temperature of 100 ° C. or higher and 400 ° C. or lower. Here, if it is 400 degrees C or less, it can heat-process within the range which does not have a problem on a process. The fourth barrier metal film 114 is oxygen-containing ruthenium nitride (RuNO) or oxygen-containing tantalum nitride (TaNO). The film thickness of the fourth barrier metal film 114 is formed to be 40% to 60% of the film thickness of the first barrier metal film 107 on the sidewall of the via hole 105 and the sidewall and bottom of the trench 106. However, it is not limited to this value.

  In the method for manufacturing a semiconductor device according to the third embodiment, compared to the method for manufacturing a semiconductor device according to the first embodiment, the fourth barrier metal film 114 further containing oxygen in RuN or TaN is formed in the first manner. The barrier metal film 107 and the interlayer insulating film 104 can be formed. Here, the fourth barrier metal film 114 is made of oxygen-containing ruthenium nitride (RuNO) or oxygen-containing tantalum nitride (TaNO) formed by degassing moisture from the interlayer insulating film 104. Oxygen, like nitrogen, has a useful effect in forming an amorphous structure. Therefore, since the atomic arrangement of the first barrier metal film 107 has an irregular amorphous structure, the first barrier metal film 107 has fewer crystal grain boundaries, which are the dominant diffusion paths, and has a barrier property against Cu diffusion. Can be improved. Further, since Ru does not lose its conductivity even when oxidized, there is no problem that the resistance value of the fourth barrier metal film 114 is increased by the heat treatment.

  Further, the oxygen-containing ruthenium nitride (RuNO) or the oxygen-containing tantalum nitride (TaNO), in other words, the fourth barrier metal film 114 is formed only at a location where the first barrier metal film 107 is in contact with the interlayer insulating film 104. Therefore, it is not formed at the bottom of the via hole 105. Therefore, even if the fourth barrier metal film 114 is formed, it is possible to suppress an increase in via resistance.

  In the third embodiment, pure Cu is used as the Cu seed film 109, but a Cu alloy seed film such as Cu-Al may be used. By using a Cu alloy seed film as the Cu seed film 109, the wettability between the Ru barrier and Cu is improved, so that the Cu embedding characteristic can be improved.

  In the third embodiment, ruthenium (Ru) or tantalum (Ta) is used as the metal used for the first barrier metal film 107, and ruthenium (Ru) is used as the metal used for the second barrier metal film 108. The metal used for the first barrier metal film 107 and the second barrier metal film 108 is, for example, rhodium (Rh), palladium (Pd), osmium (Os), iridium (Ir), or platinum. Platinum group elements such as (Pt) may be used. Since these platinum group elements have low specific resistance and good adhesion to Cu, the same effects as the above can be expected.

  Further, the fourth barrier metal film 114 may be formed on the semiconductor device according to the second embodiment. Specifically, in the second embodiment, it is formed between the first barrier metal film 107 and the interlayer insulating film 104 formed on the sidewall of the via hole 105 and the sidewall of the trench 106, and at the bottom of the trench 106. A fourth barrier metal film 114 may be formed between the third barrier metal film and the interlayer insulating film 104. Here, as a method of forming the fourth barrier metal film 114, the first barrier metal film 107 is oxidized by degassing the interlayer insulating film 104 by heat treatment, as in the third embodiment. By doing so, there is an effect that the barrier property against Cu diffusion of the via plug and wiring of the semiconductor device in the second embodiment can be further improved.

  In the first to third embodiments, the film thicknesses of the first to fourth barrier metal films are defined. However, each barrier metal film is provided on the side wall of the via plug as long as the embedding characteristics of the via plug are not impaired. Need to form.

  In the first and third embodiments, the example in which the wiring is formed by dual damascene is shown, but the present invention can also be applied to the case where the wiring is formed by single damascene.

  The present invention can be used, for example, in a method of manufacturing a semiconductor device having wiring formed by a damascene method such as miniaturized and integrated LSI (large scale integration).

Sectional drawing which shows each process of the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. Sectional drawing which shows each process of the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention. Sectional drawing which shows each process of the manufacturing method of the semiconductor device which concerns on the 3rd Embodiment of this invention. Sectional view showing a conventional semiconductor device

Explanation of symbols

101 Insulating film
102 Lower layer wiring (first wiring)
103 Insulating barrier film
104 Interlayer insulating film 105 Via hole
106 trench (second trench)
107 first barrier metal film
108 Second barrier metal film
109 Cu seed film 110 Cu film
111 Via plug
112 Upper layer wiring (second wiring)
113 Third barrier metal film
114 Fourth barrier metal film

Claims (22)

A first wiring formed in a first trench formed in the first interlayer insulating film on the semiconductor substrate, and made of a conductor;
A second interlayer insulating film provided on the first wiring;
A second trench formed in the second interlayer insulating film;
A first barrier metal film provided on a bottom and a side wall of the second trench and made of a conductor containing nitrogen;
A second barrier metal film containing a platinum group element provided on the first barrier metal film at the bottom and side walls of the second trench;
A metal film formed on the second barrier metal film in the second trench and made of copper or a copper alloy;
A second wiring having the first barrier metal film, the second barrier metal film, and the metal film;
It is provided in a via hole formed in the second interlayer insulating film so as to connect the first wiring and the second wiring, and includes a via plug made of a conductor. Semiconductor device. A first wiring formed in a first trench formed in the first interlayer insulating film on the semiconductor substrate, and made of a conductor;
A second interlayer insulating film provided on the first wiring;
A second trench formed in the second interlayer insulating film;
A first barrier metal film provided on a sidewall of the second trench and made of a conductor containing nitrogen;
A second barrier metal film containing a platinum group element provided on the first barrier metal film on the side wall of the second trench;
A third barrier metal film made of a conductor containing nitrogen, provided on the bottom of the second trench and on the second barrier metal film in the second trench;
A metal film made of copper or a copper alloy provided on the third barrier metal film in the second trench;
A second wiring having the first barrier metal film, the second barrier metal film, the third barrier metal film, and the metal film;
It is provided in a via hole formed in the second interlayer insulating film so as to connect the first wiring and the second wiring, and includes a via plug made of a conductor. Semiconductor device. A digging portion having a concave shape is formed on the upper surface of the first wiring,
The semiconductor device according to claim 2, wherein the via plug is provided in the digging portion.   A fourth barrier metal film made of a conductor containing oxygen and provided between the first barrier metal film and the second interlayer insulating film at the bottom and side walls of the second trench; The semiconductor device according to claim 1, comprising:   The sidewall of the second trench is provided between the first barrier metal film and the second interlayer insulating film, and the third barrier metal film is formed at the bottom of the second trench. 4. The semiconductor device according to claim 2, further comprising a fourth barrier metal film that is provided between the second interlayer insulating film and made of a conductor containing oxygen. The first barrier metal film is further provided between the bottom and side walls of the via hole and the via plug,
The fourth barrier metal film is provided between the first barrier metal film formed on the side wall of the via hole and the second interlayer insulating film, and is formed on the bottom of the via hole. 5. The semiconductor device according to claim 4, wherein the semiconductor device is not provided between the first barrier metal film and the first wiring. The third barrier metal film is further provided between the bottom of the via hole and the via plug, and the first barrier metal film is further provided between the side wall of the via hole and the via plug. And
The fourth barrier metal film is provided between the first barrier metal film formed on the side wall of the via hole and the second interlayer insulating film, and is formed on the bottom of the via hole. 6. The semiconductor device according to claim 5, wherein the semiconductor device is not provided between the third barrier metal film formed and the first wiring.   3. The semiconductor device according to claim 1, wherein the conductor contained in the first barrier metal film contains the nitrogen and a platinum group element or tantalum.   The semiconductor device according to claim 2, wherein the conductor contained in the third barrier metal film contains the nitrogen and a platinum group element or tantalum.   The semiconductor device according to claim 4, wherein the fourth barrier metal film further contains nitrogen.   11. The semiconductor according to claim 4, wherein the conductor contained in the fourth barrier metal film includes the nitrogen and a platinum group element or tantalum. apparatus.   12. The platinum group element according to claim 8, 9 and 11, wherein the platinum group element is ruthenium (Ru), rhodium (Rh), palladium (Pd), osmium (Os), iridium (Ir) or platinum (Pt). The semiconductor device according to any one of the above. A step (a) of forming a first wiring by embedding a conductor in a first trench formed in a first interlayer insulating film on a semiconductor substrate;
A step (b) of forming a second interlayer insulating film on the first wiring after the step (a);
(C) forming a via hole in the second interlayer insulating film so as to reach the first wiring after the step (b);
After the step (c), a step (d) of forming a second trench in the second interlayer insulating film so as to communicate with the via hole;
After the step (d), a step (e) of depositing a first barrier metal film made of a nitrogen-containing conductor so as to cover the side wall and bottom of the via hole and the side wall and bottom of the second trench. When,
After the step (e), a step (f) of depositing a second barrier metal film containing a platinum group element so as to cover the first barrier metal film;
After the step (f), a step (g) of burying copper or a copper alloy in the via hole and in the second trench is provided. A step (h) of removing the first barrier metal film and the second barrier metal film formed on the bottom of the via hole between the step (f) and the step (g);
Between the step (h) and the step (g), a third barrier metal film made of a conductor containing nitrogen is formed on the bottom of the via hole and the second barrier metal film. 14. The method for manufacturing a semiconductor device according to claim 13, further comprising a step (i).   15. The method of manufacturing a semiconductor device according to claim 14, wherein the step (h) further includes a step of forming a digging portion having a concave shape on an upper surface of the first wiring.   A heat treatment is performed between the step (f) and the step (g), whereby a first electrode made of an oxygen-containing conductor is formed between the first barrier metal film and the second interlayer insulating film. 15. The method of manufacturing a semiconductor device according to claim 13, further comprising a step (j) of forming a barrier metal film.   The method of manufacturing a semiconductor device according to claim 16, wherein the heat treatment in the step (j) is performed at a temperature of 100 ° C. to 400 ° C.   The method for manufacturing a semiconductor device according to claim 13, wherein a conductor containing the nitrogen and a platinum group element or tantalum is used as the conductor contained in the first barrier metal film.   The method for manufacturing a semiconductor device according to claim 14, wherein a conductor containing the nitrogen and a platinum group element or tantalum is used as the conductor contained in the third barrier metal film.   17. The method of manufacturing a semiconductor device according to claim 16, wherein a barrier metal film containing nitrogen is further used as the fourth barrier metal film.   21. The method of manufacturing a semiconductor device according to claim 16, wherein a conductor containing the oxygen and a platinum group element or tantalum is used as the conductor contained in the fourth barrier metal film.   The platinum group element is ruthenium (Ru), rhodium (Rh), palladium (Pd), osmium (Os), iridium (Ir), or platinum (Pt). A method for manufacturing a semiconductor device according to any one of the above.

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