KR100526452B1 - Method for forming contact electrode of semiconductor device - Google Patents

Method for forming contact electrode of semiconductor device

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KR100526452B1
KR100526452B1 KR1019970077333A KR19970077333A KR100526452B1 KR 100526452 B1 KR100526452 B1 KR 100526452B1 KR 1019970077333 A KR1019970077333 A KR 1019970077333A KR 19970077333 A KR19970077333 A KR 19970077333A KR 100526452 B1 KR100526452 B1 KR 100526452B1
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forming
contact electrode
semiconductor device
contact hole
barrier metal
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KR1019970077333A
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KR19990057284A (en
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윤성렬
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects

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  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 반도체 장치의 콘택 전극 형성방법에 관한 것으로서, 특히 콘택 전극 형성방법은 실리콘 기판 전면에 반도체 소자를 상부 금속 배선과 전기적으로 절연하기 위한 층간 절연막을 형성하며, 층간 절연막 내에 콘택 전극의 영역을 확보하기 위한 콘택홀을 형성하며, 콘택홀을 가지는 층간 절연막 내에 장벽 금속막을 형성하며, 열공정으로 장벽 금속막 표면에 실리콘 이온을 주입하며, 콘택홀 내에 금속층을 매립하여 콘택 전극을 형성하는 것을 특징으로 한다. 본 발명에 의하면, 콘택홀 내의 장벽 금속막 표면에 실리콘 이온을 주입하고 알루미늄을 증착하므로서 활성 영역과 콘택 전극의 접합 스파이킹을 미연에 방지할 수 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a contact electrode of a semiconductor device, and in particular, a method for forming a contact electrode for forming an interlayer insulating film for electrically insulating a semiconductor device from an upper metal wiring on a front surface of a silicon substrate. Forming a contact hole for securing, forming a barrier metal film in the interlayer insulating film having the contact hole, implanting silicon ions into the barrier metal film surface by a thermal process, and forming a contact electrode by embedding the metal layer in the contact hole. It is done. According to the present invention, it is possible to prevent junction spiking between the active region and the contact electrode by injecting silicon ions into the barrier metal film surface in the contact hole and depositing aluminum.

Description

반도체 장치의 콘택 전극 형성방법Method for forming contact electrode of semiconductor device

본 발명은 반도체 장치의 제조 방법에 관한 것으로서, 특히 반도체 소자와 상부 배선 간의 콘택 접속시 배선의 전기적 특성을 향상시킬 수 있는 반도체 장치의 콘택 전극 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a contact electrode of a semiconductor device capable of improving electrical characteristics of a wiring when contacting a semiconductor device and an upper wiring.

반도체 장치의 배선은 하부 구조물과 상부 구조물을 연결하기 위한 수단으로서 반도체 장치의 속도, 수율 및 신뢰성을 결정하는 요인이 되기 때문에 반도체 제조 공정중 가장 중요한 위치를 점유하고 있다. 최근 반도체 장치는 디자인 룰이 점점 미세화됨에 따라 복잡한 다층 배선구조를 가지게 되었다.The wiring of the semiconductor device occupies the most important position in the semiconductor manufacturing process because it is a factor for determining the speed, yield and reliability of the semiconductor device as a means for connecting the lower structure and the upper structure. In recent years, semiconductor devices have complicated multilayer wiring structures as the design rules become more and more sophisticated.

종래의 집적도가 낮은 반도체 장치의 경우에는 배선 연결을 위한 콘택홀의 금속 매립 방법이 크게 문제가 되지 않았지만, 최근 집적도가 높은 반도체 장치의 경우에는 개구부(콘택홀이나 비아)의 직경이 작이진 동시에 어스펙트비도 커졌기 때문에 이 금속 매립 방법이 심각한 문제가 되었다.In the case of the conventional low-density semiconductor device, the method of burying the metal in the contact hole for wiring connection has not been a problem, but in the case of the recent high-density semiconductor device, the diameter of the openings (contact holes or vias) is small and at the same time. Because of the increased rain, this method of landfilling became a serious problem.

한편, 고집적 반도체 장치의 콘택 전극 배선 공정은 약 500℃ 이상의 고온에서 스퍼터링 방식으로 알루미늄 및 텅스텐을 증착하기 때문에 열적 소자의 스트레스를 일으킨다. 특히, 저저항성의 알루미늄을 사용한 콘택 전극은 소스/드레인 영역으로 알루미늄이 확산되어 접합 스파이킹을 일으키기 때문에 반도체 소자의 접합 파괴 및 누설 전류의 원인으로 작용한다. 이를 방지하기 위해 콘택 전극은 알루미늄의 증착시 1% 미만의 실리콘을 함유한 막질을 사용하고 있지만 이러한 알루미늄으로도 접합 스파이킹을 완전하게 해결하지는 못하였다. 이에 반도체 장치는 콘택 전극을 형성하기 전에 실리콘으로 알루미늄의 확산을 방지하기 위하여 전기 전도도 특성이 우수한 장벽 금속막을 추가해서 형성하였다.On the other hand, the contact electrode wiring process of the highly integrated semiconductor device causes stress of the thermal device because aluminum and tungsten are deposited by sputtering at a high temperature of about 500 ° C or higher. In particular, a contact electrode using low-resistance aluminum acts as a cause of junction breakdown and leakage current of the semiconductor device because aluminum diffuses into the source / drain region to cause junction spikes. In order to prevent this, the contact electrode uses a film quality containing less than 1% of silicon in the deposition of aluminum, but even aluminum does not completely solve the joint spiking. Accordingly, the semiconductor device was formed by adding a barrier metal film having excellent electrical conductivity to prevent diffusion of aluminum into silicon before forming the contact electrode.

그러나, 이러한 장벽 금속막 증착 방법은 후속 금속 식각 공정에서 실리콘을 석출시켜 금속 저항을 높이며, 동시에 반도체 소자의 누설 전류 및 금속 배선을 열화시키는 문제점이 있었다.However, such a barrier metal film deposition method has a problem of depositing silicon in a subsequent metal etching process to increase metal resistance, and at the same time, deteriorate leakage current and metal wiring of a semiconductor device.

본 발명의 목적은 상기와 같은 종래 기술의 문제점을 해결하기 위하여 콘택홀 내에 알루미늄을 증착하기 전, 장벽 금속막 표면에 실리콘 이온을 주입하고 알루미늄을 증착하므로서 기판의 활성 영역과 콘택 전극의 접합 스파이킹을 미연에 방지할 수 있는 반도체 장치의 콘택 전극 형성방법을 제공하는데 있다.An object of the present invention is to spike the junction between the active region of the substrate and the contact electrode by injecting silicon ions into the barrier metal film surface and depositing aluminum before depositing aluminum in the contact hole in order to solve the problems of the prior art as described above The invention provides a method for forming a contact electrode of a semiconductor device that can be prevented.

상기 목적을 달성하기 위하여 본 발명은 반도체 기판의 활성 영역 위에 형성된 반도체 소자와 상부의 금속 배선을 상호 연결하기 위한 콘택 전극을 형성함에 있어서, 상기 기판 전면에 반도체 소자를 상부 금속 배선과 전기적으로 절연하기 위한 층간 절연막을 형성하는 단계; 상기 층간 절연막 내에 콘택 전극의 영역을 확보하기 위한 콘택홀을 형성하는 단계; 상기 콘택홀을 가지는 층간 절연막 내에 장벽 금속막을 형성하는 단계; 열공정으로 장벽 금속막 표면에 실리콘 이온을 주입하는 단계; 및 상기 콘택홀 내에 금속층을 매립하여 콘택 전극을 형성하는 단계를 포함하는 것을 특징으로 한다.In order to achieve the above object, the present invention provides a contact electrode for interconnecting a semiconductor device formed on an active region of a semiconductor substrate with an upper metal wiring, wherein the semiconductor device is electrically insulated from the upper metal wiring on the entire surface of the substrate. Forming an interlayer insulating film for; Forming a contact hole in the interlayer insulating layer to secure a region of the contact electrode; Forming a barrier metal film in the interlayer insulating film having the contact hole; Implanting silicon ions into the barrier metal film surface by a thermal process; And forming a contact electrode by filling a metal layer in the contact hole.

본 발명의 제조 방법에 있어서, 상기 열공정은 급속 열공정을 실시하는데, 이때 조건은 5～15sccm의 SiH4 가스량, 450～650℃의 반응 온도, 10～30초의 반응 시간으로 실시한다. 또는 상기 열공정은 반응로 열공정을 실시하는데, SiH4 + N2 가스, 430～500℃의 반응 온도, 10～20분의 반응 시간으로 실시한다.In the method according to the present invention, the tear Chung for carrying out the rapid thermal process, wherein the condition is carried out by the reaction temperature, 10 to 30 seconds of reaction time of the SiH 4 gas of 5 ~ 15sccm, 450 ~ 650 ℃ . Alternatively, the thermal step is carried out in the reaction furnace thermal step, the reaction temperature of SiH 4 + N 2 gas, 430 ~ 500 ℃, 10 to 20 minutes.

본 발명에 의하면, 콘택홀 내에 장벽 금속막을 증착한 후에 SiH4 분위기에서 열공정을 실시하여 장벽 금속막 표면에 실리콘 이온을 도핑시킨다. 이에 따라, 본 발명은 후속 알루미늄 증착시 장벽 금속막 표면의 실리콘이 알루미늄 내로 확산되기 때문에 알루미늄막에 실리콘이 재석출되는 현상을 방지하며, 기판의 불순물 주입 영역으로 알루미늄이 확산되는 것을 방지한다.According to the present invention, after depositing the barrier metal film in the contact hole, a thermal process is performed in an SiH 4 atmosphere to dope silicon ions onto the barrier metal film surface. Accordingly, the present invention prevents re-precipitation of silicon in the aluminum film because silicon on the barrier metal film surface is diffused into aluminum during subsequent aluminum deposition, and prevents aluminum from diffusing into the impurity implantation region of the substrate.

이하, 첨부한 도면을 참조하여 본 발명의 바람직한 실시예에 대해 상세하게 설명하고자 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 1 내지 도 5는 본 발명의 일 실시예에 따른 반도체 장치의 콘택 전극 형성방법을 설명하기 위한 공정 순서도이다.1 to 5 are flowcharts illustrating a method of forming a contact electrode of a semiconductor device according to an embodiment of the present invention.

본 발명은 우선, 일련의 제조 공정으로 반도체 소자를 형성하는데, 예를 들어 실리콘 기판(10)의 활성 영역에 게이트 산화막(14)을 내재하여 게이트 전극(16)을 형성하고, 게이트 전극(16) 측벽에 절연막으로 이루어진 스페이서(18)를 형성하고, 스페이서(16)의 하부 근방, 즉 게이트 전극(16) 에지와 필드 산화막(12) 사이의 활성 영역에 활성 영역과 다른 도전형 불순물이 주입된 소스/드레인 영역(20)을 가지는 트랜지스터를 형성한다. 이후 도 1에 나타난 바와 같이 트랜지스터의 상부에 형성될 배선을 전기적을 절연하고자 기판(10) 전면에 층간 절연막(22)을 형성한다. 층간 절연막(22)은 USG(Undoped Silicate Glass) 또는 BPSG(BoroPhospho Silicate Glass) 중에서 선택한 막질을 사용한다.The present invention first forms a semiconductor device in a series of manufacturing processes. For example, the gate electrode 16 is formed by embedding the gate oxide film 14 in the active region of the silicon substrate 10, and the gate electrode 16 A spacer 18 formed of an insulating film is formed on the sidewall, and a source in which an active region and other conductivity type impurities are injected into the active region near the lower portion of the spacer 16, that is, between the edge of the gate electrode 16 and the field oxide film 12. A transistor having the / drain region 20 is formed. Subsequently, as shown in FIG. 1, an interlayer insulating layer 22 is formed on the entire surface of the substrate 10 to electrically insulate the wiring to be formed on the transistor. The interlayer insulating film 22 uses a film quality selected from USG (Undoped Silicate Glass) or BPSG (BoroPhospho Silicate Glass).

그 다음 도 2에 나타난 바와 같이 사진 및 식각 공정으로 층간 절연막(22)을 선택 식각하여 층간 절연막(22) 내에 소스/드레인 영역(20)의 상부면이 개방되는 콘택홀(24)을 형성한다.Next, as shown in FIG. 2, the interlayer insulating layer 22 is selectively etched by a photo and etching process to form a contact hole 24 in which the top surface of the source / drain region 20 is opened in the interlayer insulating layer 22.

이어서 도 3에 나타난 바와 같이 콘택홀(24)이 형성된 층간 절연막(22) 전 면에 장벽 금속막(26)으로서 Ti을 300Å, 그 위에 TiN을 1000Å으로 적층한다. 이어서 웨이퍼에 급속 열공정(Rapid Thermal Annealing: 이하 RTA라 함)을 실시하여 상기 장벽 금속막(26) 표면에 실리콘 이온을 주입한다. 이때, 열공정은 5～15sccm의 SiH4 가스량, 450～650℃의 반응 온도, 10～30초의 반응 시간으로 실시한다. 한편, 상기 열공정은 반응로 열공정으로도 실시할 수 있는데, 이때 공정은 SiH4 + N2 가스, 430～500℃의 반응 온도, 10～20분의 반응 시간으로 실시한다.3, Ti is deposited as a barrier metal film 26 on the front surface of the interlayer insulating film 22 having the contact holes 24 formed thereon, and TiN is deposited thereon at 1000 ms. Subsequently, a rapid thermal process (hereinafter referred to as RTA) is performed on the wafer to implant silicon ions into the surface of the barrier metal film 26. At this time, the thermal step is carried out with a gas content of SiH 4 of 5 to 15 sccm, a reaction temperature of 450 to 650 ° C, and a reaction time of 10 to 30 seconds. On the other hand, the thermal process can also be carried out in the reaction furnace thermal process, wherein the process is carried out with a SiH 4 + N 2 gas, a reaction temperature of 430 ~ 500 ℃, reaction time of 10 to 20 minutes.

그 다음 도 4에 나타난 바와 같이 실리콘 이온이 주입된 장벽 금속막(26) 전면에 알루미늄(28)을 증착한다. 이때, 알루미늄은 실리콘 이온이 1% 미만으로 함 유된 막질 보다는 실리콘이 전혀 함유되지 않은 순수 알루미늄을 사용하는 것이 바람직하다. 그 이유는 후속 열공정시 실리콘이 알루미늄에서 석출되는 것을 감소시키기 위해서이다.Next, as shown in FIG. 4, aluminum 28 is deposited on the entire surface of the barrier metal film 26 implanted with silicon ions. In this case, it is preferable to use pure aluminum containing no silicon at all, rather than a film containing silicon ions less than 1%. The reason is to reduce the precipitation of silicon in aluminum during subsequent thermal processes.

이어서 도 5에 나타난 바와 같이 사진 및 식각 공정으로 증착된 알루미늄막(28)과 장벽 금속막(26)을 선택 식각한다. 이로 인해 상기 선택 식각된 알루미늄 막(28‘)과 장벽 금속막(26’)으로 이루어진 콘택 전극(29)이 상기 층간 절연막(22)의 콘택홀을 통해서 소스/드레인 영역(20)과 연결된다.Subsequently, as shown in FIG. 5, the aluminum film 28 and the barrier metal film 26 deposited by photo and etching processes are selectively etched. As a result, the contact electrode 29 including the selectively etched aluminum film 28 ′ and the barrier metal film 26 ′ is connected to the source / drain region 20 through the contact hole of the interlayer insulating layer 22.

상기와 같은 제조 공정에 따르면, 본 발명은 장벽 금속막 표면에 실리콘 이온을 주입하고 알루미늄을 증착하므로서 기판과 콘택 전극의 접합 스파이킹을 미연에 방지할 수 있어 반도체 소자의 접합 특성을 향상시킬 수 있는 효과가 있다.According to the manufacturing process as described above, the present invention can prevent the joint spiking of the substrate and the contact electrode in advance by injecting silicon ions and depositing aluminum on the barrier metal film surface can improve the bonding characteristics of the semiconductor device It works.

도 1 내지 도 5는 본 발명의 일 실시예에 따른 반도체 장치의 콘택 전극 형성방법을 설명하기 위한 공정 순서도이다.1 to 5 are flowcharts illustrating a method of forming a contact electrode of a semiconductor device according to an embodiment of the present invention.

*도면의 주요 부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *

10 : 실리콘 기판10: silicon substrate

12 : 필드 산화막12: field oxide film

14 : 게이트 산화막14: gate oxide film

16 : 게이트 전극16: gate electrode

18 : 스페이서18: spacer

20 : 소스/드레인 영역20: source / drain area

22 : 층간 절연막22: interlayer insulation film

26 : 콘택홀26: contact hole

28 : 장벽 금속막28: barrier metal film

30 : 금속층30: metal layer

29 : 콘택 전극29: contact electrode

Claims (5)

반도체 기판의 활성 영역 위에 형성된 반도체 소자와 상부의 금속 배선을 상호 연결하기 위한 콘택 전극을 형성함에 있어서,In forming a contact electrode for interconnecting a semiconductor element formed over an active region of a semiconductor substrate and an upper metal wiring, 상기 기판 전면에 반도체 소자를 상부 금속 배선과 전기적으로 절연하기 위한 층간 절연막을 형성하는 단계;Forming an interlayer insulating film on the entire surface of the substrate to electrically insulate the semiconductor device from the upper metal wiring; 상기 층간 절연막 내에 콘택 전극의 영역을 확보하기 위한 콘택홀을 형성하는 단계;Forming a contact hole in the interlayer insulating layer to secure a region of the contact electrode; 상기 콘택홀을 가지는 층간 절연막 내에 장벽 금속막을 형성하는 단계;Forming a barrier metal film in the interlayer insulating film having the contact hole; 열공정으로 장벽 금속막 표면에 실리콘 이온을 주입하는 단계; 및Implanting silicon ions into the barrier metal film surface by a thermal process; And 상기 콘택홀 내에 알루미늄을 매립하여 콘택 전극을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 장치의 콘택 전극 형성방법.And embedding aluminum in the contact hole to form a contact electrode. 제1항에 있어서, 상기 열공정은 급속 열공정을 실시하는 것을 특징으로 하는 반도체 장치의 콘택 전극 형성방법.The method of claim 1, wherein the thermal process is a rapid thermal process. 제2항에 있어서, 상기 열공정은 5～15sccm의 SiH4 가스량, 450～650℃의 반응 온도, 10～30초의 반응 시간으로 실시하는 것을 특징으로 하는 반도체 장치의 콘택 전극 형성방법.The method for forming a contact electrode of a semiconductor device according to claim 2, wherein the thermal step is performed at an amount of SiH 4 gas of 5 to 15 sccm, a reaction temperature of 450 to 650 ° C, and a reaction time of 10 to 30 seconds. 제1항에 있어서, 상기 열공정은 반응로 열공정을 실시하는 것을 특징으로 하는 반도체 장치의 콘택 전극 형성방법.The method for forming a contact electrode of a semiconductor device according to claim 1, wherein the thermal step performs a reactor thermal step. 제4항에 있어서, 상기 열공정은 SiH4 + N2 가스, 430～500℃의 반응 온도, 10～20분의 반응 시간으로 실시하는 것을 특징으로 하는 반도체 장치의 콘택 전극 형성방법.The method for forming a contact electrode of a semiconductor device according to claim 4, wherein the thermal step is performed with a SiH 4 + N 2 gas, a reaction temperature of 430 to 500 DEG C, and a reaction time of 10 to 20 minutes.
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KR100462763B1 (en) * 2002-06-18 2004-12-20 동부전자 주식회사 Method for forming aluminium metal line of semiconductor device

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JPH08124876A (en) * 1994-10-27 1996-05-17 Sony Corp Formation of high-melting-point metal film
JPH08274171A (en) * 1995-04-03 1996-10-18 Yamaha Corp Formation of titanium nitride layer and formation of wiring
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KR101319469B1 (en) * 2010-11-25 2013-10-17 미쓰비시덴키 가부시키가이샤 Semiconductor device
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