JP3444047B2 - Method for manufacturing semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device applied as a TFT such as a liquid crystal display device and a manufacturing method thereof.

[0002]

2. Description of the Related Art Thin Film Transist
In an or (hereinafter referred to as TFT) drive type liquid crystal display device, a TFT formed of an amorphous silicon layer or a TFT formed of a polycrystalline silicon layer is used, but the latter has a higher field effect mobility than the former. It is considered that the TFT will become the mainstream in the future because it can achieve higher performance.

A TFT having a polycrystalline silicon layer requires a high temperature process, that is, activation annealing at about 1000 ° C. and formation of a gate oxide film. Therefore, it is necessary to use a quartz glass substrate which is expensive and difficult to increase in size. By using this quartz glass, it is difficult to reduce the cost and upsize the liquid crystal panel.

Therefore, in recent years, from the viewpoint of cost reduction, etc., borosilicate glass, which is cheaper than a quartz glass substrate, is adopted, and an amorphous silicon layer is formed on this borosilicate glass to produce a pulsed excimer laser beam. Research and development have been conducted on techniques for crystallization into a polycrystalline silicon layer and improvement of crystallinity by activation annealing by irradiation.

[0005]

However, such a semiconductor device and its manufacturing method have the following problems. That is, it is necessary to work in a high vacuum in order to prevent the contamination of alkali metal ions, metal impurities, etc. due to the irradiation of the excimer laser light, and the productivity is very poor. Further, working in nitrogen results in a decrease in productivity for replacement and an increase in cost due to the use of expensive nitrogen. Further, when the amorphous silicon layer formed on the borosilicate glass is directly irradiated with the excimer laser light, the deterioration of the characteristics due to the contamination is likely to occur and the reliability of the product is deteriorated.

Further, when an amorphous silicon layer is formed, a low temperature film formation by plasma CVD (chemical vapor deposition) is suitable, and the amorphous silicon layer (α formed at this time is formed.
Since a large amount of hydrogen is contained in —Si: H), dehydrogenation annealing is necessary. On the other hand, when the excimer laser beam is directly radiated directly to the amorphous silicon layer, the reflectance in the ultraviolet region becomes large and the efficiency becomes poor. Therefore, it is possible to use a transparent silicon oxide film (up to 50 nm thick) as an antireflection film. Conceivable.

If the antireflection film such as the silicon oxide film is deposited on the entire surface of the amorphous silicon layer, the dehydrogenation by the dehydrogenation annealing described above becomes insufficient, and the hydrogen is bumped to a non-deposited state. The problem that the crystalline silicon layer is destroyed occurs. In addition, metal impurities such as Fe, Cr and Ni generated from the inner wall of the chamber of the apparatus when performing ion doping, and alkali metal ion contaminants such as sodium generated in a cleaning process such as resist stripping enter the amorphous silicon layer. This is a cause of characteristic deterioration.

In general, since metal impurities represented by Fe, Cr, Ni, and Au become lifetime killer in a silicon crystal, great efforts have been made to reduce them (for example, all metal impurities are excluded). Efforts have been made to reduce the level to 10 ¹⁰ cm ^-2 ), and similar efforts are required for amorphous silicon and polycrystalline silicon TFTs.

[0009]

SUMMARY OF THE INVENTION The present invention is a semiconductor device and a method of manufacturing the same which are made to solve the above problems. A semiconductor device according to the present invention includes a polycrystalline silicon layer formed as a gate region on an insulating substrate, a gate insulating portion formed between the polycrystalline silicon layer and a gate electrode, and a gate for the polycrystalline silicon layer. A protective insulating portion formed on the opposite side of the electrode, and the gate insulating portion is composed of a first interlayer stress buffer layer and a first metal contamination preventing layer in this order from the polycrystalline silicon layer side toward the gate electrode side. Then, the protective insulating portion is configured in the order of the second interlayer stress buffer layer and the second metal contamination preventing layer from the polycrystalline silicon layer side toward the side away from the gate electrode.

In such a semiconductor device, the first metal contamination preventing layer of the gate insulating portion and the second metal contamination preventing layer of the protective insulating portion cause metal contamination during or after the manufacturing process, that is, the gate region is an alkali metal ion. It becomes possible to prevent contamination by metal impurities and the like. Further, the first interlayer stress buffer layer of the gate insulating part and the second interlayer stress buffer layer of the protective insulating part alleviate the interlayer stress in a multi-layer structure and prevent the generation of leak current.

The semiconductor device manufacturing method of the present invention is
First layer metal contamination preventing layer made of a silicon nitride film forming a gate insulating portion, at least a silicon oxide film or an acid
A first interlayer stress buffer layer made of a silicon nitride film , an amorphous silicon layer for forming a polycrystalline silicon layer, at least a silicon oxide film or an oxynitride forming a protective insulating portion.
Second interlayer stress buffer layer made of silicon oxide film, silicon nitride
Performed continuously formed in this order of the second metal contamination preventing layer made of down film, then, leaving the protective insulating portion of the portion to be a gate region of the amorphous silicon layer, through the remaining protective insulating section laser This is a method of annealing to crystallize the amorphous silicon layer to form a polycrystalline silicon layer. Further, a second metal contamination preventing layer forming a protective insulating portion, a second interlayer stress buffer layer, an amorphous silicon layer forming a polycrystalline silicon layer, and a first interlayer stress buffer layer forming a gate insulating portion. , First
The metal contamination preventing layer is successively formed in this order, and then the gate insulating portion of the gate region of the amorphous silicon layer is left, and laser annealing is performed through the remaining gate insulating portion to perform the amorphous silicon layer. It is also a method of crystallizing the above to form a polycrystalline silicon layer.

In such a method of manufacturing a semiconductor device, it becomes possible to reduce the interlayer stress and reduce the mixing of dust between layers when a multilayer structure is formed by continuous film formation. The metal contamination prevention layer can prevent contaminants from entering the amorphous silicon layer even when laser annealing is performed in the atmosphere. Further, it is possible to prevent the problem of characteristic deterioration due to formation of the lower oxide film by laser annealing. Well
Also, during laser annealing, the gate area of the amorphous silicon layer is
Protective insulation or gate insulation is left in the area
The laser light is focused on the amorphous silicon layer.
The protection area is protected from direct irradiation.
Where the edge or gate insulation is not provided
It becomes possible to perform sufficient dehydrogenation.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of a semiconductor device and a method of manufacturing the same according to the present invention will be described below with reference to the drawings. FIG. 1 is a schematic cross-sectional view illustrating a first embodiment of a semiconductor device of the present invention, (a) is an inverted stagger type,
(B) shows a coplanar type (also referred to as a stagger type).

The inverted stagger type semiconductor device 1 shown in FIG. 1A includes a gate electrode 3 provided on an insulating substrate 2 and a gate insulating portion which is attached to the entire surface of the insulating substrate 2 so as to cover the gate electrode 3. 4, a polycrystalline silicon layer 5 for forming the gate region G, and a protective insulating portion 6 formed at least on the gate region G.

In particular, in the semiconductor device 1 shown in FIG. 1A, the gate insulating part 4 is composed of the first interlayer stress buffer layer 41 and the first metal contamination preventing layer 42, and the protective insulating part 6 is the second. It is characterized in that it is composed of the interlayer stress buffer layer 61 and the second metal contamination preventing layer 62.

In the coplanar type semiconductor device 1 shown in FIG. 1B, a protective insulating portion 6 formed on an insulating substrate 2, a polycrystalline silicon layer 5 for forming a gate region G, A gate insulating portion 4 formed at least on the gate region G, and a gate electrode 3 provided on the gate insulating portion 4.
It is configured to include and.

Also in the semiconductor device 1 shown in FIG. 1B, the gate insulating portion 4 is composed of the first interlayer stress buffer layer 41 and the first metal contamination preventing layer 42, and the protective insulating portion 6 is the second interlayer insulating layer. It is characterized in that it is composed of the stress buffer layer 61 and the second metal contamination preventing layer 62.

In any of the semiconductor devices 1, the first interlayer stress buffer layer 41 and the second interlayer stress buffer layer 61 not only serve to buffer the stress between the layers but also serve to electrically insulate them, thereby preventing the first metal contamination. The layer 42 and the second metal contamination preventing layer 62 are made of alkali metal ions (Na ⁺ , Li ⁺ , K ^+, etc.)
And metal impurities (transition metals such as Fe, Ni, Cu, Au)
It also plays the role of electrical insulation as well as preventing pollution.

In each of the semiconductor devices 1 of the first embodiment, LDDs (Lightly Doped) are formed on both inner sides of the gate electrode 3.
The structure is such that the Drain area 7 enters. LDD is an abbreviation for Lightly Doped Drain, M
N in the n ⁺ or p ⁺ source and drain regions of the OS structure
^The -or p ^- region is formed in a self-aligned manner, and particularly, the maximum electric field in the drain direction of the drain coupling is weakened. Usually, low-concentration phosphorus is used for the n ⁻ region, low-concentration boron is used for the p ⁻ region, high-concentration phosphorus or arsenic is used for the n ⁺ region, and high-concentration boron is used for the p ⁺ region. With this LDD structure, hot carrier injection from the drain region to the gate oxide film and the substrate can be reduced, V _T and G _m of the transistor can be stabilized, and overall characteristics can be improved. Further, in the case of a TFT for a liquid crystal display device, it is possible to reduce the leak current at high temperature and improve the image quality.

In such a semiconductor device 1, for example, in the inverted stagger type shown in FIG. 1A, the first electrode is formed on the entire surface of the insulating substrate 2 so as to cover the gate electrode 3 on the insulating substrate 2. The 1-metal contamination prevention layer 42 is capable of blocking alkali metal ion contaminants such as sodium that try to enter the gate region G from the insulating substrate 2 side.

Further, the second metal contamination preventing layer 62 and the second interlayer stress buffer layer 61 on the gate region G serve as a protective film, which is generated when the polycrystalline silicon layer 5 is crystallized by laser light irradiation which will be described later. The structure is such that contaminants such as alkali metal ions and metal impurities can be prevented from entering the gate region G.

In order to increase the gate withstand voltage,
The thickness of the gate insulating portion 4 may be thicker than the thickness of the protective insulating portion 6. That is, in the manufacturing method described later, since the excimer laser light is emitted through the protective insulating portion 6, the thickness of the protective insulating portion 6 is limited from the viewpoint of optical energy loss, but the thickness of the gate insulating portion 4 is limited. There is no such limitation, and there is no problem in increasing the thickness.

In the coplanar type shown in FIG. 1B, the second metal contamination preventing layer 62 formed on the insulating substrate 2 is also used.
Thus, it is possible to block contaminants of alkali metal ions, such as sodium, which try to enter the gate region G from the insulating substrate 2 side. Further, the first metal contamination preventing layer 42 and the first interlayer stress buffer layer 41 formed on the gate region G cause metal impurities and alkalis generated when the polycrystalline silicon layer 5 is crystallized by laser light irradiation described later. Contaminants such as metal ions are in the gate area G
It is designed to prevent you from getting inside.

Even in the case of the coplanar type, the thickness of the gate insulating portion 4 may be larger than that of the protective insulating portion 6. In the case of the coplanar type, in the manufacturing method described later, since the excimer laser light irradiation is performed from the insulating substrate 2 side, it is necessary to limit the thickness of the protective insulating portion 6 to a thickness in consideration of energy loss. The portion 4 does not have such a limitation and can be made thick to increase the gate breakdown voltage.

In any of the semiconductor devices 1, the stress between the polycrystalline silicon layer 5 and the first metal contamination preventing layer 42 is relaxed by the first interlayer stress buffer layer 41, and the second interlayer stress buffer layer 61 is used. The structure is such that the stress between the polycrystalline silicon layer 5 and the second metal contamination prevention layer 62 is relaxed.
As a result, it is possible to reduce the occurrence of leak current due to the interlayer stress, and it is possible to suppress the characteristic deterioration of the semiconductor device 1.

Next, a method of manufacturing the semiconductor device of the present invention will be described by showing concrete materials. 2 to 5 are schematic cross-sectional views for sequentially explaining the method for manufacturing a semiconductor device. In the following description, a method for manufacturing a semiconductor device mainly composed of an inverted stagger type N channel MOS type polysilicon TFT will be described as an example.

First, as shown in FIG. 2A, molybdenum / tantalum (Mo / Ta) having a thickness of, for example, about 300 nm is formed on an insulating substrate 2 made of translucent borosilicate glass by sputtering, Then, photolithography is performed to form the gate electrode 3. The reason why Mo / Ta is used here is to reduce resistance and improve heat resistance. In order to relieve the stress concentration in the thin film and improve the withstand voltage, the side edge 3a of the gate electrode 3 should be provided with a taper (20 to 30 ° C. with respect to the vertical direction) as shown by the broken line in the figure to have a trapezoidal cross section. Is good.

Next, as shown in FIG. 2B, a first metal contamination preventing layer 42, a first interlayer stress buffer layer 41, are formed on the entire surface of the insulating substrate 2 while covering the gate electrode 3 on the insulating substrate 2. The amorphous silicon layer 5 ', the second interlayer stress buffer layer 61, and the second metal contamination preventing layer 62 are successively formed in this order.

For example, as the first metal contamination preventing layer 42 and the second metal contamination preventing layer 62, a silicon nitride film (Si
N _x ), a silicon oxide film (SiO ₂ ) is used as the first interlayer stress buffer layer 41 and the second interlayer stress buffer layer 61. Each film is continuously grown by plasma CVD at a substrate temperature of about 300 ° C. and a thickness of about 30 to 50 nm.

That is, first, a silicon nitride film (SiN _x ) is used as the first metal contamination preventing layer 42 with SiH ₄ , NH ₃ ,
N ₂ is grown as a reaction gas, and then a silicon oxide film (SiO ₂ ) is used as a first interlayer stress buffer layer 41.
H ₄ and O ₂ are grown using a reaction gas, and then the amorphous silicon layer 5 ′ is grown using SiH ₄ as a reaction gas. Then, as a second interlayer stress buffer layer 61, a silicon oxide film (S
iO ₂ ) with SiH ₄ and O ₂ as reaction gases,
Finally, a silicon nitride film (SiN _x ) is grown as the second metal contamination prevention layer 62 using SiH ₄ , NH ₃ , and N ₂ as reaction gases.

Each of these films is continuously grown by switching the reaction gas in the same plasma CVD apparatus chamber. In continuous growth, each film can be continuously formed without opening the chamber to atmospheric pressure, so that contaminants can be prevented from mixing between each film and the stress between layers during film formation can be reduced as much as possible. It becomes possible.

The first interlayer stress buffer layer 41 and the second interlayer stress buffer layer 41
At least one of the interlayer stress buffer layers 61 is made of silicon oxynitride.
Membrane (SiO_xN_y) And a silicon oxide film (SiO₂)And
You may comprise from. That is, the first interlayer stress buffer layer 41
Silicon oxynitride film (SiO _xN_y) And silicon oxide film
(SiO₂) And are used on the gate electrode 3
The silicon nitride film (S
iN_x), And then nitric acid forming the first interlayer stress buffer layer 41
Silicon film (SiO_xN_y), Then silicon oxide film
(SiO₂) Is formed.

The second interlayer stress buffer layer 61 has a silicon oxynitride film (SiO _x N _y ) and a silicon oxide film (Si).
When O ₂ ) is used, a silicon oxide film (S) forming the second interlayer stress buffer layer 61 is formed on the amorphous silicon layer 5 ′.
iO ₂ ), then a silicon oxynitride film (SiO _x N _y ), and then a silicon nitride film (SiN _x ) forming the second metal contamination preventing layer 62.

Even when such a structure is formed, continuous growth can be easily performed by continuously switching the reaction gas introduced into the chamber of the plasma CVD apparatus. This can further alleviate the interlayer stress.

Further, the thickness of the protective insulating portion 6 is limited in terms of energy loss during irradiation of excimer laser light, which will be described later. Since the gate insulating portion 4 is not subject to such a limitation, it may be formed thick to improve the gate breakdown voltage.

Further, tantalum oxide is used as the gate insulating portion 4.
When a structure including a film is used, the structure shown in FIGS. 3 (a) and 3 (b) is used.
A continuous film having such a structure is formed. That is, FIG. 3 (a)
In the structure shown in, molybdenum / tantalum (Mo / Ta)
Metal contamination prevention layer covering the gate electrode 3 made of
42 constituting the silicon nitride film (SiN_x) About 100
nm thick, and a tantalum oxide film 42 '(Ta₂
O_Five) Is formed to a thickness of about 100 nm, and the first interlayer stress
Silicon oxide film (SiO 2) that constitutes the buffer layer 41 ₂) About
It is formed to a thickness of 50 nm.

Further, an amorphous silicon layer 5'is formed to a thickness of about 50 nm on the first interlayer stress buffer layer 41, and a silicon oxide film (Si) constituting the second interlayer stress buffer layer 61 is formed thereon.
O ₂ ) is formed to a thickness of about 50 nm, and a silicon nitride film (SiN _x ) forming the second metal contamination prevention layer 62 is formed thereon to about 1 nm.
It is formed to a thickness of 00 nm. Each film is continuously formed by plasma CVD. At this time, the silicon nitride film (SiN _x ) is Si
N ₄ , NH ₃ , and N ₂ are used as reaction gases, and Ta ₂ O ₅ is Ta.
(OC ₂ H ₅ ) ₅ and O ₂ are used as reaction gases, and SiO ₂ is S
iH ₄ and O ₂ are used as a reaction gas, and the amorphous silicon film 5 ′ uses SiH ₄ as a reaction gas.

In the structure shown in FIG. 3B, a silicon nitride film (SiN _x ) forming the first metal contamination preventing layer 42 is formed on the insulating substrate 2 to a thickness of about 200 nm, and molybdenum / tantalum (Mo / Mo / A gate electrode 3 made of Ta) is formed by sputtering (thickness: 300 nm), and the gate electrode 3 is dry-etched. After that, Mo / Ta
Oxidation of citric acid (citric acid 0.5-1.0%, 100 (V)
1 hour) to carry out tantalum oxide film 42 ′ (Ta ₂ O ₅ ).
To a thickness of about 100 nm.

Then, in a state of covering the tantalum oxide film 42 ', a silicon oxide film (SiO ₂ ) constituting the first interlayer stress buffer layer 41 is formed to a thickness of about 50 nm, and an amorphous silicon layer 5'is formed thereon. The thickness is 50 nm, and a silicon oxide film (SiO ₂ ) forming the second interlayer stress buffer layer 61 is formed on the thin film with a thickness of about 50
nm thick, and a silicon nitride film (SiN _x ) forming the second metal contamination prevention layer 62 is continuously formed thereon by plasma CVD to a thickness of about 50 nm. Plasma CVD
The reaction gas of each film formed by is similar to the above example.

The tantalum oxide film 4 is used as the gate oxide film 4.
By using the silicon oxide film which is the 2 ′ and first interlayer stress buffer layer 41, miniaturization and thinning can be promoted for improving the characteristics of the MOS transistor, and the leakage current due to direct tunneling becomes dominant. However, the gate insulating film thickness (4 nm) can be reached.
In addition, since the silicon oxide film-equivalent film thickness is reduced while keeping the gate insulating film thickness of 4 nm or more, Ta having a high relative dielectric constant is used.
It is also conceivable to use a ₂ O ₅ film.

Next, as shown in FIG. 3C, a resist R1 for an ion doping stopper is formed and LDD is performed.
Ion doping of low concentration phosphorus (P ⁻ ) for the region 7 (see FIG. 1A) is performed. In performing this ion doping, photolithography is performed to leave the resist R1 slightly narrower than the width of the gate electrode 3, and the second metal contamination preventing layer 62 and the second interlayer stress buffer layer 61 are etched so as to leave this width. Keep it. The former is dry etching using CF ₄ or the like, and the latter is wet etching with HF.

In the photolithography of the resist R1 at this time, overexposure is performed from the back surface side of the insulating substrate 2 using the gate electrode 3 as a mask in a state where the resist R1 is deposited on the entire surface to a thickness of about 300 nm. By removing the exposed portion of the resist R1, the resist R1 having a width slightly smaller than the width of the gate electrode 3 can be left. Then, using the resist R1, the second metal contamination preventing layer 62, and the second interlayer stress buffer layer 61 having this width as a mask, for example, 1
Doping with phosphorus (P) ions of about 0 ¹² to 10 ¹³ cm ^{-2 is performed} .

Next, as shown in FIG. 4A, a resist R2 is formed in a state of covering the resist R1, the second metal contamination preventing layer 62 and the second interlayer stress buffer layer 61, and using this as a mask, a high concentration is formed. Ion doping of phosphorus (P ⁺ ) is performed to form a source region and a drain region.

To form the resist R2, just exposure is performed from the back surface side of the insulating substrate 2 using the gate electrode 3 as a mask while the resist R2 is applied to the entire surface to a thickness of about 300 nm. Then, phosphorus (P) ions of 10 ¹⁴ to 10 ¹⁵ cm ⁻² are doped using the resist R2 as a mask. As a result, the portions of the amorphous silicon layer 5 ′ doped with the high concentration phosphorus (P ⁺ ) ions become the source region and the drain region.

In this doping, the resist R
1 and the resist R2, the portion of L that is the difference between the
^- ) Since it remains as an ion doping region, the size of this L determines the size of the LDD region 7 shown in FIG.

After the high-concentration phosphorus (P ⁺ ) ion doping is completed, the resists R1 and R2 are removed. For stripping, for example, a solution consisting of H ₂ SO ₄ : H ₂ O ₂ = 5: 1 is used to sufficiently remove and wash the resist so that no resist remains.

Next, the amorphous silicon layer 5'is irradiated with laser light as shown in FIG. 4B through the exposed protective insulating portion 6 to crystallize the polycrystalline silicon layer 5. . The laser light is, for example, XeCl and has a wavelength of 308 nm.
Excimer laser light of about 250-300 mJ /
Crystallization is performed with a dose of cm ² .

In the case of the present embodiment, this laser light irradiation is performed, for example, in clean air at room temperature and normal pressure. That is, since the protective insulating portion 6 is adhered at least above the portion which becomes the gate region G, the contaminants become the gate region G even when the treatment is performed in air without direct irradiation of the laser beam. It doesn't get into the part. Further, the deterioration of the characteristics can be prevented because the lower oxide film in the gate region G is not formed by the laser annealing. Further, the protection insulating portion 6 serves as an antireflection film, and the laser light is irradiated with low loss, so that the gate region G can be efficiently crystallized.

As the irradiation method, first, irradiation is performed with an energy lower than the melting energy to expel hydrogen in the amorphous silicon layer 5 ', and then irradiation is performed with an energy higher than the melting energy for melting. Let it solidify.
When the hydrogen is expelled, the protective insulating portion 6 is not provided except for the portion to be the gate region G, so that sufficient dehydrogenation can be performed from here. further,
By the above irradiation method, dehydrogenation, crystallization of the polycrystalline silicon layer 5, and activation of phosphorus (P) ions including the source, drain, and LDD regions can be performed at the same time, which also contributes to improvement in productivity. become.

Next, as shown in FIG. 4C, PSG8 (Phospho-) is formed on the crystallized polycrystalline silicon layer 5.
Abbreviation for Silicate Glass, which is a silicon oxide film containing phosphorus), and a silicon nitride film 9 is formed on the silicon oxide film by atmospheric pressure CVD.
Apply by law. For example, PSG8 is SiH ₄ ,
It is grown to a thickness of about 300 nm using a reaction gas composed of PH ₃ and O ₂ . The phosphorus concentration in this PSG8 is several% by weight. The silicon nitride film 9 is made of Si
It is grown to a thickness of about 200 nm using H ₄ , NH ₃ and N ₂ as reaction gases.

Then, the PSG 8 and the silicon nitride film 9
The hydrogenation annealing treatment is performed in the state of being deposited. For the hydrogenation annealing treatment, for example, heat treatment at 400 ° C. for 3 to 4 hours is performed in the forming gas. Many silicon dangling bonds exist at the grain boundaries of the polycrystalline silicon layer 5, and they act as a carrier generation / recombination center to generate a leak current. By this hydrogenation annealing treatment, the silicon dangling bonds can be cut and the generation of leak current can be suppressed.

In the hydrogenation annealing process with the PSG 8 and the silicon nitride film 9 deposited, hydrogen is allowed to enter the polycrystalline silicon layer 5 by utilizing the hygroscopicity of PSG 8, and a silicon dangling bond is formed by heat treatment. To cut. The reason why the silicon nitride film 9 is deposited on the PSG 8 is to confine hydrogen in the silicon nitride film 9 and enhance the hydrogen annealing effect. That is, since the silicon nitride film 9 is impermeable to hydrogen, it can be used as a cap film.

Further, the hydrogenation annealing treatment is carried out by the above-mentioned PSG.
8 and the silicon nitride film 9 are deposited, and instead of depositing the PSG 8 and the silicon nitride film 9, the laser light irradiation shown in FIG. The heat treatment may be performed with the silicon nitride film 9 shown in FIG. Also in this case, the point is to use the silicon nitride film 9 as a cap film.

Next, after the hydrogenation annealing treatment is completed, the source electrode S and the drain electrode D are formed as shown in FIG. 5B. In order to form the source electrode S and the drain electrode D, a window is opened in the silicon nitride film 9 and the PSG 8 corresponding to the respective positions, and aluminum (Al) containing Si (1%) is sputtered there to about 600 nm. Thickness of 4 and then 4
Aluminum sintering is performed at 00 ° C. for about 1 hour.

Incidentally, FIG. 5C shows a case where the above hydrogenation annealing treatment is performed with the silicon nitride film 9 deposited on the polycrystalline silicon layer 5 as shown in FIG. 5A. The state where the source electrode S and the drain electrode D are formed is shown.

By the above processing, the semiconductor device 1 as shown in FIG. 1A is completed. Note that FIG. 6 is a schematic cross-sectional view showing the semiconductor device 1 in which the LDD region 7 is formed outside the gate electrode 3. To manufacture such a semiconductor device 1, when forming the resist R1 shown in FIG.
If the exposure from the back surface of the insulating substrate 2 is just performed with respect to the width of the gate electrode 3, it can be easily manufactured.

Next, a manufacturing method according to the second embodiment of the present invention will be described with reference to the schematic sectional views of FIGS. The semiconductor device according to the second embodiment is a coplanar type N-channel MOS type polysilicon TFT.

In general, in both the inverted stagger type and the coplanar type, when the LDD region 7 (see FIG. 1) is in the gate region G, the gate channel length is shortened and the current characteristics are improved, while the gate- The breakdown voltage between the drains becomes low and the leak current increases slightly. In addition, the LDD region 7
Is provided outside the gate region G, the breakdown voltage between the gate and the drain is improved, the leak current is reduced, and the drain current is turned ON / OF.
The F ratio is increased and the switching characteristics and the contrast are improved.

When manufacturing this semiconductor device, first, as shown in FIG. 7A, a second metal contamination preventing layer 62 (eg, a metal contamination preventing layer 62) is formed on an insulating substrate 2 made of translucent borosilicate glass. Silicon nitride film), second interlayer stress buffer layer 61 (for example, silicon oxide film), amorphous silicon layer 5 ', first
Interlayer stress buffer layer 41 (eg, silicon oxide film), first
The metal contamination prevention layer 42 (for example, a silicon nitride film) is successively deposited by plasma CVD.

Further, as shown in FIG. 7A, when the tantalum oxide film 42 ′ (Ta ₂ O ₅ ) is used, the second metal contamination preventing layer 62 (for example, silicon nitride) is formed on the insulating substrate 2. Film), the second interlayer stress buffer layer 61 (for example, a silicon oxide film), the amorphous silicon layer 5 ′ (later polycrystalline silicon layer 5), the first interlayer stress buffer layer 41 (for example, a silicon oxide film), tantalum oxide film _{42 '(Ta 2 O 5)} , a continuous film formation by plasma CVD in the order of the first metal contamination prevention layer 42.

Then, as shown in FIG. 8A, the first interlayer stress buffer layer 41 and the first metal contamination preventing layer 42 are etched into a predetermined shape by mask exposure using the resist R1 to form the gate insulating portion 4. To form. Then 10 ¹²
LDD is formed by ion doping low-concentration phosphorus (P ⁻ ) of about 10 ¹³ cm ⁻² .

Next, as shown in FIG. 8B, the resist R2 is brought into a state of covering the resist R1 by mask exposure.
And a high concentration phosphorus (P ⁺ ) ion doping of about 10 ¹⁴ to 10 ¹⁵ cm ⁻² is performed to form source and drain regions. After that, the resists R1 and R2 are removed.

Then, as shown in FIG. 8C, laser light is irradiated to dehydrogenate and crystallize the amorphous silicon layer 5 ′ to form a polycrystalline silicon layer 5. The laser light irradiation is, for example, made of XeCl and has a wavelength of 308 nm.
Excimer laser light of about 250-300 mJ /
Crystallization is performed with a dose of cm ² . The laser light can be emitted from either the front surface or the back surface of the insulating substrate 2.

At the time of this dehydrogenation, since the first metal contamination preventing layer 42 and the first interlayer stress buffer layer 41 are formed only in the portion of the gate region G, hydrogen is easily released from other portions. become able to. Further, since the first metal contamination preventing layer 42 and the first interlayer stress buffer layer 41 remain at least above the gate region G, they serve as a protective film, and pollutants remain even if laser light irradiation is performed in the air. It does not enter the gate region G. Further, the first metal contamination preventing layer 42 and the first interlayer stress buffer layer 41 above the gate region G serve as an antireflection film, and the laser light is efficiently irradiated to the portion serving as the gate region G.

Next, as shown in FIG. 9A, PSG8
After the silicon nitride film 9 (for example, 300 nm thick) and the silicon nitride film 9 (for example, 200 nm thick) are formed, hydrogenation annealing treatment is performed in a forming gas at 400 ° C. for about 3 to 4 hours to perform dangling bond in the polycrystalline silicon layer 5. To cut.

Then, as shown in FIG. 9B, the PSG
8 and a window corresponding to the source, gate and drain of the silicon nitride film 9 are opened to form a source electrode S, a gate electrode G and a drain electrode D. The PSG 8 window is opened by dry etching, and the silicon nitride film 9 window is opened by wet etching. Also, each electrode is, for example, 1%
Aluminum containing silicon is formed to a thickness of about 300 nm, and aluminum etching and aluminum sintering are performed.

As a result, the coplanar semiconductor device 1
Is completed. Further, the coplanar type semiconductor device 1 shown in FIG. 9C has a structure in which the LDD region 7 is embedded in the gate region G. In order to insert the LDD region 7 into the gate region G in this way, the LDD region 7 is obliquely implanted during the ion doping of low concentration phosphorus (P ⁻ ) shown in FIG. You just have to go in.

Even in the coplanar type semiconductor device 1 shown in FIGS. 9B and 9C, the first interlayer stress buffer layer 41 and the protective insulating portion 6 forming the gate insulating portion 4 are formed. At least one of the second interlayer stress buffer layers 61 may be formed in order of the silicon oxide film and the silicon oxynitride film in the direction away from the polycrystalline silicon layer 5. by this,
It is possible to further alleviate the interlayer stress.

Further, in any of the semiconductor devices 1 in the first and second embodiments, the LDD regions 7 are provided on both sides of the gate electrode 3 in a so-called double LDD structure, but only between the gate and the drain. LDD region 7
A so-called single LDD structure may be provided. Further, in each of the embodiments, the example of the semiconductor device 1 including the N-channel MOS type polysilicon TFT has been described.
The same applies to the semiconductor device 1 including the channel MOS type polysilicon TFT, if the conductivity type in ion doping is changed.

Further, in each of the embodiments of the present invention, an example in which an amorphous silicon film (a-Si: H) is converted into polycrystalline silicon by laser annealing by irradiation of excimer laser light is shown. Laser annealing by light irradiation of Ar laser or low temperature annealing (600 ° C.,
20-30 hours), RTA (Rapid Thermal Annea)
A method such as annealing treatment at 650 to 700 ° C. for 0.5 to 1.0 hour according to l) may be used.

[0071]

As described above, the semiconductor device and the method of manufacturing the same of the present invention have the following effects.
That is, a gate insulating portion including a first interlayer stress buffer layer and a first metal contamination preventing layer is provided above the gate region,
Since the protective insulating portion including the second interlayer stress buffer layer and the second metal contamination preventing layer is located thereunder, the gate region is contaminated with alkali metal ions, metal impurities, etc. even when the laser light is irradiated in the air. Therefore, it is possible to prevent the deterioration of characteristics and improve the productivity significantly.

Further, the gate insulating portion or the protective insulating portion serves as an anti-reflection film for laser light to efficiently crystallize the amorphous silicon layer serving as the gate region, thereby improving the characteristics of the semiconductor device and reducing capital investment. Can be achieved.

Further, since various thin films are continuously formed, contamination between layers can be eliminated, stress between layers can be reduced, and leak current can be reduced. Also,
Since dehydrogenation can be easily performed at the time of laser light irradiation, dehydrogenation, crystallization, and activation can be continuously performed, and productivity can be significantly improved.

[Brief description of drawings]

FIG. 1 is a schematic cross-sectional view illustrating a first embodiment of a semiconductor device of the present invention.

FIG. 2 is a schematic cross-sectional view (No. 1) for explaining the method for manufacturing a semiconductor device of the present invention.

FIG. 3 is a schematic sectional view (No. 2) for explaining the method for manufacturing a semiconductor device of the present invention.

FIG. 4 is a schematic cross-sectional view (3) explaining the method for manufacturing a semiconductor device of the present invention.

FIG. 5 is a schematic cross-sectional view (4) explaining the method for manufacturing a semiconductor device of the present invention.

FIG. 6 is a schematic cross-sectional view (5) explaining the method for manufacturing a semiconductor device of the present invention.

FIG. 7 is a schematic sectional view (No. 1) for explaining the manufacturing method of the second embodiment.

FIG. 8 is a schematic cross-sectional view (No. 2) for explaining the manufacturing method of the second embodiment.

FIG. 9 is a schematic cross-sectional view (3) illustrating the manufacturing method according to the second embodiment.

[Explanation of symbols]

1 Semiconductor Device 2 Insulating Substrate 3 Gate Electrode 4 Gate Insulating Part 5 Polycrystalline Silicon Layer 5 ′ Amorphous Silicon Layer 6 Protective Insulating Part 7 LDD Region 41 First Interlayer Stress Buffer Layer 42 First Metal Contamination Prevention Layer 61 Second Interlayer stress buffer layer 62 Second metal contamination prevention layer

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI H01L 29/78 627G G02F 1/136 500 (56) Reference JP-A-6-13610 (JP, A) JP-A-6-334183 (JP, A) JP-A-7-37999 (JP, A) JP-A-4-12330 (JP, A) JP-A-5-47791 (JP, A) JP-A-4-240734 (JP, A) Kaihei 6-163409 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 29/786

Claims (12)

(57) [Claims] 1. A polycrystalline silicon layer formed as a gate region on an insulating substrate, a gate insulating portion formed between the polycrystalline silicon layer and a gate electrode, and the polycrystalline silicon layer with respect to the polycrystalline silicon layer. A method of manufacturing a semiconductor device, comprising: a gate electrode and a protective insulating portion formed on the side opposite to the gate electrode, the first metal contamination preventing layer comprising a silicon nitride film forming the gate insulating portion, and at least silicon oxide. Membrane
Is a first interlayer stress buffer layer made of a silicon oxynitride film , an amorphous silicon layer for forming the polycrystalline silicon layer,
At least a silicon oxide film forming the protective insulating portion
Alternatively, a second interlayer stress buffer layer made of a silicon oxynitride film and a second metal contamination prevention layer made of a silicon nitride film are successively formed in that order, and then the portion of the amorphous silicon layer to be the gate region is formed. A method of manufacturing a semiconductor device, characterized in that the amorphous silicon layer is crystallized by leaving the protective insulating portion and laser annealing through the remaining protective insulating portion to form the polycrystalline silicon layer. . 2. When the first interlayer stress buffer layer is composed of a silicon oxide film and a silicon oxynitride film and the first metal contamination prevention layer is composed of a silicon nitride film, the first metal contamination prevention layer is formed. The silicon nitride film forming the layer, the silicon oxynitride film forming the first interlayer stress buffer layer, the silicon oxide film, the amorphous silicon layer, the second
The interlayer stress buffer layer and the second metal contamination prevention layer are successively formed in this order.
The method for manufacturing a semiconductor device according to claim 1 , wherein a film is formed . 3. When the second interlayer stress buffer layer is composed of a silicon oxide film and a silicon oxynitride film and the second metal contamination prevention layer is composed of a silicon nitride film, the first metal contamination prevention layer is provided. A layer, the first interlayer stress buffer layer, the amorphous silicon layer, a silicon oxide film forming the second interlayer stress buffer layer, a silicon oxynitride film, and a silicon nitride film forming the second metal contamination preventing layer. Continuous film formation in order
The method according to claim 1, wherein the cormorants. 4. The first interlayer stress buffer layer and the second interlayer stress buffer layer are composed of a silicon oxide film and a silicon oxynitride film, and the first metal contamination prevention layer and the second metal contamination prevention layer are silicon nitride. In the case of forming a film, the silicon nitride film forming the first metal contamination preventing layer, the silicon oxynitride film forming the first interlayer stress buffer layer, the silicon oxide film, the amorphous silicon layer ,
2. The continuous film formation is performed in the order of the silicon oxide film forming the second interlayer stress buffer layer, the silicon oxynitride film, and the silicon nitride film forming the second metal prevention layer. A method for manufacturing a semiconductor device as described above. 5. A polycrystalline silicon layer formed as a gate region on an insulating substrate, a gate insulating part formed between the polycrystalline silicon layer and a gate electrode, and the polycrystalline silicon layer with respect to the polycrystalline silicon layer. A method of manufacturing a semiconductor device, comprising: a protective insulating portion formed on a side opposite to a gate electrode, wherein a second metal contamination preventing layer made of a silicon nitride film forming the protective insulating portion, at least silicon oxide. Membrane or
A second interlayer stress buffer layer formed of a silicon oxynitride film , an amorphous silicon layer for forming the polycrystalline silicon layer, and at least a silicon oxide film forming the gate insulating portion are also formed.
Or a first interlayer stress buffer layer made of a silicon oxynitride film ,
A first metal contamination preventing layer made of a silicon nitride film is continuously formed in this order, and thereafter, the gate insulating portion of a portion of the amorphous silicon layer to be the gate region is left, and the remaining gate insulating portion is removed. A method of manufacturing a semiconductor device, characterized in that the amorphous silicon layer is crystallized by laser annealing via the above to form the polycrystalline silicon layer. 6. The first interlayer stress buffer layer is made of silicon oxide.
It is composed of a film and a silicon oxynitride film to prevent the contamination of the first metal.
In the case where the stop layer is composed of a silicon nitride film, the second metal contamination preventing layer, the second interlayer stress buffer layer, the
Amorphous silicon layer, constituting the first interlayer stress buffer layer
Silicon oxide film, silicon oxynitride film, contamination of the first metal
Successive film formation is performed in order of the silicon nitride film that constitutes the prevention layer
6. A method of manufacturing a semiconductor device according to claim 5, wherein
Law. 7. The second interlayer stress buffer layer is made of silicon oxide.
It consists of a film and a silicon oxynitride film to prevent the contamination of the second metal.
In the case where the stop layer is composed of a silicon nitride film, a silicon nitride film that constitutes the second metal contamination preventing layer, a second
Silicon oxynitride film and silicon oxide forming the interlayer stress buffer layer
Con film, the amorphous silicon layer, the first interlayer stress buffer
Layer, carrying out the successive deposition in the order of the first metal contamination prevention layer
6. The method of manufacturing a semiconductor device according to claim 5, wherein. 8. The first interlayer stress buffer layer and the second interlayer stress
The force buffer layer is composed of a silicon oxide film and a silicon oxynitride film.
And the first metal contamination prevention layer and the second metal contamination prevention layer
In the case where is formed of a silicon nitride film, the silicon nitride forming the second metal contamination preventing layer
A film, the nitrous oxide oxide constituting the second interlayer stress buffer layer
Con film, the silicon oxide film, the amorphous silicon layer,
The silicon oxide forming the first interlayer stress buffer layer
Film, the silicon oxynitride film, and the first metal contamination prevention layer
By performing successive deposition order of the silicon nitride film constituting
6. The method of manufacturing a semiconductor device according to claim 5, wherein. Wherein said first interlayer stress buffer layer and the second interlayer stress buffer layer comprises a silicon oxide film, the first metal contamination prevention layer and the second metal contamination prevention layer is configured to include a silicon nitride film And the laser annealing is an excimer laser made of XeCl.
The method for manufacturing a semiconductor device according to claim 1 , wherein light is used . Wherein said addition claim 1 laser annealing for amorphous silicon layer and performing in the air
Is a method of manufacturing a semiconductor device according to 5 . 11. The method according to claim 1 or 5, wherein the forming thicker than the thickness of the gate complementary color edge thickness the protection of the insulating portion. 12. The method of manufacturing a semiconductor device according to claim 11, wherein the amorphous silicon layer is irradiated with laser light from the protective insulating portion side to perform laser annealing.