CN114121939B - Integrated MOSFET device and preparation method - Google Patents
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- CN114121939B CN114121939B CN202111408815.XA CN202111408815A CN114121939B CN 114121939 B CN114121939 B CN 114121939B CN 202111408815 A CN202111408815 A CN 202111408815A CN 114121939 B CN114121939 B CN 114121939B
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- 238000002360 preparation method Methods 0.000 title abstract description 14
- 210000000746 body region Anatomy 0.000 claims abstract description 180
- 238000005468 ion implantation Methods 0.000 claims abstract description 42
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 42
- 229920005591 polysilicon Polymers 0.000 claims abstract description 30
- 238000000034 method Methods 0.000 claims abstract description 29
- 238000002347 injection Methods 0.000 claims abstract description 5
- 239000007924 injection Substances 0.000 claims abstract description 5
- 239000002184 metal Substances 0.000 claims description 90
- 238000002955 isolation Methods 0.000 claims description 66
- 229920002120 photoresistant polymer Polymers 0.000 claims description 34
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 17
- 229910052710 silicon Inorganic materials 0.000 claims description 17
- 239000010703 silicon Substances 0.000 claims description 17
- 238000004519 manufacturing process Methods 0.000 claims description 12
- 238000005530 etching Methods 0.000 claims description 10
- WYTGDNHDOZPMIW-RCBQFDQVSA-N alstonine Natural products C1=CC2=C3C=CC=CC3=NC2=C2N1C[C@H]1[C@H](C)OC=C(C(=O)OC)[C@H]1C2 WYTGDNHDOZPMIW-RCBQFDQVSA-N 0.000 claims description 5
- 238000002513 implantation Methods 0.000 claims description 5
- 238000005229 chemical vapour deposition Methods 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 abstract description 4
- 238000010586 diagram Methods 0.000 description 25
- 239000000758 substrate Substances 0.000 description 17
- 229910052581 Si3N4 Inorganic materials 0.000 description 7
- 238000001312 dry etching Methods 0.000 description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 7
- 238000001039 wet etching Methods 0.000 description 7
- 238000012986 modification Methods 0.000 description 5
- 230000004048 modification Effects 0.000 description 5
- 238000000206 photolithography Methods 0.000 description 4
- 238000001259 photo etching Methods 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 230000000149 penetrating effect Effects 0.000 description 2
- 230000035939 shock Effects 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000001883 metal evaporation Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0292—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using a specific configuration of the conducting means connecting the protective devices, e.g. ESD buses
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
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Abstract
The invention discloses an integrated MOSFET device and a preparation method thereof, relating to the field of semiconductor power devices. The purpose of voltage resistance of the device is achieved by using the ESD polysilicon layer as a mask to block the injection of the P-type body region at the periphery, and an adjustable resistance region is formed in the Rg region, so that the function of the device can be perfected. The method comprises the following steps: a non-doped polysilicon layer located above the drift layer of the first conductivity type, which forms a body region of the first conductivity type by ion implantation; the active region groove is positioned in the MOSFET region, a second layer of second conductive type body region is arranged on two sides of the active region groove, and a second layer of first conductive type source region is arranged on the upper layer of the second layer of second conductive type body region positioned on one side of the active region groove; an ESD region between the MOSFET region and the Rg region; a first layer of first conductivity type source regions located within a first layer of second conductivity type body regions of the ESD region; and the adjustable resistance region is positioned on the upper layer of the first layer second conduction type body region in the Rg region.
Description
Technical Field
The invention relates to the technical field of semiconductor power devices, in particular to an integrated MOSFET device and a preparation method thereof.
Background
For power device mosfet (Metal-Oxide-Semiconductor Field Effect Transistor, chinese) devices, in some application fields, in order to seek lower internal resistance, the density of device cells is increased by mainly reducing the width of each critical dimension, but the reduction of the critical dimension of the device is necessary to compress the thickness of a gate Oxide layer, so as to reduce the antistatic and impact resistance of the gate of the device.
Disclosure of Invention
The embodiment of the invention provides an integrated MOSFET device and a preparation method thereof, which can effectively enhance the antistatic and impact resistance capability of a grid electrode, achieve the purpose of voltage resistance of the device by using an ESD polycrystalline silicon layer as a mask plate to block the injection of a P-type body region at the periphery, and form an adjustable resistance region in an Rg region, so that the function of the device can be perfected.
An embodiment of the present invention provides an integrated MOSFET device, including:
a non-doped polysilicon layer located above the first conductive type drift layer and forming a first layer of a second conductive type body region by ion implantation;
the active region groove is positioned in the MOSFET region, a second layer of second conductive type body region is arranged on two sides of the active region groove, and a second layer of first conductive type source region is arranged on the upper layer of the second layer of second conductive type body region positioned on one side of the active region groove;
an ESD region located between the MOSFET region and Rg region;
a first layer of first conductivity type source regions located within a first layer of second conductivity type body regions of the ESD region;
and an adjustable resistance region located at an upper layer of the first layer second conductive type body region in the Rg region.
Preferably, the method further comprises the following steps: an N-type heavily doped polysilicon layer and a gate oxide layer;
the grid oxide layer is arranged in the active region groove and above the first conduction type drift layer;
the N-type heavily doped polycrystalline silicon layer is arranged in the active region groove, and the upper surface of the N-type heavily doped polycrystalline silicon layer in the active region groove and the upper surfaces of the grid oxide layers on the two sides of the top of the active region groove have the same height.
Preferably, the silicon nitride oxide layer and the first isolation oxide layer are further included;
the silicon oxynitride layer and the first isolation oxide layer are sequentially arranged above the grid oxide layer, and the upper surface of the first isolation oxide layer is contacted with the lower surface of the first layer of the second conductive type body region;
the silicon oxynitride layer, the first isolation oxide layer and the first second conductive type body region in the MOSFET region have the same width; the silicon oxynitride layer, the first isolation oxide layer and the first layer of second conductive type body region in the ESD region have the same width; the silicon oxynitride layer, the first isolation oxide layer and the first second conductive type body region in the Rg region have the same width;
and a gap exists between the first layer second conduction type body region positioned in the ESD region and the first layer second conduction type body region positioned in the MOSFET region and the first layer second conduction type body region positioned in the Rg region.
Preferably, a first layer second conductivity type body region is further included;
a projection in a vertical direction of the first layer of second conductivity type body regions located in the MOSFET region does not coincide with the second layer of second conductivity type body regions located in the MOSFET region;
contact holes are formed in the second layer of first conduction type source region on one side of the active region groove and the second layer of second conduction type body region between the active regions, and the contact holes are in contact with a metal layer arranged on the second isolation oxide layer to form a source region metal layer.
Preferably, a projection in a vertical direction of the first layer of second conductivity type body regions located within the ESD region does not coincide with the second layer of second conductivity type body regions located within the MOSFET region;
the projection of the first layer of second conductive type body region in the Rg region in the vertical direction is not overlapped with the second layer of second conductive type body region in the Rg region;
the two first-layer first-conductivity-type source regions are positioned in the first-layer first-conductivity-type body region and are not in contact with each other, and each first-layer first-conductivity-type source region is provided with a contact hole;
two contact holes are formed in the adjustable resistance area in the Rg area;
one contact hole in the ESD area close to the MOSFET area is contacted with a metal layer arranged on a second isolation oxide layer to form a gate area metal layer;
another contact hole in the ESD area close to the Rg area is in contact with a metal layer arranged on a second isolation oxide layer, and one contact hole in the ESD area close to the Rg area is in contact with the metal layer arranged on the second isolation oxide layer, so that an Rg area-ESD area connecting metal layer is formed;
and the other contact hole positioned in the Rg area is contacted with a metal layer arranged on the second isolation oxide layer to form gate polysilicon-Rg area connection metal layer.
The embodiment of the invention also provides a preparation method of the integrated MOSFET device, which comprises the following steps:
forming a first layer of second conductive type body region on the non-doped polycrystalline silicon layer above the first conductive type drift layer in an ion implantation mode; dividing the first conductivity type drift layer into a MOSFET region, an ESD region, and an Rg region;
forming a first layer of first conductive type source region on the first layer of second conductive type body region in the ESD region through ion implantation, and forming a second layer of first conductive type source region on the second layer of second conductive type body region on one side of the active region groove;
forming an adjustable resistance region on the first layer second conductive type body region of the Rg region by ion implantation;
forming contact holes in the second layer of second conductive type body region, the second layer of first conductive type source region, the first layer of first conductive type source region and the adjustable resistance region, and sequentially forming a source region metal layer, a gate polysilicon-Rg region connecting metal layer, an Rg region-ESD region connecting metal layer and a gate region metal layer through the contact holes.
Preferably, the forming an adjustable resistance region on the first layer second conductivity type body region of the Rg region by ion implantation specifically includes:
forming a third photoresist layer on the upper surfaces of the MOSFET region, the ESD region and the Rg region;
and covering two sides of the top of the first layer of second conductive type body region by using a third photoresist layer positioned on the upper surface of the Rg region, carrying out ion implantation on the first layer of second conductive type body region positioned in the Rg region, and forming an adjustable resistance region in the first layer of second conductive type body region.
Preferably, the third photoresist layer on the upper surface of the Rg region covers two sides of the top of the first second conductive type region, and further includes:
the third photoresist layer is partially covered on the top of the first layer second conduction type body region in the Rg area, wherein the shape of the third photoresist layer on the top of the first layer second conduction type body region at least comprises: at least three first rectangles which are consistent in shape and are not in contact with each other, wherein the length of the long side of each first rectangle is smaller than the distance between two contact holes on the adjustable resistance area; the two second rectangles with the same shape are arranged on the side edge between the two contact holes on the adjustable resistance area, and the side length of the long edge of each second rectangle is smaller than the distance between the two contact holes; a serpentine.
Preferably, before forming the first layer of second conductivity type body region from the undoped polysilicon layer above the drift layer of the first conductivity type, the method further includes:
forming an active region groove in the first conductive type drift layer by an etching method;
forming a grid oxide layer on the first conductive type drift layer and in the active region groove, and forming a polycrystalline silicon layer in the active region groove by chemical vapor deposition;
and sequentially forming a silicon oxynitride layer, a first isolation oxide layer and a non-doped polycrystalline silicon layer on the upper surfaces of the grid oxide layer and the polycrystalline silicon layer.
Before forming a first layer of first conductivity type source region on the first layer of second conductivity type body region in the ESD region by ion implantation, and forming a second layer of first conductivity type source region on the second layer of second conductivity type body region at one side of the active region trench, the method further includes:
removing the silicon oxynitride layer, the first isolation oxide layer and the first second conductive type body region which are positioned on two sides of the ESD region, two sides of the Rg region, two sides of the MOSFET region and above the first conductive type drift layer in an etching mode, wherein the ESD region is positioned between the Rg region and the MOSFET region; one side of the MOSFET region comprises the silicon oxynitride layer, the first isolation oxide layer and the first layer of second conductive type body region between the active region grooves and above two sides of the active region grooves;
forming a second layer of second conductivity type body region in the first conductivity type drift layer, wherein the projection of the first layer of second conductivity type body region in the vertical direction in the MOSFET region is not overlapped with the second layer of second conductivity type body region; the projection of the first layer of second-conductivity-type body region in the ESD area in the vertical direction is not overlapped with the second layer of second-conductivity-type body region; and the projection of the first layer of second conductive type body region in the Rg region in the vertical direction is not overlapped with the second layer of second conductive type body region.
Preferably, the forming of the first and second conductivity type body regions by the undoped polysilicon layer above the first conductivity type drift layer is a first ion implantation, and the forming of the second conductivity type body region in the first conductivity type drift layer is a second ion implantation; wherein the implantation dosage of the first ion implantation is larger than that of the second ion implantation.
The embodiment of the invention provides an integrated MOSFET device and a preparation method thereof, wherein the device comprises: a non-doped polysilicon layer located above the drift layer of the first conductivity type, which forms a body region of the first conductivity type by ion implantation; the active region groove is positioned in the MOSFET region, a second layer of second conductive type body region is arranged on two sides of the active region groove, and a second layer of first conductive type source region is arranged on the upper layer of the second layer of second conductive type body region positioned on one side of the active region groove; an ESD region between the MOSFET region and the Rg region; a first layer of first conductivity type source regions located within a first layer of second conductivity type body regions of the ESD region; and an adjustable resistance region located at an upper layer of the first layer second conductive type body region in the Rg region. The grid electrode and the source electrode of the MOSFET device are integrated into an ESD (electro-static discharge) area, so that electrostatic breakdown of grid oxide can be prevented; an Rg area is integrated on the grid end, so that the grid current can be reduced, and the shock resistance of the grid end of the device in application is improved; meanwhile, an adjustable resistance area is formed in the Rg area, so that the function of the device can be improved; furthermore, the polycrystalline silicon layer in the ESD area is used as a mask to prevent the injection of the first layer of second conductive type body area at the periphery, so that the purpose of resisting the voltage of the device is achieved, one layer of photoetching process can be reduced, and the production cost is reduced.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments or the prior art descriptions will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 is a schematic structural diagram of an integrated MOSFET device according to an embodiment of the present invention;
fig. 2 is a schematic view of a process for manufacturing an integrated MOSFET device according to an embodiment of the present invention;
fig. 3A is a schematic diagram of a first conductive type drift layer according to an embodiment of the present invention;
fig. 3B is a schematic diagram illustrating the preparation of an active region trench according to an embodiment of the present invention;
fig. 3C is a schematic diagram illustrating a sacrificial oxide layer according to an embodiment of the invention;
FIG. 3D is a schematic diagram of the sacrificial oxide layer with the active region removed according to an embodiment of the present invention;
fig. 3E is a schematic diagram illustrating a gate oxide layer formed on the drift layer of the first conductivity type and in the trench of the active region according to an embodiment of the present invention;
FIG. 3F is a schematic diagram of a polysilicon layer according to an embodiment of the present invention;
fig. 3G is a schematic diagram illustrating the preparation of a first layer of a second conductivity type body region according to an embodiment of the present invention;
fig. 3H is a schematic view of the second conductivity type body region of the second layer according to an embodiment of the present invention;
fig. 3I is a schematic diagram illustrating the preparation of a first conductive type source region according to an embodiment of the present invention;
FIG. 3J is a schematic diagram illustrating the fabrication of an adjustable resistor according to an embodiment of the present invention;
fig. 3K is a schematic view illustrating a second isolation oxide layer according to an embodiment of the invention;
FIG. 4A is a schematic diagram of a first third photoresist layer and an adjustable resistance layer according to an embodiment of the present invention;
FIG. 4B is a schematic diagram of a second third photoresist layer and an adjustable resistance layer according to an embodiment of the present invention;
FIG. 4C is a schematic diagram of a third photoresist layer and an adjustable resistance layer according to an embodiment of the present invention;
the transistor comprises a first conductive type substrate layer-101, a first conductive type drift layer-102, an active region groove-103, a sacrificial oxide layer-104, a gate oxide layer-105, an N-type heavily doped polysilicon layer-106, a silicon nitride layer-107, a first isolation oxide layer-108, an undoped polysilicon layer-109, a first photoresist layer-110, a second conductive type body region-111, a second photoresist layer-112, a first conductive type source region-113, a second conductive type source region-114, a third photoresist layer-115, an adjustable resistance region-116, a second isolation oxide layer-117, an active region contact hole-118, an Rg region contact hole-119, an ESD region contact hole-120, a source region metal layer Rg-121, a gate-Rg region connecting metal layer-122, an ESD region-ESD region connecting metal layer-123, a gate region metal layer-124 and a drain region metal layer-125.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Fig. 1 schematically shows a structure of an integrated MOSFET device according to an embodiment of the present invention, as shown in fig. 1, the MOSFET device mainly includes an active region trench 103, a first conductivity type drift layer 102, a first layer of second conductivity type body regions, a first layer of first conductivity type source regions 113, a second layer of first conductivity type source regions 114, and an adjustable resistance region.
Since the MOSFET device provided by the embodiment of the invention comprises the MOSFET region, the ESD region and the Rg region, in order to clearly describe the structure of the MOSFET device, the detailed structures of the three regions are respectively described.
As shown in fig. 1, in the MOSFET region, an active region trench 103 is disposed on the first conductivity type drift layer 102, wherein the active region trench 103 is located at one side of the first conductivity type drift layer 102, and a notch of the active region trench 103 is located on an upper surface of the first conductivity type drift layer 102, the active region trench 103 extends vertically downward from the upper surface of the first conductivity type drift layer 102, and a depth of the active region trench 103 is smaller than a thickness of the first conductivity type drift layer 102.
The MOSFET region includes a first layer second conductive type body region, a second layer second conductive type body region 111, and a second layer first conductive type source region 114. Specifically, a second layer of first conductivity type source regions 114 is disposed on a side of the active region trench 103 away from the ESD region, and an upper surface of the second layer of first conductivity type source regions 114 and an upper surface of the second layer of second conductivity type body regions 111 are located on an upper surface of the first conductivity type drift layer 102; the lower surfaces of the second layer of first conductive type source regions 114 and the second layer of second conductive type body regions 111 both extend into the first conductive type drift layer 102, and the lower surfaces of the second layer of first conductive type source regions 114 and the second layer of second conductive type body regions 111 have different heights.
Further, a first layer of second conductivity type body region is disposed above the first conductivity type drift layer 102, and a projection thereof in the vertical direction does not coincide with the second layer of second conductivity type body region 111. In the embodiment of the present invention, three regions are included from left to right above the first conductive type drift layer 102 in the MOSFET region, the first region includes the gate oxide layer 105, the second isolation oxide layer 117 and the metal layer on the first conductive type drift layer 102, and the metal layer penetrates through the second isolation oxide layer 117 through the active region contact hole 118, and the gate oxide layer 105 contacts with the second layer of the second conductive type body region 111 to form the source region metal layer 121; the second region comprises a gate oxide layer 105, a silicon nitride layer 107, a first isolation oxide layer 108, a first second conductivity type body region, a second isolation oxide layer 117 and two spaced apart metal layers on the first conductivity type drift layer 102, one metal layer being part of the source region metal layer 121 and the other metal layer being part of the gate region metal layer 124; the third region includes the gate oxide layer 105 on the first conductive-type drift layer 102, the second isolation oxide layer 117, and a metal layer, and the metal layer of the region contacts the first conductive-type source region 113 in the ESD region through the second isolation oxide layer 117 to form the gate region metal layer 124.
The ESD region includes a first layer of second conductivity type body region, a first layer of first conductivity type source region 113 and a second layer of second conductivity type body region 111, wherein the first layer of second conductivity type body region and the first layer of first conductivity type source region 113 are located above the first conductivity type drift layer 102, the first layer of first conductivity type source region 113 includes two blocks, both of which are disposed in the first layer of second conductivity type body region and do not contact, and the first layer of second conductivity type body region and the first layer of first conductivity type source region 113 have the same height; further, a gate oxide layer 105, a silicon nitride layer 107 and a first isolation oxide layer 108 are further included between the first layer of the second conductive type body region and the first conductive type drift layer 102.
Further, the second layer of second conductivity type body regions 111 is located within the first conductivity type drift layer 102, and a projection of the first layer of second conductivity type body regions in the vertical direction does not coincide with the second layer of second conductivity type body regions 111. That is, three regions are included from left to right above the first conductive type drift layer 102 of the ESD region, the first region including the gate oxide layer 105, the second isolation oxide layer 117, and the metal layer on the first conductive type drift layer 102; the second region comprises a gate oxide layer 105, a silicon nitride layer 107, a first isolation oxide layer 108, a first second conductive body region, a first conductive source region 113, a second isolation oxide layer 117 and a metal layer on the first conductive drift layer 102, wherein the metal layer penetrates through the second isolation oxide layer 117 through an ESD region contact hole 120 to be respectively contacted with the two first conductive source regions 113, the ESD region contact hole 120 close to the MOSFET region is contacted with the metal layer arranged on the second isolation oxide layer 117 to form a gate region metal layer 124, and the other ESD region contact hole 120 close to the Rg region is contacted with the metal layer arranged on the second isolation oxide layer 117 to form a Rg region-ESD region connecting metal layer 123; an Rg region contact hole 119 close to the Rg region in the ESD region penetrates through the second isolation oxide layer 117 and contacts with the first layer second conductive type body region to form an Rg region-ESD region connection metal layer 123; the third region includes the gate oxide layer 105, the second isolation oxide layer 117, and a metal layer on the first conductive-type drift layer 102, and the metal layer of the region is a portion of the Rg region — ESD region connection metal layer 123.
The Rg region includes the adjustable resistance region 116, the first layer second conductivity type body region, and the second layer second conductivity type body region 111. Specifically, the adjustable resistive region 116 is located above the first layer of the second conductivity type body region, which is formed by ion implantation into the first layer of the second conductivity type body region, so that the lower surface of the adjustable resistive region 116 is in contact with the upper surface of the first layer of the second conductivity type body region; further, the first layer of the second conductive type body region is located above the first conductive type drift layer 102, and a gate oxide layer 105, a silicon nitride layer 107 and a first isolation oxide layer 108 are further included between the first layer of the second conductive type body region and the first conductive type drift layer 102.
Further, the second layer of second conductivity type body regions 111 is located within the first conductivity type drift layer 102, and a projection of the first layer of second conductivity type body regions in the vertical direction does not coincide with the second layer of second conductivity type body regions 111. That is, three regions are included from left to right above the first conductive type drift layer 102 in the Rg region, the first region includes the gate oxide layer 105, the second isolation oxide layer 117, and the metal layer on the first conductive type drift layer 102, and the metal layer is a part of the Rg region — ESD region connection metal layer 123; the second region comprises a gate oxide layer 105, a silicon nitride layer 107, a first isolation oxide layer 108, a first second conductive type body region, an adjustable resistance region 116, a second isolation oxide layer 117 and two spaced metal layers on the first conductive type drift layer 102, wherein one metal layer penetrates through the second isolation oxide layer 117 through an Rg region contact hole 119 to be in contact with the adjustable resistance region 116, and a part of an Rg region-ESD region connecting metal layer 123 is formed; the other metal layer penetrates through the second isolation oxide layer 117 through the Rg area contact hole 119 to be in contact with the adjustable resistance area 116, and gate polysilicon-Rg area connection metal layer 122 is formed; the third region includes the gate oxide layer 105, the second isolation oxide layer 117, and a metal layer on the first conductive type drift layer 102, and the metal layer of the region is a portion of the gate polysilicon-Rg region connection metal layer 122.
It should be noted that the MOSFET device further includes a drain region metal layer 125, which is located below the first conductivity type substrate layer.
In the embodiment of the present invention, a first conductivity type substrate layer 101 may be provided first, and a first conductivity type drift layer 102 is generated on the first conductivity type substrate layer, where the first conductivity type substrate may be an N-type substrate or a P-type substrate, and when the first conductivity type substrate layer is an N-type substrate layer, the first conductivity type drift layer 102 disposed on the N-type substrate layer is an N-type epitaxial layer; when the substrate layer of the first conductivity type is a P-type substrate, the first conductivity type drift layer 102 disposed on the P-type substrate is a P-type epitaxial layer.
In order to more clearly describe the MOSFET device provided by the embodiment of the present invention, a method for manufacturing the MOSFET device is described below.
Fig. 2 is a schematic view of a process for manufacturing an integrated MOSFET device according to an embodiment of the present invention; fig. 3A is a schematic diagram of a first conductive type drift layer according to an embodiment of the present invention; fig. 3B is a schematic diagram illustrating the preparation of an active region trench according to an embodiment of the present invention; fig. 3C is a schematic diagram illustrating a sacrificial oxide layer according to an embodiment of the invention; FIG. 3D is a schematic diagram of the sacrificial oxide layer with the active area removed according to an embodiment of the present invention; fig. 3E is a schematic diagram of preparing a gate oxide layer on the first conductivity type drift layer and in the active region trench according to an embodiment of the present invention; FIG. 3F is a schematic diagram of a polysilicon layer according to an embodiment of the present invention; fig. 3G is a schematic diagram illustrating the preparation of a first layer of a second conductivity type body region according to an embodiment of the present invention; fig. 3H is a schematic diagram illustrating the preparation of a second-conductivity-type body region in a second layer according to an embodiment of the present invention; fig. 3I is a schematic diagram illustrating the preparation of a first conductive type source region according to an embodiment of the present invention; FIG. 3J is a schematic diagram illustrating the fabrication of an adjustable resistor according to an embodiment of the present invention; fig. 3K is a schematic view illustrating a second isolation oxide layer according to an embodiment of the invention.
In the following, the flow diagram of the manufacturing method provided by fig. 2 is combined with the manufacturing diagrams provided by fig. 3A to fig. 3K to describe in detail the manufacturing method of the integrated MOSFET device, and specifically, as shown in fig. 2, the method mainly includes the following steps:
101, forming a first layer of second conductive type body region on the undoped polysilicon layer above the first conductive type drift layer in an ion implantation mode; dividing the first conductivity type drift layer into a MOSFET region, an ESD region, and an Rg region;
102, forming a first layer of first conductive type source region on the first layer of second conductive type body region in the ESD region through ion implantation, and forming a second layer of first conductive type source region on the second layer of second conductive type body region on one side of the active region groove;
103, forming an adjustable resistance region on the first layer second conductive type body region of the Rg region through ion implantation;
and 104, forming contact holes in the second layer of second conductivity type body region, the second layer of first conductivity type source region, the first layer of first conductivity type source region and the adjustable resistance region, and sequentially forming a source region metal layer, a gate polysilicon-Rg region connecting metal layer, an Rg region-ESD region connecting metal layer and a gate region metal layer through the contact holes.
Specifically, as shown in fig. 3A, an N-type heavily doped semiconductor substrate layer is provided, which may be referred to as a first conductivity type substrate layer 101, and then an N-type lightly doped epitaxial layer is grown on the first conductivity type substrate layer 101, which is referred to as a first conductivity type drift layer 102.
As shown in fig. 3B, an active region trench 103 is formed in the first conductive type drift layer 102 by means of etching.
As shown in fig. 3C and 3D, a sacrificial oxide layer 104 is grown on the upper surface of the first conductive type drift layer 102 and inside the active region trench 103 by a thermal oxidation process, and then the sacrificial oxide layer 104 is etched away by an etching method. The etching method in this embodiment includes, but is not limited to, dry etching, wet etching, and mixed use of dry etching and wet etching, where the mixed use method includes, but is not limited to: the method comprises the steps of firstly using dry etching and then using wet etching, firstly using wet etching and then using dry etching, firstly using dry etching and then using wet etching and finally using dry etching, and firstly using wet etching and then using dry etching and finally using wet etching.
As shown in fig. 3E, a gate oxide layer 105 is grown by a thermal oxidation process on the upper surface of the first conductive type drift layer 102 and in the active region trench 103.
As shown in fig. 3F, a heavily N-doped polysilicon layer 106 is deposited on the top surface of the gate oxide layer 105 by a deposition process, i.e. while the heavily N-doped polysilicon layer 106 is formed in the active region trench 103, a heavily N-doped polysilicon layer 106 is deposited on the gate oxide layer 105 on both sides of the active region trench 103.
Further, a layer of heavily N-doped polysilicon layer 106 deposited on the gate oxide layer 105 on both sides of the active region trench 103 is etched away by an etch-back process.
As shown in fig. 3G, a nitride oxide layer, a first isolation oxide layer 108 and an undoped polysilicon layer 109 are deposited on the active region trench 103 and the gate oxide layer 105 on both sides of the active region trench 103 by chemical vapor deposition.
In step 101, a first layer of second conductivity type body region is formed on the undoped polysilicon layer 109 through a first ion implantation, where it is to be noted that the undoped polysilicon layer 109 is located at the uppermost layer of the first conductivity type drift layer 102, that is, when the first ion implantation is performed, all the implanted ions enter the undoped polysilicon layer 109, and then the undoped polysilicon layer 109 forms the first layer of second conductivity type body region.
As shown in fig. 3H, a first photoresist layer 110 is spin-coated on the first second conductive type body region (undoped polysilicon layer 109), and then the first photoresist layer 110 is exposed through a mask plate to form a photoresist mask.
Specifically, all layers inside the first conductivity type drift layer 102 and above the first conductivity type drift layer 102 are divided into a MOSFET region, an ESD region, and an Rg region from left to right in this order. Further, by means of etching, the silicon oxynitride layer, the first isolation oxide layer 108 and the formed first second conductive type body region on two sides of the ESD region, the Rg region, the MOSFET region and above the first conductive type drift layer 102 are etched away, it should be noted that the ESD region is located between the Rg region and the MOSFET region, that is, two sides of the ESD region are respectively in contact with one side of the Rg region and one side of the MOSFET region; further, the above description about the other side of the MOSFET region includes the silicon oxynitride layer between the active region trenches 103, over both sides of the active region trenches 103, the first isolation oxide layer 108, and the first layer second conductivity type body region.
In the embodiment of the invention, the grid electrode terminal and the source electrode terminal are integrated into an ESD structure, so that electrostatic breakdown of grid oxide can be prevented; further, when an Rg structure is integrated on the grid end to reduce the grid current, the shock resistance of the grid end of the device in application is further improved.
Further, a second layer of second conductivity type body region 111 is formed between the active region trenches 103, on both sides of the active region trenches 103, between the MOSFET region and the ESD region, between the ESD region and the Rg region, and on one side of the Rg region by a second implantation; it should be noted that, during the second ion implantation, a layer of photoresist is spin-coated on the first layer of second conductive type body region, so that the region that is located above the first conductive type drift layer 102 and is not etched away blocks ions entering the first conductive type drift layer 102.
When the first layer of second conductive type body region is used as a mask, the injection of the second layer of second conductive type body region 111 at the periphery is blocked to achieve the purpose of voltage resistance of the device, so that one layer of photoetching process can be reduced, and the production cost is reduced; further, the implantation energy of the first second conductivity type body region is required to ensure that the first second conductivity type body region cannot penetrate through the sum of the thicknesses of the undoped polysilicon layer 109 and the first isolation oxide layer 108 during implantation.
Further, a projection of the first layer second conductivity type body region located in the MOSFET region in the vertical direction does not coincide with the second layer second conductivity type body region 111; the projection of the first layer second conductivity type body region in the ESD region in the vertical direction does not coincide with the second layer second conductivity type body region 111; the projection in the vertical direction of the first layer second conductivity type body region located in the Rg region does not coincide with the second layer second conductivity type body region 111.
It should be noted that, in the embodiment of the present invention, the first ion implantation dose is two orders of magnitude of the second ion implantation dose, that is, when the first layer of the second conductive type body region is used as a mask, the dose of the second ion implantation dose does not affect the doping concentration of the first layer of the second conductive type body region, and therefore does not affect the anti-static capability of the ESD.
In step 102, a first conductive type source region and second photoresist layer 112 is formed above the first conductive type drift layer 102 through a photolithography process, then the second photoresist layer 112 is exposed through a mask plate to form a photoresist mask, two non-adjacent first conductive type source regions 113 are formed on the first conductive type body region in the ESD region through a third ion implantation, and second conductive type source regions 114 are formed between the active region trenches 103 and on one side of the active region trenches 103.
As shown in fig. 3I, the first layer first conductive type source region 113 and the second layer first conductive type source region 114 are formed at the same time, but the positions of the first layer first conductive type source region and the second layer first conductive type source region are different, and in order to avoid confusion in the description of the first conductive type source region, the first layer first conductive type source region 113 and the second layer first conductive type source region 114 are defined according to the different positions of the first conductive type source region.
In step 103, an adjustable resistance region 116 is formed on the first layer second conductive type body region of the Rg region by a fourth ion implantation.
Specifically, as shown in fig. 3J, a third photoresist layer is formed on the first second conductive type body region located in the Rg region through a photolithography process, and an adjustable resistance region 116 is formed in the first second conductive type body region through an ion implantation manner.
It should be noted that the adjustable resistive region 116 is formed in the context of an ESD implant, which may reduce a photolithography process and thus reduce the production cost. Further, the embodiment of the invention provides the adjustable resistive area 116, wherein the magnitude of the resistance value is related to the size of the ion implantation area, i.e. the shape of the third photoresist layer. Specifically, the third photoresist layer provided by the embodiment of the invention is formed on the upper surfaces of the MOSFET region, the ESD region and the Rg region, specifically, the third photoresist layer located in the Rg region covers two sides of the top of the first second conductive type body region, but the top of the first second conductive type body region in the Rg region may be in a partial covering manner. As shown in fig. 4A, the shape of the third photoresist layer located at the top of the first second conductive type body region may include two second rectangles with the same shape, which are disposed on the side edge between the two contact holes on the adjustable resistance region 116, and because two contact holes need to be disposed on the adjustable resistance region 116, the length of the long side of the two rectangles is smaller than the distance between the two contact holes, in this case, the area of the ion implantation region is larger, i.e., the via is largest, and thus the formed adjustable resistance region 116 is smallest; as shown in fig. 4B, the shape of the third photoresist layer on top of the first layer second conductivity type body region includes at least three first rectangles with the same shape and without contact, the shapes of the plurality of first rectangles are the same, and since two contact holes need to be disposed on the adjustable resistive region 116, the length of the long side of the plurality of rectangles is smaller than the distance between the two contact holes, in this case, the area of the ion implantation region is smaller than that of fig. 4A, and the path is smaller than that of fig. 4A, so that the adjustable resistive region 116 is formed larger than the resistor formed in fig. 4A; as shown in fig. 4C, the third photoresist layer at the top of the first layer of the second conductive type body region is shaped as a serpentine line including a plurality of third rectangles perpendicular to and parallel to the contact holes and a plurality of fourth matrixes parallel to the contact holes. It should be noted that, since two contact holes are required to be formed on the adjustable resistive region 116, the width of the serpentine is smaller than the distance between the two contact holes, in this case, the area of the ion implantation region is the smallest, i.e., the bending path is the smallest, and thus the adjustable resistive region 116 is the largest.
In step 104, as shown in fig. 3K, a second isolation oxide layer 117 is deposited on the first conductive type drift layer 102 by a deposition process, and a plurality of contact holes are formed by photolithography and etching, which are referred to as an active region contact hole 118, an esd region contact hole 120 and an Rg region contact hole 119 from left to right in sequence for convenience of description.
Further, the contact holes are filled with metal, a metal layer is sputtered on the surface of the wafer through a sputtering process, the metal layer is defined into a source layer metal layer 121, a gate polysilicon-Rg region connecting metal layer 122, an Rg region-ESD region connecting metal layer 123 and a gate region metal layer 124 through a photoetching and etching process, the wafer is thinned through a grinding process, and then a drain region metal layer 125 is formed through a metal evaporation process.
As shown in fig. 1, in the MOSFET region, a metal layer is in contact with the second layer second conductive type body region 111 through an active region contact hole 118 penetrating the second isolation oxide layer 117 and the gate oxide layer 105 to form a source region metal layer 121; in the ESD region, the metal layer contacts the two first-layer first-conductivity-type source regions 113 through one ESD region contact hole 120 penetrating the second isolation oxide layer 117, wherein the ESD region contact hole 120 near the MOSFET region contacts the metal layer disposed on the second isolation oxide layer 117, forming a gate region metal layer 124; another ESD region contact hole 120 near the Rg region contacts a metal layer disposed on the second isolation oxide layer 117, forming an Rg region — ESD region connecting a portion of the metal layer 123; an Rg region contact hole 119 close to the Rg region in the ESD region penetrates through the second isolation oxide layer 117 and contacts with the adjustable resistance region 116 to form an Rg region-ESD region connecting metal layer 123; in the Rg region, one metal layer penetrates through the second isolation oxide layer 117 through one Rg region contact hole 119 to contact with the adjustable resistance region 116, so as to form a portion of the Rg region-ESD region connection metal layer 123, and the other metal layer penetrates through the second isolation oxide layer 117 through the other Rg region contact hole 119 to contact with the adjustable resistance region 116, so as to form a gate polysilicon-Rg region connection metal layer 122. The drain region metal layer 125 is in contact with the lower surface of the first conductive type substrate layer 101.
In summary, the embodiment of the present invention provides an integrated MOSFET device, including: a non-doped polysilicon layer located above the first conductive type drift layer, which forms the first layer second conductive type body region by ion implantation; the active region groove is positioned in the MOSFET region, a second layer of second conductive type body region is arranged on two sides of the active region groove, and a second layer of first conductive type source region is arranged on the second layer of second conductive type body region positioned on one side of the active region groove; an ESD region between the MOSFET region and the Rg region; a first layer of first conductivity type source regions located within the first layer of second conductivity type body regions of the ESD region; an adjustable resistance region overlying the first layer second conductivity type body region within the Rg region.
While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all such alterations and modifications as fall within the scope of the invention.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (8)
1. An integrated MOSFET device, comprising:
a non-doped polysilicon layer located above the first conductive type drift layer and forming a first layer of a second conductive type body region by ion implantation;
the active region groove is positioned in the MOSFET region, a second layer of second conductive type body region is arranged on two sides of the active region groove, and a second layer of first conductive type source region is arranged on the upper layer of the second layer of second conductive type body region positioned on one side of the active region groove;
an ESD region located between the MOSFET region and Rg region;
a first layer of first conductivity type source regions located within a first layer of second conductivity type body regions of the ESD region;
an adjustable resistance region located at an upper layer of the first layer second conductive type region in the Rg region;
a third photoresist layer is arranged on the upper surfaces of the MOSFET area, the ESD area and the Rg area;
the third photoresist layer positioned on the upper surface of the Rg area is partially covered on two sides of the top of the first second conduction type body area, the first second conduction type body area of the Rg area is provided with an ion injection area, and an adjustable resistance area is arranged in the first second conduction type body area;
wherein the shape of the third photoresist layer covering the top part of the first layer second conductive type body region at least comprises: at least three first rectangles which are consistent in shape and are not in contact with each other, wherein the length of the long side of each first rectangle is smaller than the distance between two contact holes on the adjustable resistance area; or two second rectangles with the same shape are arranged on the side edge between the two contact holes on the adjustable resistance area, and the side length of the long edge of each second rectangle is smaller than the distance between the two contact holes; or a serpentine.
2. The device of claim 1, further comprising: an N-type heavily doped polysilicon layer and a gate oxide layer;
the grid oxide layer is arranged in the active region groove and above the first conduction type drift layer;
the N-type heavily doped polysilicon layer is arranged in the active region groove, and the upper surface of the N-type heavily doped polysilicon layer in the active region groove and the upper surfaces of the grid oxide layers on the two sides of the top of the active region groove have the same height.
3. The device of claim 1, further comprising a silicon oxynitride layer and a first isolation oxide layer;
the silicon oxynitride layer and the first isolation oxide layer are sequentially arranged above the grid oxide layer, and the upper surface of the first isolation oxide layer is contacted with the lower surface of the first second conduction type body region;
the silicon oxynitride layer, the first isolation oxide layer and the first second conductive type body region in the MOSFET region have the same width; the silicon oxynitride layer, the first isolation oxide layer and the first layer of second conductive type body region in the ESD region have the same width; the silicon oxynitride layer, the first isolation oxide layer and the first second conductive type body region in the Rg region have the same width;
and a gap exists between the first layer second conduction type body region positioned in the ESD region and the first layer second conduction type body region positioned in the MOSFET region and the first layer second conduction type body region positioned in the Rg region.
4. The device of claim 3, further comprising a first layer of body regions of the second conductivity type;
a projection in a vertical direction of the first layer of second conductivity type body regions located in the MOSFET region does not coincide with the second layer of second conductivity type body regions located in the MOSFET region;
contact holes are formed in the second layer of first conduction type source region on one side of the active region groove and the second layer of second conduction type body region between the active regions, and the contact holes are in contact with a metal layer arranged on the second isolation oxide layer to form a source region metal layer.
5. The device of claim 3, wherein a projection in a vertical direction of the first layer of body regions of second conductivity type located within the ESD region is not coincident with the second layer of body regions of second conductivity type located within the MOSFET region;
the projection of the first layer of second conductive type body region in the Rg region in the vertical direction is not overlapped with the second layer of second conductive type body region in the Rg region;
the two first-layer first conductive type source regions are positioned in the first-layer first conductive type body region and are not contacted, and each first-layer first conductive type source region is provided with a contact hole;
two contact holes are formed in the adjustable resistance area in the Rg area;
one contact hole in the ESD area close to the MOSFET area is contacted with a metal layer arranged on a second isolation oxide layer to form a gate area metal layer;
another contact hole in the ESD area close to the Rg area is in contact with a metal layer arranged on a second isolation oxide layer, and one contact hole in the ESD area close to the Rg area is in contact with the metal layer arranged on the second isolation oxide layer to form an Rg area-ESD area connecting metal layer;
and the other contact hole positioned in the Rg area is contacted with a metal layer arranged on the second isolation oxide layer to form grid polysilicon-Rg area connecting metal layer.
6. A method of making an integrated MOSFET device, comprising:
forming a first layer of second conductive type body region on the non-doped polycrystalline silicon layer above the first conductive type drift layer in an ion implantation mode; dividing the first conductivity type drift layer into a MOSFET region, an ESD region and an Rg region;
forming a first layer of first conductive type source region on the first layer of second conductive type body region in the ESD region through ion implantation, and forming a second layer of first conductive type source region on the second layer of second conductive type body region on one side of the active region groove;
forming an adjustable resistance region on the first layer second conductive type body region of the Rg region by ion implantation;
forming contact holes in the second layer of second conductive type body region, the second layer of first conductive type source region, the first layer of first conductive type source region and the adjustable resistance region, and sequentially forming a source region metal layer, a gate polysilicon-Rg region connecting metal layer, an Rg region-ESD region connecting metal layer and a gate region metal layer through the contact holes;
forming an adjustable resistance region on the first layer second conductive type body region of the Rg region by ion implantation, specifically comprising:
forming a third photoresist layer on the upper surfaces of the MOSFET area, the ESD area and the Rg area;
a third photoresist layer positioned on the upper surface of the Rg region covers two sides of the top of the first second conductive type body region, ion implantation is carried out on the first second conductive type body region positioned in the Rg region, and an adjustable resistance region is formed in the first second conductive type body region;
the third photoresist layer located on the upper surface of the Rg region covers two sides of the top of the first second conductive type body region, and the third photoresist layer further comprises:
the third photoresist layer is partially covered on the top of the first layer second conduction type body region in the Rg area, wherein the shape of the third photoresist layer on the top of the first layer second conduction type body region at least comprises: at least three first rectangles which are consistent in shape and are not in contact with each other, wherein the length of the long side of each first rectangle is smaller than the distance between two contact holes on the adjustable resistance area; or two second rectangles with the same shape are arranged on the side edge between the two contact holes on the adjustable resistance area, and the side length of the long edge of each second rectangle is smaller than the distance between the two contact holes; or a serpentine.
7. The method of claim 6, wherein before forming the first layer of body regions of the second conductivity type from the undoped polysilicon layer over the drift layer of the first conductivity type, further comprising:
forming an active region groove in the first conductive type drift layer by an etching method;
forming a grid oxide layer on the first conductive type drift layer and in the active region groove, and forming a polycrystalline silicon layer in the active region groove by chemical vapor deposition;
sequentially forming a silicon oxynitride layer, a first isolation oxide layer and a non-doped polycrystalline silicon layer on the upper surfaces of the grid oxide layer and the polycrystalline silicon layer;
before forming a first layer of first conductivity type source region on the first layer of second conductivity type body region in the ESD region by ion implantation, and forming a second layer of first conductivity type source region on the second layer of second conductivity type body region at one side of the active region trench, the method further includes:
removing the silicon oxynitride layer, the first isolation oxide layer and the first second conductive type body region which are positioned on two sides of the ESD region, two sides of the Rg region, two sides of the MOSFET region and above the first conductive type drift layer in an etching mode, wherein the ESD region is positioned between the Rg region and the MOSFET region; one side of the MOSFET region comprises the silicon oxynitride layer, the first isolation oxide layer and the first layer of second conductive type body region between the active region grooves and above two sides of the active region grooves;
forming a second layer of second conductivity type body region in the first conductivity type drift layer, wherein the projection of the first layer of second conductivity type body region in the vertical direction in the MOSFET region is not overlapped with the second layer of second conductivity type body region; the projection of the first layer of second-conductivity-type body region in the ESD area in the vertical direction is not overlapped with the second layer of second-conductivity-type body region; and the projection of the first layer of second conduction type body region in the Rg region in the vertical direction is not overlapped with the second layer of second conduction type body region.
8. The method according to claim 7, wherein the forming of the undoped polysilicon layer over the first conductivity type drift layer into the first and second conductivity type body regions is a first ion implantation and the forming of the second conductivity type body region in the first conductivity type drift layer is a second ion implantation; wherein the implantation dosage of the first ion implantation is larger than that of the second ion implantation.
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101919042A (en) * | 2007-12-31 | 2010-12-15 | 万国半导体股份有限公司 | Reduced mask configuration for power mosfets with electrostatic discharge (ESD) circuit protection |
| CN105990148A (en) * | 2015-01-26 | 2016-10-05 | 美普森半导体公司（股） | Method for manufacturing power semiconductor device having process of controlling switching characteristic |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US8004009B2 (en) * | 2009-05-18 | 2011-08-23 | Force Mos Technology Co., Ltd. | Trench MOSFETS with ESD Zener diode |
| US8164114B2 (en) * | 2009-05-18 | 2012-04-24 | Force Mos Technology Co., Ltd. | Semiconductor devices with gate-source ESD diode and gate-drain clamp diode |
| CN111029408A (en) * | 2019-12-17 | 2020-04-17 | 华羿微电子股份有限公司 | ESD integrated VDMOS device and preparation method thereof |
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| CN101919042A (en) * | 2007-12-31 | 2010-12-15 | 万国半导体股份有限公司 | Reduced mask configuration for power mosfets with electrostatic discharge (ESD) circuit protection |
| CN105990148A (en) * | 2015-01-26 | 2016-10-05 | 美普森半导体公司（股） | Method for manufacturing power semiconductor device having process of controlling switching characteristic |
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