CN104124195B - The forming method of groove isolation construction - Google Patents
The forming method of groove isolation construction Download PDFInfo
- Publication number
- CN104124195B CN104124195B CN201310158820.9A CN201310158820A CN104124195B CN 104124195 B CN104124195 B CN 104124195B CN 201310158820 A CN201310158820 A CN 201310158820A CN 104124195 B CN104124195 B CN 104124195B
- Authority
- CN
- China
- Prior art keywords
- liner layer
- insulation liner
- insulation
- minute
- opening
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76237—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials introducing impurities in trench side or bottom walls, e.g. for forming channel stoppers or alter isolation behavior
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
Abstract
A kind of forming method of groove isolation construction, including: Semiconductor substrate is provided, in described Semiconductor substrate, there is opening；Sidewall surfaces at described opening forms the first insulation liner layer；Lower surface at described opening forms the second insulation liner layer；After forming the first insulation liner layer and the second insulation liner layer, carry out process of surface treatment, make the first insulation liner layer in described opening and the second insulation liner layer surface have hydrogen-oxygen key, and the hydrogen-oxygen key density on described second insulation liner layer surface is more than the hydrogen-oxygen key density on the first insulation liner layer surface；After process of surface treatment, the first insulation liner layer and the second insulation liner layer surface in described opening form the insulating barrier filling full described opening.Tight in the fleet plough groove isolation structure formed, quality are good.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly relate to the forming method of a kind of groove isolation construction.
Background technology
Fleet plough groove isolation structure (Shallow Trench Isolation, STI) is in current semiconductor device manufactures
For device isolation.The technique of described fleet plough groove isolation structure includes: use etching technics to form opening (i.e. shallow ridges in substrate
Groove), described shallow trench be usually used at the bottom of isolation liner in active area；Formed in described substrate surface and opening and fill full gate mouth
Insulating barrier, the material of described insulating barrier includes silicon oxide；Use chemical machinery to throw technique and remove the insulating barrier higher than open top.
Along with the development of semiconductor technology, device size persistently reduces, and the integrated of integrated circuit improves constantly, and causes shallow
The width dimensions of groove isolation construction reduces the most accordingly, then for forming the depth-to-width ratio of the opening of fleet plough groove isolation structure
(aspect ratio) constantly increases, and produces space (void) in causing formed fleet plough groove isolation structure.Fig. 1 to Fig. 3
It it is the cross-sectional view of the forming process of the groove isolation construction of prior art high-aspect-ratio.
Refer to Fig. 1, it is provided that there is the substrate 100 of opening 101, the depth-to-width ratio of described opening 101 be more than 3:1, described in open
Sidewall and the lower surface of mouth 101 are formed with oxide liner layer 102.
Refer to Fig. 2, use chemical vapor deposition method to form insulation film in substrate 100 surface and opening 101
103.During forming described insulation film 103, insulant is easily deposited in the sidewall table near opening 101 top
Face, results in insulation film 103 thickness in opening 101 top sidewall thicker, and the insulation film 103 bottom opening 101
Thinner thickness.
Refer to Fig. 3, continue to use chemical vapor deposition method thickening insulation thin film 103, be positioned at the exhausted of opening 101 top
First edge thin film 103 closes, and appoints in opening 101 now and be not filled full, thus forms space 104.
Prior art, in order to overcome the filling problem in the opening of high-aspect-ratio, uses high-aspect-ratio process for filling hole
(HARP, High Aspect Ratio Process), to meet the filling demand of more high depth-width ratio open, advanced wide to realize
Tight than groove isolation construction.Concrete, with tetraethyl orthosilicate (TEOS) and ozone (O3) it is reacting gas, it is possible to fill
The depth-to-width ratio opening more than 6:1.
But, when the opening depth-to-width ratio continuation increase for forming groove isolation construction, described high-aspect-ratio process for filling hole
Or voiding problem can be produced.
Summary of the invention
The problem that the present invention solves is to provide the forming method of a kind of groove isolation construction, make formed shallow trench every
In structure, tight, quality are good.
For solving the problems referred to above, the present invention provides the forming method of a kind of groove isolation construction, including: quasiconductor lining is provided
The end, in described Semiconductor substrate, there is opening；Sidewall surfaces at described opening forms the first insulation liner layer；At described opening
Lower surface form the second insulation liner layer；After forming the first insulation liner layer and the second insulation liner layer, carry out table
Face processes technique, makes the first insulation liner layer in described opening and the second insulation liner layer surface have hydrogen-oxygen key, and described
The hydrogen-oxygen key density on the second insulation liner layer surface is more than the hydrogen-oxygen key density on the first insulation liner layer surface；In surface science and engineering
After skill, the first insulation liner layer and the second insulation liner layer surface in described opening are formed and fill the exhausted of full described opening
Edge layer.
Optionally, the formation process of described first insulation liner layer is: at described semiconductor substrate surface and opening
Sidewall and lower surface deposit the first insulation film；It is etched back to described first insulation film, removes and be positioned at semiconductor substrate surface
With first insulation film on open bottom surface, form the first insulation liner layer.
Optionally, being etched back to technique described in is anisotropic dry etch process.
Optionally, the material of described first insulation liner layer is silicon nitride, and the material of described second insulation liner layer is oxygen
SiClx.
Optionally, the formation process of described second insulation liner layer is thermal oxidation technology.
Optionally, after the thermal oxidation, carrying out thermal anneal process, the parameter of described thermal anneal process is: at hot oxygen
After metallization processes, carrying out thermal anneal process, the parameter of described thermal anneal process is: temperature is 500 degrees Celsius～800 degrees Celsius,
Time is 30 minutes～90 minutes.
Optionally, described process of surface treatment is: temperature is 400 DEG C～550 DEG C, steam H2The flow of O is 3000 standards
Ml/min～6000 standard milliliters/minute, the flow of carrier gas helium be 5000 standard milliliters/minute～15000 standards milli
Liter/min, air pressure is 2 torr～8 torr, and radio-frequency power is 500 watts～1000 watts.
Optionally, the depth-to-width ratio of described opening is more than 8:1.
Optionally, the formation process of described opening is: form mask layer at semiconductor substrate surface, and described mask layer exposes
Going out part semiconductor substrate surface, the material of described mask layer is silicon nitride；Serve as a contrast with described mask layer for mask etching quasiconductor
The end, forming opening, described mask layer is removed after forming insulating barrier.
Optionally, the formation process of described insulating barrier is: exhausted described Semiconductor substrate, the first insulation liner layer and second
Edge laying surface is formed fills full gate mouth insulation film；Use CMP process to remove and be positioned at semiconductor substrate surface
Insulation film, till exposing Semiconductor substrate.
Optionally, the material of described insulation film is silicon oxide, and formation process is chemical vapor deposition method.
Optionally, the deposition gases of described chemical vapor deposition method includes tetraethyl orthosilicate and ozone, described positive silicic acid
The flow of ethyl ester is 500 mg minute～8000 mg minute, the flow of ozone be 5000 standard milliliters/minute～3000 mark
Quasi-ml/min, air pressure is 300 torr～600 torr, and temperature is 400 degrees Celsius～600 degrees Celsius.
Optionally, described deposition gases also includes: nitrogen, oxygen and helium, the flow of nitrogen be 1000 standard milliliters/point
Clock～10000 standard milliliters/minute, the flow of oxygen be 0 standard milliliters/minute～5000 standard milliliters/minute, the stream of helium
Amount be 5000 standard milliliters/minute～20000 standard milliliters/minute.
Compared with prior art, technical scheme has the advantage that
The first insulation liner layer, described first insulation liner layer is formed on the opening sidewalls surface being used for being formed isolation structure
As the transition between the insulating barrier being subsequently formed and Semiconductor substrate；Lower surface at described opening forms the second insulation lining
Bed course；Owing to the density of the hydrogen-oxygen key of material surface is determined by the characteristic of material itself, it is possible to by adjusting the kind of material, make
The hydrogen-oxygen key density on the second insulation liner layer surface is more than the hydrogen-oxygen key density on described first insulation liner layer surface；Due to described
Hydrogen-oxygen key density is the biggest, and the speed being subsequently formed insulating barrier is the fastest, and therefore open bottom forms the speed of insulating barrier more than opening
Sidewall forms the speed of insulating barrier, it is possible to the problem that suppression open top insulating barrier closes too early because synthesis speed is too fast, protects
Demonstrate,prove tight in the insulating barrier of opening.The groove isolation construction formed is fine and close, quality is good, stable performance.
Further, the material of described first insulation liner layer is silicon nitride, and the material of described second dielectric substrate layers is oxygen
SiClx；Owing to the characteristic of material itself determines, the hydrogen-oxygen key density of silicon oxide surface is more than the hydrogen-oxygen key density of silicon nitride surface,
The hydrogen-oxygen key density on described first insulation liner layer surface is more than the hydrogen-oxygen key density on the second insulation liner layer surface, therefore the
Two insulation liner layer surfaces form the speed of insulating barrier and form the speed of insulating barrier less than the first insulation liner layer surface, it is possible to keep away
Exempt from the problem that the open top when opening is not filled by full has closed, advantageously form void-free groove isolation construction.
Accompanying drawing explanation
Fig. 1 to Fig. 3 is the cross-sectional view of the forming process of the groove isolation construction of prior art high-aspect-ratio；
Fig. 4 to Fig. 8 is the cross-sectional view of the forming process of groove isolation construction described in embodiments of the invention；
Fig. 9 is to use tetraethyl orthosilicate and ozone, form the mechanism schematic diagram of insulation film with high-aspect-ratio depositing operation.
Detailed description of the invention
As stated in the Background Art, the groove isolation construction content of the high-aspect-ratio that prior art is formed is easily formed space.
Study discovery through the present inventor, use high-aspect-ratio technique with silester and ozone as reacting gas
When forming silicon oxide film, sedimentation rate is relevant with the hydrogen-oxygen key density of institute's deposition surface, when the hydrogen-oxygen key of institute's deposition surface is close
When spending the highest, sedimentation rate is the fastest.In prior art, for forming the opening sidewalls of insulating barrier and the material phase of lower surface
With, then hydrogen-oxygen key similar density is close in the speed of described opening sidewalls and lower surface silicon oxide film.But, instead
Answering the sidewall at gas first easily contact openings top, the sidewall surfaces of the most described open top can first capture reacting gas shape
Become silicon oxide, cause forming the speed relatively open bottom of silicon oxide film faster in described open top；Deep when described opening
Wide continuation increases, and when being greater than 10:1, reacting gas arrives the difficulty of open bottom and increases, and causes open bottom to form oxidation
The rate reduction of silicon thin film, open top forms the speed of silicon oxide film comparatively fast simultaneously, the most still can cause open top
Insulating layer of silicon oxide first close, and in opening, form space, cause producing in formed groove isolation construction space, institute
State space and can reduce isolation effect, or capture electric charge, easily cause formed device performance unstable.
Study further through the present inventor, in the opening sidewalls surface formation first for forming isolation structure
Insulation liner layer, described first insulation liner layer is as the transition between the insulating barrier being subsequently formed and Semiconductor substrate；Institute
The lower surface stating opening forms the second insulation liner layer；Owing to the density of hydrogen-oxygen key of material surface is by the characteristic of material itself
Determine, it is possible to by adjusting the kind of material, make the hydrogen-oxygen key density on the second insulation liner layer surface more than described first insulation
The hydrogen-oxygen key density on laying surface；Owing to described hydrogen-oxygen key density is the biggest, the speed being subsequently formed insulating barrier is the fastest, therefore opens
The speed forming insulating barrier bottom Kou forms the speed of insulating barrier more than opening sidewalls, it is possible to suppression open top insulating barrier is because of shape
The problem becoming speed too fast and to close too early, it is ensured that tight in the insulating barrier of opening.The groove isolation construction formed causes
Close, quality good, stable performance.
Understandable, below in conjunction with the accompanying drawings to the present invention for enabling the above-mentioned purpose of the present invention, feature and advantage to become apparent from
Specific embodiment be described in detail.
Fig. 4 to Fig. 8 is the cross-sectional view of the forming process of the groove isolation construction of the embodiment of the present invention.
Refer to Fig. 4, it is provided that Semiconductor substrate 200, in described Semiconductor substrate 200, there is opening 201.
Described Semiconductor substrate 200 is for providing work platforms for subsequent technique, and the material of described Semiconductor substrate 200 is
Silicon, SiGe, carborundum, silicon-on-insulator or III-V (such as gallium nitride or GaAs etc.).
It is subsequently used in described opening 201 forming fleet plough groove isolation structure (STI, Shallow Trench
Isolation)；The formation process of described opening 201 includes: Semiconductor substrate 200 surface formed mask layer 202, described in cover
Film layer 202 defines the position of active area of semiconductor device, and exposes Semiconductor substrate 200 table needing to form opening 201
Face, the combination that material is silicon oxide, silicon nitride or silicon oxide and silicon nitride of described mask layer 202；With described mask layer 202 it is
Mask, uses anisotropic dry etch process etch semiconductor substrates, forms opening 201 in Semiconductor substrate 200.
Along with the characteristic size of semiconductor device persistently reduce, the integrated level of integrated circuit improves constantly, cause reducing shape
The width dimensions at the groove isolation construction top become constantly reduces, and the degree of depth of described groove isolation construction should not reduce accordingly,
Thus causing the depth-to-width ratio of the opening 201 for forming isolation structure constantly to increase, described opening 201 top width is a size of
30nm～50nm, the depth-to-width ratio of described opening 201 is more than 6:1.In the present embodiment, the depth-to-width ratio of described opening 201 is more than 8:
1。
When the depth-to-width ratio of described opening 201 is relatively big, when being greater than 6:1, follow-up filling insulation material in described opening 201
The difficulty of material improves, and is difficult to the bottom well into opening 201, easily open described for filling the insulant of opening 201
In the case of mouth 201 tops are closed by insulant, still there is in described opening the space not being filled full.
Therefore, the present embodiment is by reducing the synthesis speed of the sidewall surfaces insulation film near opening 201 top, and carries
The synthesis speed of high opening 201 bottom insulation thin film, to avoid opening 201 top to close too early, thus is being subsequently formed without empty
The isolation structure of gap.
Refer to Fig. 5, the sidewall surfaces at described opening 201 forms the first insulation liner layer 203.
Owing to the sidewall of the speed with opening that are subsequently formed insulation film and the hydrogen-oxygen key density of lower surface are relevant, hydrogen-oxygen
Key density is the highest, and the synthesis speed of insulation film is the highest；And the material that described hydrogen-oxygen key density and described hydrogen-oxygen key are depended on is originally
Body characteristic is relevant；Described first insulation liner layer 203 is formed at the sidewall surfaces of opening 201, follow-up in the first insulation in order to make
Laying 203 surface forms the speed of insulation film less than the speed forming insulation film bottom opening 201, needs to make first exhausted
The hydrogen-oxygen key density on its surface of material that edge laying 203 uses is less than the second insulation lining being subsequently formed bottom opening 201
Bed course such that it is able to the insulation film synthesis speed of suppression opening 201 sidewall surfaces, it is to avoid opening 201 closes too early and causes
The problem in the groove isolation construction formed with space.
The formation process of described first insulation liner layer 203 is: mask layer 202 table in described Semiconductor substrate 200
Face and the sidewall of opening 201 and lower surface deposit the first insulation film；It is etched back to described first insulation film, removes position
In semiconductor substrate surface and first insulation film on open bottom surface, form the first insulation liner layer 203.
Described depositing operation is chemical vapor deposition method, it is possible to controls the thickness of described first insulation film, i.e. etches
The thickness of the first dielectric substrate layers 203 of rear formation is controlled by described chemical vapor deposition method.
The described technique that is etched back to is anisotropic dry etch process, such as plasma dry etch process；Institute
Stating in anisotropic dry etch process, etching gas vertically bombards and Semiconductor substrate 200 surface, covers therefore, it is possible to remove
Film layer 202 surface and first insulation film on open bottom surface, and be positioned at the first insulation film of opening 201 sidewall surfaces with
The direction of motion of etching gas is parallel, therefore, it is difficult to removed by bombardment, makes the first insulation film of opening 201 sidewall surfaces be protected
Stay.
In the present embodiment, the thickness of described first insulation liner layer 203 is 20 angstroms～200 angstroms, described first insulating cell
The material of layer 203 is silicon nitride, and the hydrogen-oxygen key density that described silicon nitride surface can depend on is less than the hydrogen on silica material surface
Oxygen key density, follow-up at opening 201 lower surface formation silicon oxide, the hydrogen-oxygen key that can either make opening 201 lower surface is close
Spend higher, and the hydrogen-oxygen key density of opening 201 sidewall surfaces is relatively low, closes too early when being conducive to avoiding being subsequently formed insulation film
Opening 201.
Refer to Fig. 6, the lower surface at described opening 201 forms the second insulation liner layer 204.
In the present embodiment, owing to the material of described first insulation liner layer 203 is silicon nitride, in order to make bottom opening 201
The hydrogen-oxygen key density on surface is higher than the hydrogen-oxygen key density on the first insulation liner layer 203 surface, described second insulation liner layer 204
Material is silicon oxide.
Owing to, in the present embodiment, described Semiconductor substrate 200 surface has mask layer 202, the sidewall table of described opening 201
Mask has the first insulation liner layer 203, the most only exposes the Semiconductor substrate 200 of the bottom of described opening 201, therefore described
Second insulation liner layer 204 can use thermal oxidation technology to be formed；The thickness of described second insulation liner layer 204 be 20 angstroms～
200 angstroms.
Described first insulation liner layer 203 and the second insulation liner layer 204 can be as Semiconductor substrate 200 and follow-up shapes
Transition between the insulating barrier become, makes the bond quality between insulating barrier and the Semiconductor substrate 200 being subsequently formed more preferable, reduces
Defect between insulating barrier and Semiconductor substrate 200 contact interface, improves the stability of the semiconductor device formed.
In one embodiment, after described second insulation liner layer 204 of described formation, carry out thermal anneal process, described
The parameter of thermal anneal process is: temperature is 500 degrees Celsius～800 degrees Celsius, and the time is 30 minutes～90 minutes；Described thermal annealing
Technique can remove the first insulation liner layer 203 and the second insulation liner layer 204, and makes described first insulation liner layer 203 He
Bond quality between second insulation liner layer 204 and Semiconductor substrate 200 is more preferable.
It should be noted that in other embodiments, described first insulation liner layer 203 and the second insulation liner layer 204
Material can be adjusted according to concrete process requirements, it is only necessary to meet the hydrogen of material surface of the first insulation liner layer 203
Oxygen key density is less than described second insulation liner layer 204.
Refer to Fig. 7, after forming the first insulation liner layer 203 and the second insulation liner layer 204, carry out surface science and engineering
Skill, makes the first insulation liner layer 203 in described opening and the second insulation liner layer 204 surface have hydrogen-oxygen key, and described
The hydrogen-oxygen key density on two insulation liner layer 204 surfaces is more than the hydrogen-oxygen key density on the first insulation liner layer 203 surface.
Described process of surface treatment is: temperature is 400 DEG C～550 DEG C, and place's process gases is steam (H2O), the flow of steam
Be 3000 standard milliliters/minute～6000 standard milliliters/minute, the flow of carrier gas helium be 5000 standard milliliters/minute～
15000 standard milliliters/minute, air pressure is 2 torr～8 torr, and radio-frequency power is 500 watts～1000 watts.
Described process of surface treatment is used for making described first insulation liner layer 203 and the second insulation liner layer 204 surface band
There is hydrogen-oxygen key；And, described first insulation liner layer 203 or the second insulation liner layer 204 with hydrogen-oxygen key density by institute
The material behavior stating the first insulation liner layer 203 and the second insulation liner layer 204 determines.
In the present embodiment, the material of described first insulation liner layer 203 is silicon nitride, described second insulation liner layer
The material of 204 is silicon oxide, and after process of surface treatment, the hydrogen-oxygen key density on described second insulation liner layer 204 surface is big
In the hydrogen-oxygen key density on the first insulation liner layer 203 surface, described second insulation liner layer 204 surface is made to form insulation film
Speed forms the speed of insulation film higher than the first insulation liner layer 203 surface；It is thus possible in avoiding follow-up described opening 201
When forming insulation film, described opening 201 be not filled by full before, described opening 201 closes too early, and then avoids being formed
Space is produced, it is possible to make formed performance of semiconductor device more stable in groove isolation construction.
Refer to Fig. 8, in described mask layer the 202, first insulation liner layer 203 and the second insulation liner layer 204 surface shape
Become to fill full gate mouth 201(as shown in Figure 7) insulation film 205.
It should be noted that after forming described insulation film 205, use CMP process planarization described
Insulation film 205, till exposing Semiconductor substrate 200 surface, forms insulating barrier (not shown), described insulating barrier i.e. institute
The groove isolation construction that need to be formed.
The material of described insulation film 205 is silicon oxide, and the formation process of described insulation film 205 is chemical gaseous phase deposition
Technique；In the present embodiment, high-aspect-ratio depositing operation (HARP) is used to form described insulation film 205；Described high-aspect-ratio
In chemical vapor deposition method, deposition gases includes tetraethyl orthosilicate Si(OC2H5)4With ozone O3, the stream of described tetraethyl orthosilicate
Amount is 500 mg minute～8000 mg minute, the flow of ozone be 5000 standard milliliters/minute～3000 standard milliliters/
Minute, air pressure is 300 torr～600 torr, and temperature is 400 degrees Celsius～600 degrees Celsius；Additionally, deposition gases also includes: nitrogen,
Oxygen and helium, the flow of nitrogen be 1000 standard milliliters/minute～10000 standard milliliters/minute, the flow of oxygen is 0 mark
Quasi-ml/min～5000 standard milliliters/minute, the flow of helium be 5000 standard milliliters/minute～20000 standard milliliters/
Minute.In described chemical vapor deposition processes, the hydrogen-oxygen key density being positioned at opening sidewalls and lower surface is the highest, forms insulation
The speed of thin film 205 is the fastest, illustrates below with reference to accompanying drawing.
Refer to Fig. 9, Fig. 9 be employing tetraethyl orthosilicate and ozone, form insulation film 205 with high-aspect-ratio depositing operation
Mechanism schematic diagram.
Wherein, as shown in Fig. 9 (a), tetraethyl orthosilicate Si(OC2H5)4One-(OC in molecule2H5) key and ozone reaction
Form hydrogen-oxygen key-OH；As shown in Figure 9 (b), Si(OC2H5)3(OH) the hydrogen-oxygen key phase of the hydrogen-oxygen key that molecule is carried and material surface
In conjunction with, formed with three-(OC at described material surface2H5) silicon oxide of key；As shown in Figure 9 (c), silicon oxide carried-
(OC2H5) key continues and ozone reaction forms hydrogen-oxygen key, i.e. forms the silicon oxide with hydrogen-oxygen key, the hydrogen-oxygen key of described silicon oxide
Can continue to form silicon oxide with deposition gases molecule.Therefore, the hydrogen-oxygen key density of material surface is the highest, it is possible to the most depositions
Gas molecule reacts, and the speed forming silicon oxide is the fastest.
In the present embodiment, form the first insulation liner layer with silicon nitride as material on opening sidewalls surface, in open bottom
Surface, portion forms the with silicon oxide as material and insulation liner layer；After carrying out process of surface treatment with steam, due to material
Material self character relation, the hydrogen-oxygen key density of described silicon oxide surface is more than the hydrogen-oxygen key density of silicon nitride surface, and described hydrogen
Oxygen key is the most, and the speed forming the described insulation film with silicon oxide as material is the fastest；Therefore, on the second insulation liner layer surface
Forming insulation film speed very fast, the speed forming insulation film on the first insulation liner layer surface is slower；Fill at opening 201
Before Man, it is possible to ensure that the top of described opening 201 will not close, make tight, quality in formed groove isolation construction
Good, it is ensured that the performance of semiconductor device formed is stable.
In sum, form the first insulation liner layer on the opening sidewalls surface for forming isolation structure, described first
Insulation liner layer is as the transition between the insulating barrier being subsequently formed and Semiconductor substrate；Lower surface at described opening is formed
Second insulation liner layer；Owing to the density of the hydrogen-oxygen key of material surface is determined by the characteristic of material itself, it is possible to by adjusting material
The kind of material, the hydrogen-oxygen key density making the second insulation liner layer surface is close more than the hydrogen-oxygen key on described first insulation liner layer surface
Degree；Owing to described hydrogen-oxygen key density is the biggest, the speed being subsequently formed insulating barrier is the fastest, and therefore open bottom forms the speed of insulating barrier
Rate forms the speed of insulating barrier more than opening sidewalls, it is possible to suppression open top insulating barrier closes too early because synthesis speed is too fast
Problem, it is ensured that tight in the insulating barrier of opening.The groove isolation construction formed is fine and close, quality is good, stable performance.
Further, the material of described first insulation liner layer is silicon nitride, and the material of described second dielectric substrate layers is oxygen
SiClx；Owing to the characteristic of material itself determines, the hydrogen-oxygen key density of silicon oxide surface is more than the hydrogen-oxygen key density of silicon nitride surface,
The hydrogen-oxygen key density on described first insulation liner layer surface is more than the hydrogen-oxygen key density on the second insulation liner layer surface, therefore the
Two insulation liner layer surfaces form the speed of insulating barrier and form the speed of insulating barrier less than the first insulation liner layer surface, it is possible to keep away
Exempt from the problem that the open top when opening is not filled by full has closed, advantageously form void-free groove isolation construction.
Although present disclosure is as above, but the present invention is not limited to this.Any those skilled in the art, without departing from this
In the spirit and scope of invention, all can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Limit in the range of standard.
Claims (13)
1. the forming method of a groove isolation construction, it is characterised in that including:
Semiconductor substrate is provided, in described Semiconductor substrate, there is opening；
Sidewall surfaces at described opening forms the first insulation liner layer；
Lower surface at described opening forms the second insulation liner layer；
After forming the first insulation liner layer and the second insulation liner layer, carry out process of surface treatment, in making described opening
First insulation liner layer and the second insulation liner layer surface have hydrogen-oxygen key, and the hydrogen-oxygen key on described second insulation liner layer surface
Density is more than the hydrogen-oxygen key density on the first insulation liner layer surface；
After process of surface treatment, the first insulation liner layer and the second insulation liner layer surface in described opening are formed and fill out
Being full of the insulating barrier of described opening, the material of described insulating barrier is silicon oxide.
2. the forming method of groove isolation construction as claimed in claim 1, it is characterised in that the shape of described first insulation liner layer
The technique is become to be: to deposit the first insulation film at described semiconductor substrate surface and the sidewall of opening and lower surface；It is etched back to
Described first insulation film, removes the first insulation film being positioned at semiconductor substrate surface and open bottom surface, forms first
Insulation liner layer.
3. the forming method of as claimed in claim 2 groove isolation construction, it is characterised in that described in be etched back to technique be each to different
The dry etch process of property.
4. the forming method of groove isolation construction as claimed in claim 1, it is characterised in that the material of described first insulation liner layer
Material is silicon nitride, and the material of described second insulation liner layer is silicon oxide.
5. the forming method of groove isolation construction as claimed in claim 4, it is characterised in that the shape of described second insulation liner layer
One-tenth technique is thermal oxidation technology.
6. the forming method of groove isolation construction as claimed in claim 5, it is characterised in that after the thermal oxidation, carry out
Thermal anneal process, the parameter of described thermal anneal process is: temperature is 500 degrees Celsius～800 degrees Celsius, and the time is 30 minutes～90
Minute.
7. the forming method of groove isolation construction as claimed in claim 1, it is characterised in that described process of surface treatment is: temperature
Degree is 400 DEG C～550 DEG C, steam H2The flow of O be 3000 standard milliliters/minute～6000 standard milliliters/minute, carrier gas helium
Flow be 5000 standard milliliters/minute～15000 standard milliliters/minute, air pressure is 2 torr～8 torr, and radio-frequency power is 500 watts
～1000 watts.
8. the forming method of groove isolation construction as claimed in claim 1, it is characterised in that the depth-to-width ratio of described opening is more than 8:
1。
9. the forming method of groove isolation construction as claimed in claim 1, it is characterised in that the formation process of described opening is:
Forming mask layer at semiconductor substrate surface, described mask layer exposes part semiconductor substrate surface, the material of described mask layer
Material is silicon nitride；With described mask layer for mask etching Semiconductor substrate, formed opening, described mask layer formed insulating barrier it
After be removed.
10. the forming method of groove isolation construction as claimed in claim 1, it is characterised in that the formation process of described insulating barrier
For: formed on described Semiconductor substrate, the first insulation liner layer and the second insulation liner layer surface and fill full gate mouth insulation film；
Using CMP process to remove the insulation film being positioned at semiconductor substrate surface, until exposing Semiconductor substrate being
Only.
The forming method of 11. groove isolation constructions as claimed in claim 10, it is characterised in that the material of described insulation film is
Silicon oxide, formation process is chemical vapor deposition method.
The forming method of 12. groove isolation constructions as claimed in claim 11, it is characterised in that described chemical vapor deposition method
Deposition gases include tetraethyl orthosilicate and ozone, the flow of described tetraethyl orthosilicate be 500 mg minute～8000 milligrams/
Minute, the flow of ozone be 5000 standard milliliters/minute～3000 standard milliliters/minute, air pressure is 300 torr～600 torr, temperature
It it is 400 degrees Celsius～600 degrees Celsius.
The forming method of 13. groove isolation constructions as claimed in claim 12, it is characterised in that described deposition gases also includes:
Nitrogen, oxygen and helium, the flow of nitrogen be 1000 standard milliliters/minute～10000 standard milliliters/minute, the flow of oxygen
Be 0 standard milliliters/minute～5000 standard milliliters/minute, the flow of helium be 5000 standard milliliters/minute～20000 standards
Ml/min.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310158820.9A CN104124195B (en) | 2013-04-28 | 2013-04-28 | The forming method of groove isolation construction |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310158820.9A CN104124195B (en) | 2013-04-28 | 2013-04-28 | The forming method of groove isolation construction |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104124195A CN104124195A (en) | 2014-10-29 |
| CN104124195B true CN104124195B (en) | 2016-12-28 |
Family
ID=51769561
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310158820.9A Active CN104124195B (en) | 2013-04-28 | 2013-04-28 | The forming method of groove isolation construction |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104124195B (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115332153A (en) | 2017-12-29 | 2022-11-11 | 联华电子股份有限公司 | Semiconductor element and manufacturing method thereof |
| US10522390B1 (en) * | 2018-06-21 | 2019-12-31 | Taiwan Semiconductor Manufacturing Co., Ltd. | Shallow trench isolation for integrated circuits |
| CN111403282B (en) * | 2020-01-02 | 2022-01-04 | 杭州士兰微电子股份有限公司 | Trench gate MOSFET power semiconductor device and polysilicon filling method and manufacturing method thereof |
| CN111192925B (en) * | 2020-01-07 | 2021-12-31 | 杭州士兰微电子股份有限公司 | Trench gate MOSFET power semiconductor device and polysilicon filling method and manufacturing method thereof |
| CN111933571B (en) * | 2020-10-10 | 2021-02-19 | 晶芯成(北京)科技有限公司 | Semiconductor structure and manufacturing method thereof |
| CN117238839B (en) * | 2023-11-10 | 2024-02-09 | 合肥晶合集成电路股份有限公司 | Shallow trench isolation structure and forming method thereof |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101515560A (en) * | 2008-02-18 | 2009-08-26 | 台湾积体电路制造股份有限公司 | A method for forming a shallow trench isolation region |
| CN102104040A (en) * | 2009-12-18 | 2011-06-22 | 和舰科技(苏州)有限公司 | Semiconductor device with shallow-trench isolation structure and manufacturing method thereof |
| TW201218313A (en) * | 2010-10-28 | 2012-05-01 | Macronix Int Co Ltd | Semiconductor structure and manufacturing method of the same |
-
2013
- 2013-04-28 CN CN201310158820.9A patent/CN104124195B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101515560A (en) * | 2008-02-18 | 2009-08-26 | 台湾积体电路制造股份有限公司 | A method for forming a shallow trench isolation region |
| CN102104040A (en) * | 2009-12-18 | 2011-06-22 | 和舰科技(苏州)有限公司 | Semiconductor device with shallow-trench isolation structure and manufacturing method thereof |
| TW201218313A (en) * | 2010-10-28 | 2012-05-01 | Macronix Int Co Ltd | Semiconductor structure and manufacturing method of the same |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104124195A (en) | 2014-10-29 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104795331B (en) | The forming method of transistor | |
| CN104124195B (en) | The forming method of groove isolation construction | |
| CN104124193B (en) | The forming method of groove isolation construction | |
| US7442620B2 (en) | Methods for forming a trench isolation structure with rounded corners in a silicon substrate | |
| CN106373924A (en) | Semiconductor structure forming method | |
| CN107293545B (en) | Semiconductor memory device and method of manufacturing the same | |
| US20150041948A1 (en) | Semiconductor device including sti structure and method for forming the same | |
| CN106486374B (en) | The forming method of semiconductor structure | |
| CN104752215B (en) | The forming method of transistor | |
| CN103531522B (en) | Fleet plough groove isolation structure preparation method | |
| CN105655284A (en) | Formation method of trench isolation structure | |
| CN102222636B (en) | Manufacturing method of shallow trench isolation | |
| CN106571336A (en) | Method for forming fin field effect transistor | |
| CN107039535A (en) | Capacitor element and forming method thereof | |
| CN103943621A (en) | Shallow trench isolation structure and forming method thereof | |
| CN102437083A (en) | Method for reducing critical dimension loss of high aspect ratio process filling shallow isolation trench | |
| CN103531523A (en) | Preparation method of STI (shallow trench isolation) structure | |
| CN104795351B (en) | The forming method of isolation structure | |
| CN107591323A (en) | The forming method of isolation structure | |
| CN106952815A (en) | The forming method of fin transistor | |
| CN106952911B (en) | The forming method of fin semiconductor devices | |
| WO2021228269A1 (en) | Method for preparing embedded word line structure | |
| CN104637881A (en) | Method for forming shallow trench isolation structure | |
| CN104425277B (en) | The forming method of transistor | |
| CN107591399A (en) | Semiconductor structure and forming method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |