CN104124195A - Method for forming groove isolation structure - Google Patents
Method for forming groove isolation structure Download PDFInfo
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- CN104124195A CN104124195A CN201310158820.9A CN201310158820A CN104124195A CN 104124195 A CN104124195 A CN 104124195A CN 201310158820 A CN201310158820 A CN 201310158820A CN 104124195 A CN104124195 A CN 104124195A
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- liner layer
- insulation liner
- opening
- groove isolation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76237—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials introducing impurities in trench side or bottom walls, e.g. for forming channel stoppers or alter isolation behavior
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Abstract
A method for forming a groove isolation structure comprises the steps of providing a semiconductor substrate which is internally provided with an opening; forming a first insulating gasket layer on the surface of a side wall of the opening; forming a second insulating gasket layer on the surface of the bottom of the opening; after the first insulating gasket layer and the second insulating gasket layer are formed, performing a surface treatment process so that the surface of the first insulating gasket layer and the surface of the second insulating gasket layer in the opening are provided with hydroxyl bonds and the thickness of the hydroxyl bonds on the surface of the second insulating gasket layer is larger than that of the hydroxyl bonds on the surface of the first insulating gasket layer; and forming an insulating layer filling the opening on the surface of the first insulating gasket layer and the surface of the second insulating gasket layer in the opening. The formed groove isolation structure is voidless and good in quality.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, relate in particular to a kind of formation method of groove isolation construction.
Background technology
Fleet plough groove isolation structure (Shallow Trench Isolation, STI) in current semiconductor device is manufactured for device isolation.The technique of described fleet plough groove isolation structure comprises: adopt etching technics in substrate, to form opening (being shallow trench), the active area of described shallow trench in being usually used at the bottom of isolation liner; In described substrate surface and opening, form the insulating barrier of filling full gate mouth, the material of described insulating barrier comprises silica; Adopt chemical machinery to throw technique and remove the insulating barrier higher than open top.
Along with the development of semiconductor technology, device size continues to dwindle, the integrated of integrated circuit improves constantly, cause also corresponding the reducing of width dimensions of fleet plough groove isolation structure, the depth-to-width ratio (aspect ratio) that is used to form the opening of fleet plough groove isolation structure constantly increases, and can cause generation space (void) in formed fleet plough groove isolation structure.Fig. 1 to Fig. 3 is the cross-sectional view of the forming process of the groove isolation construction of prior art high-aspect-ratio.
Please refer to Fig. 1, the substrate 100 with opening 101 is provided, the depth-to-width ratio of described opening 101 is greater than 3:1, and the sidewall of described opening 101 and lower surface are formed with oxide liner layer 102.
Please refer to Fig. 2, adopt chemical vapor deposition method on substrate 100 surfaces and the interior formation insulation film 103 of opening 101.Forming in the process of described insulation film 103, insulating material is easily deposited in the sidewall surfaces near opening 101 tops, and insulation film 103 thickness that cause being formed at opening 101 top sidewalls are thicker, and insulation film 103 thinner thicknesses of opening 101 bottoms.
Please refer to Fig. 3, continue to adopt chemical vapor deposition method to thicken insulation film 103, the insulation film 103 that is positioned at opening 101 tops is first closed, and in opening 101 now, appoint be not filled full, thereby form space 104.
Prior art is in order to overcome the filling problem in the opening of high-aspect-ratio, adopt high-aspect-ratio process for filling hole (HARP, High Aspect Ratio Process), to meet the more filling demand of high depth-width ratio open, to realize the tight of high aspect ratio trench quite isolation structure.Concrete, with tetraethoxysilane (TEOS) and ozone (O
3) be reacting gas, can fill the opening that depth-to-width ratio is greater than 6:1.
But, continuing to increase when being used to form the opening depth-to-width ratio of groove isolation construction, described high-aspect-ratio process for filling hole still can produce space problem.
Summary of the invention
The problem that the present invention solves is to provide a kind of formation method of groove isolation construction,, make tight in formed fleet plough groove isolation structure, quality good.
For addressing the above problem, the invention provides a kind of formation method of groove isolation construction, comprising: Semiconductor substrate is provided, in described Semiconductor substrate, there is opening; Form the first insulation liner layer in the sidewall surfaces of described opening; Form the second insulation liner layer in the lower surface of described opening; After forming the first insulation liner layer and the second insulation liner layer, carry out process of surface treatment, make the first insulation liner layer and the second insulation liner layer surface in described opening there is hydrogen-oxygen key, and the hydrogen-oxygen key density on described the second insulation liner layer surface is greater than the hydrogen-oxygen key density on the first insulation liner layer surface; After process of surface treatment, the first insulation liner layer in described opening and the second insulation liner layer surface form the insulating barrier of filling full described opening.
Optionally, the formation technique of described the first insulation liner layer is: sidewall and lower surface at described semiconductor substrate surface and opening deposit the first insulation film; Return the first insulation film described in etching, remove the first insulation film that is positioned at semiconductor substrate surface and open bottom surface, form the first insulation liner layer.
Optionally, described time etching technics is anisotropic dry etch process.
Optionally, the material of described the first insulation liner layer is silicon nitride, and the material of described the second insulation liner layer is silica.
Optionally, the formation technique of described the second insulation liner layer is thermal oxidation technology.
Optionally, after thermal oxidation technology, carry out thermal anneal process, the parameter of described thermal anneal process is: after thermal oxidation technology, carry out thermal anneal process, the parameter of described thermal anneal process is: temperature is 500 degrees Celsius～800 degrees Celsius, and the time is 30 minutes～90 minutes.
Optionally, described process of surface treatment is: temperature is 400 DEG C～550 DEG C, steam H
2the flow of O is 3000 standard ml/min～6000 standard ml/min, and the flow of carrier gas helium is 5000 standard ml/min～15000 standard ml/min, and air pressure is 2 holder～8 holders, and radio-frequency power is 500 watts～1000 watts.
Optionally, the depth-to-width ratio of described opening is greater than 8:1.
Optionally, the formation technique of described opening is: form mask layer at semiconductor substrate surface, described mask layer exposes part semiconductor substrate surface, and the material of described mask layer is silicon nitride; Taking described mask layer as mask etching Semiconductor substrate, form opening, described mask layer is removed after forming insulating barrier.
Optionally, the formation technique of described insulating barrier is: form and fill full gate mouth insulation film on described Semiconductor substrate, the first insulation liner layer and the second insulation liner layer surface; Adopt CMP (Chemical Mechanical Polishing) process to remove and be positioned at the insulation film of semiconductor substrate surface, until expose Semiconductor substrate.
Optionally, the material of described insulation film is silica, and formation technique is chemical vapor deposition method.
Optionally, the deposition gases of described chemical vapor deposition method comprises tetraethoxysilane and ozone, the flow of described tetraethoxysilane is 500 milli gram/minute～8000 milli gram/minute, the flow of ozone is 5000 standard ml/min～3000 standard ml/min, air pressure is 300 holder～600 holders, and temperature is 400 degrees Celsius～600 degrees Celsius.
Optionally, described deposition gases also comprises: nitrogen, oxygen and helium, the flow of nitrogen is 1000 standard ml/min～10000 standard ml/min, the flow of oxygen is 0 standard ml/min～5000 standard ml/min, and the flow of helium is 5000 standard ml/min～20000 standard ml/min.
Compared with prior art, technical scheme of the present invention has the following advantages:
Form the first insulation liner layer on the opening sidewalls surface that is used to form isolation structure, described the first insulation liner layer is as the transition between insulating barrier and the Semiconductor substrate of follow-up formation; Form the second insulation liner layer in the lower surface of described opening; Because the density of the hydrogen-oxygen key of material surface is determined by the characteristic of material itself, can, by adjusting the kind of material, make the hydrogen-oxygen key density on the second insulation liner layer surface be greater than the hydrogen-oxygen key density on described the first insulation liner layer surface; Because described hydrogen-oxygen key density is larger, the speed of follow-up formation insulating barrier is faster, therefore the speed of open bottom formation insulating barrier is greater than the speed of opening sidewalls formation insulating barrier, can suppress open top insulating barrier because forming the too fast problem of closure too early of speed, ensure the interior tight of insulating barrier of opening.The groove isolation construction densification, the quality that form are good, stable performance.
Further, the material of described the first insulation liner layer is silicon nitride, and the material of described the second dielectric substrate layers is silica; Because the characteristic of material itself determines, the hydrogen-oxygen key density of silicon oxide surface is greater than the hydrogen-oxygen key density of silicon nitride surface, the hydrogen-oxygen key density on described the first insulation liner layer surface is more than the hydrogen-oxygen key density on the second insulation liner layer surface, therefore the speed that forms insulating barrier on the second insulation liner layer surface is less than the speed of the first insulation liner layer surface formation insulating barrier, can avoid not filling the closed problem of open top when full at opening, be conducive to form void-free groove isolation construction.
Brief description of the drawings
Fig. 1 to Fig. 3 is the cross-sectional view of the forming process of the groove isolation construction of prior art high-aspect-ratio;
Fig. 4 to Fig. 8 is the cross-sectional view of the forming process of groove isolation construction described in embodiments of the invention;
Fig. 9 is the mechanism schematic diagram that adopts tetraethoxysilane and ozone, forms insulation film with high-aspect-ratio depositing operation.
Embodiment
In the groove isolation construction of the high-aspect-ratio that as stated in the Background Art, prior art forms, easily form space.
Study discovery through the present inventor, adopt high-aspect-ratio technique taking silester and ozone when reacting gas forms silicon oxide film, deposition rate is relevant with the hydrogen-oxygen key density of institute's deposition surface, and in the time that the hydrogen-oxygen key density of institute's deposition surface is higher, deposition rate is faster.In prior art, be used to form the opening sidewalls of insulating barrier identical with the material of lower surface, hydrogen-oxygen key density is close, close in the speed of described opening sidewalls and lower surface cvd silicon oxide film.But reacting gas is the sidewall at contact openings top first easily, the sidewall surfaces of described open top can first capture reacting gas and form silica, causes in the speed of described open top formation silicon oxide film faster compared with open bottom; When the dark wide continuation of described opening increases, for example, while being greater than 10:1, the difficulty that reacting gas arrives open bottom increases, cause open bottom to form the rate reduction of silicon oxide film, the speed of the silicon oxide film of open top formation is simultaneously very fast, therefore still can cause the insulating layer of silicon oxide of open top first closed, and in opening, form space, cause generation space in formed groove isolation construction, described space can reduce isolation effect, or catch electric charge, easily cause formed device performance unstable.
Further study through the present inventor, form the first insulation liner layer on the opening sidewalls surface that is used to form isolation structure, described the first insulation liner layer is as the transition between insulating barrier and the Semiconductor substrate of follow-up formation; Form the second insulation liner layer in the lower surface of described opening; Because the density of the hydrogen-oxygen key of material surface is determined by the characteristic of material itself, can, by adjusting the kind of material, make the hydrogen-oxygen key density on the second insulation liner layer surface be greater than the hydrogen-oxygen key density on described the first insulation liner layer surface; Because described hydrogen-oxygen key density is larger, the speed of follow-up formation insulating barrier is faster, therefore the speed of open bottom formation insulating barrier is greater than the speed of opening sidewalls formation insulating barrier, can suppress open top insulating barrier because forming the too fast problem of closure too early of speed, ensure the interior tight of insulating barrier of opening.The groove isolation construction densification, the quality that form are good, stable performance.
For above-mentioned purpose of the present invention, feature and advantage can more be become apparent, below in conjunction with accompanying drawing, specific embodiments of the invention are described in detail.
Fig. 4 to Fig. 8 is the cross-sectional view of the forming process of the groove isolation construction of the embodiment of the present invention.
Please refer to Fig. 4, Semiconductor substrate 200 is provided, in described Semiconductor substrate 200, there is opening 201.
Described Semiconductor substrate 200 is used to subsequent technique that workbench is provided, and the material of described Semiconductor substrate 200 is silicon, SiGe, carborundum, silicon-on-insulator or III-V compounds of group (such as gallium nitride or GaAs etc.).
The interior follow-up fleet plough groove isolation structure (STI, Shallow Trench Isolation) that is used to form of described opening 201; The formation technique of described opening 201 comprises: form mask layer 202 on Semiconductor substrate 200 surfaces, described mask layer 202 has defined the position of active area of semiconductor device, and exposing Semiconductor substrate 200 surfaces that need to form opening 201, the material of described mask layer 202 is the combination of silica, silicon nitride or silica and silicon nitride; Taking described mask layer 202 as mask, adopt anisotropic dry etch process etching semiconductor substrate, at the interior formation opening 201 of Semiconductor substrate 200.
Along with the characteristic size of semiconductor device continues to dwindle, the integrated level of integrated circuit improves constantly, cause the width dimensions at the groove isolation construction top that dwindles formation constantly to dwindle, and the degree of depth of described groove isolation construction is not answered corresponding reducing, thereby cause the depth-to-width ratio of the opening 201 that is used to form isolation structure constantly to increase, described opening 201 top width are of a size of 30nm～50nm, and the depth-to-width ratio of described opening 201 is greater than 6:1.In the present embodiment, the depth-to-width ratio of described opening 201 is greater than 8:1.
When the depth-to-width ratio of described opening 201 larger, for example, while being greater than 6:1, the follow-up difficulty at described opening 201 interior fill insulants improves, be difficult to fully enter the bottom of opening 201 for the insulating material of filling opening 201, the in the situation that of being easily insulated material closes at described opening 201 tops, in described opening, still having and be not filled full space.
Therefore, the present embodiment is the formation speed near the sidewall surfaces insulation film at opening 201 tops by reduction, and improve the formation speed of opening 201 bottom insulation films, to avoid opening 201 tops closed too early, thereby at the void-free isolation structure of follow-up formation.
Please refer to Fig. 5, form the first insulation liner layer 203 in the sidewall surfaces of described opening 201.
Because the hydrogen-oxygen key density of the speed of follow-up formation insulation film and the sidewall of opening and lower surface is relevant, hydrogen-oxygen key density is higher, and the formation speed of insulation film is higher; And described hydrogen-oxygen key density is relevant with the material self character that described hydrogen-oxygen key depends on; Described the first insulation liner layer 203 is formed at the sidewall surfaces of opening 201, in order to make the follow-up speed that forms insulation film on the first insulation liner layer 203 surfaces form the speed of insulation film lower than opening 201 bottoms, need to make its surperficial hydrogen-oxygen key density of material that the first insulation liner layer 203 adopts lower than follow-up the second insulation liner layer that is formed at opening 201 bottoms, thereby the insulation film that can suppress opening 201 sidewall surfaces forms speed, avoid opening 201 closed and cause having in formed groove isolation construction the problem in space too early.
The formation technique of described the first insulation liner layer 203 is: mask layer 202 surfaces in described Semiconductor substrate 200 and sidewall and the lower surface of opening 201 deposit the first insulation film; Return the first insulation film described in etching, remove the first insulation film that is positioned at semiconductor substrate surface and open bottom surface, form the first insulation liner layer 203.
Described depositing operation is chemical vapor deposition method, can control the thickness of described the first insulation film, and the thickness of the first dielectric substrate layers 203 forming after etching is by described chemical vapor deposition method control.
Described time etching technics is anisotropic dry etch process, for example plasma dry etch process; In described anisotropic dry etch process, the vertical bombardment of etching gas and Semiconductor substrate 200 surfaces, therefore can remove first insulation film on mask layer 202 surfaces and open bottom surface, and the first insulation film that is positioned at opening 201 sidewall surfaces is parallel with the direction of motion of etching gas, therefore be difficult to be bombarded removal, the first insulation film of opening 201 sidewall surfaces is retained.
In the present embodiment, the thickness of described the first insulation liner layer 203 is 20 dust～200 dusts, the material of described the first insulation liner layer 203 is silicon nitride, the hydrogen-oxygen key density that described silicon nitride surface can depend on is lower than the hydrogen-oxygen key density on silica material surface, follow-up at opening 201 lower surface formation silica, can either make the hydrogen-oxygen key density of opening 201 lower surface higher, and the hydrogen-oxygen key density of opening 201 sidewall surfaces is lower, too early closing any opening 201 while being conducive to avoid follow-up formation insulation film.
Please refer to Fig. 6, form the second insulation liner layer 204 in the lower surface of described opening 201.
In the present embodiment, because the material of described the first insulation liner layer 203 is silicon nitride, in order to make the hydrogen-oxygen key density of opening 201 lower surface higher than the hydrogen-oxygen key density on the first insulation liner layer 203 surfaces, the material of described the second insulation liner layer 204 is silica.
In the present embodiment, described Semiconductor substrate 200 surfaces have mask layer 202, the sidewall surfaces of described opening 201 has the first insulation liner layer 203, therefore only expose the Semiconductor substrate 200 of the bottom of described opening 201, therefore described the second insulation liner layer 204 can adopt thermal oxidation technology to form; The thickness of described the second insulation liner layer 204 is 20 dust～200 dusts.
Described the first insulation liner layer 203 and the second insulation liner layer 204 can be served as the transition between Semiconductor substrate 200 and the insulating barrier of follow-up formation, make the bond quality between insulating barrier and the Semiconductor substrate 200 of follow-up formation better, reduce the defect between insulating barrier and Semiconductor substrate 200 contact interfaces, improve the stability of the semiconductor device forming.
In one embodiment, after described the second insulation liner layer 204 of described formation, carry out thermal anneal process, the parameter of described thermal anneal process is: temperature is 500 degrees Celsius～800 degrees Celsius, and the time is 30 minutes～90 minutes; Described thermal anneal process can be removed the first insulation liner layer 203 and the second insulation liner layer 204, and makes the bond quality between described the first insulation liner layer 203 and the second insulation liner layer 204 and Semiconductor substrate 200 better.
It should be noted that, in other embodiments, the material of described the first insulation liner layer 203 and the second insulation liner layer 204 can be adjusted according to concrete process requirements, only needs the hydrogen-oxygen key density of the material surface that meets the first insulation liner layer 203 lower than described the second insulation liner layer 204.
Please refer to Fig. 7, forming after the first insulation liner layer 203 and the second insulation liner layer 204, carry out process of surface treatment, make the first insulation liner layer 203 and the second insulation liner layer 204 surfaces in described opening there is hydrogen-oxygen key, and the hydrogen-oxygen key density on described the second insulation liner layer 204 surfaces is greater than the hydrogen-oxygen key density on the first insulation liner layer 203 surfaces.
Described process of surface treatment is: temperature is 400 DEG C～550 DEG C, and processing gas is steam (H
2o), the flow of steam is 3000 standard ml/min～6000 standard ml/min, and the flow of carrier gas helium is 5000 standard ml/min～15000 standard ml/min, and air pressure is 2 holder～8 holders, and radio-frequency power is 500 watts～1000 watts.
Described process of surface treatment is used for making described the first insulation liner layer 203 and the second insulation liner layer 204 surfaces with hydrogen-oxygen key; And, 204 of described the first insulation liner layer 203 or the second insulation liner layer with hydrogen-oxygen key density determined by the material behavior of described the first insulation liner layer 203 and the second insulation liner layer 204.
In the present embodiment, the material of described the first insulation liner layer 203 is silicon nitride, the material of described the second insulation liner layer 204 is silica, after process of surface treatment, the hydrogen-oxygen key density on described the second insulation liner layer 204 surfaces is greater than the hydrogen-oxygen key density on the first insulation liner layer 203 surfaces, and the speed that makes described the second insulation liner layer 204 surfaces form insulation film forms the speed of insulation film higher than the first insulation liner layer 203 surfaces; Thereby can avoid the interior formation insulation film of follow-up described opening 201 time, before described opening 201 is not filled completely, described opening 201 is closed too early, and then avoids the formed interior space that produces of groove isolation construction, can make formed performance of semiconductor device more stable.
Please refer to Fig. 8, form and fill full gate mouth 201(as shown in Figure 7 on described mask layer 202, the first insulation liner layer 203 and the second insulation liner layer 204 surfaces) insulation film 205.
It should be noted that, after forming described insulation film 205, adopt insulation film 205 described in CMP (Chemical Mechanical Polishing) process planarization until expose Semiconductor substrate 200 surfaces, form insulating barrier (not shown), described insulating barrier is the groove isolation construction of required formation.
The material of described insulation film 205 is silica, and the formation technique of described insulation film 205 is chemical vapor deposition method; In the present embodiment, adopt high-aspect-ratio depositing operation (HARP) to form described insulation film 205; In the chemical vapor deposition method of described high-aspect-ratio, deposition gases comprises tetraethoxysilane Si(OC
2h
5)
4with ozone O
3, the flow of described tetraethoxysilane is 500 milli gram/minute～8000 milli gram/minute, and the flow of ozone is 5000 standard ml/min～3000 standard ml/min, and air pressure is 300 holder～600 holders, and temperature is 400 degrees Celsius～600 degrees Celsius; In addition, deposition gases also comprises: nitrogen, oxygen and helium, the flow of nitrogen is 1000 standard ml/min～10000 standard ml/min, the flow of oxygen is 0 standard ml/min～5000 standard ml/min, and the flow of helium is 5000 standard ml/min～20000 standard ml/min.In described chemical vapor deposition processes, the hydrogen-oxygen key density that is positioned at opening sidewalls and lower surface is higher, and the speed that forms insulation film 205 is faster, illustrates below with reference to accompanying drawing.
Please refer to Fig. 9, Fig. 9 is the mechanism schematic diagram that adopts tetraethoxysilane and ozone, forms insulation film 205 with high-aspect-ratio depositing operation.
Wherein, as shown in Fig. 9 (a), tetraethoxysilane Si(OC
2h
5)
4one-(OC in molecule
2h
5) key and ozone reaction formation hydrogen-oxygen key-OH; As shown in Figure 9 (b), Si(OC
2h
5)
3(OH) molecule with hydrogen-oxygen key combine with the hydrogen-oxygen key of material surface, form with three-(OC at described material surface
2h
5) silica of key; As shown in Figure 9 (c), silica with-(OC
2h
5) key continues and ozone reaction forms hydrogen-oxygen key, forms the silica with hydrogen-oxygen key, the hydrogen-oxygen bond energy of described silica enough continues and deposition gases molecule forms silica.Therefore, the hydrogen-oxygen key density of material surface is higher, can with the molecular reaction of more deposition gases, form the speed of silica faster.
In the present embodiment, form the first insulation liner layer taking silicon nitride as material on opening sidewalls surface, form the insulation liner layer taking silica as material on open bottom surface; After carrying out process of surface treatment with steam, due to material self character relation, the hydrogen-oxygen key density of the hydrogen-oxygen key density ratio silicon nitride surface of described silicon oxide surface is many, and described hydrogen-oxygen key is more, and the speed that forms the described insulation film taking silica as material is faster; Therefore, form insulation film speed very fast on the second insulation liner layer surface, the speed that forms insulation film on the first insulation liner layer surface is slower; Opening 201 fill full before, can ensure that the top of described opening 201 can be closed, make tight in formed groove isolation construction, quality good, ensured that the performance of semiconductor device forming is stable.
In sum, form the first insulation liner layer on the opening sidewalls surface that is used to form isolation structure, described the first insulation liner layer is as the transition between insulating barrier and the Semiconductor substrate of follow-up formation; Form the second insulation liner layer in the lower surface of described opening; Because the density of the hydrogen-oxygen key of material surface is determined by the characteristic of material itself, can, by adjusting the kind of material, make the hydrogen-oxygen key density on the second insulation liner layer surface be greater than the hydrogen-oxygen key density on described the first insulation liner layer surface; Because described hydrogen-oxygen key density is larger, the speed of follow-up formation insulating barrier is faster, therefore the speed of open bottom formation insulating barrier is greater than the speed of opening sidewalls formation insulating barrier, can suppress open top insulating barrier because forming the too fast problem of closure too early of speed, ensure the interior tight of insulating barrier of opening.The groove isolation construction densification, the quality that form are good, stable performance.
Further, the material of described the first insulation liner layer is silicon nitride, and the material of described the second dielectric substrate layers is silica; Because the characteristic of material itself determines, the hydrogen-oxygen key density of silicon oxide surface is greater than the hydrogen-oxygen key density of silicon nitride surface, the hydrogen-oxygen key density on described the first insulation liner layer surface is more than the hydrogen-oxygen key density on the second insulation liner layer surface, therefore the speed that forms insulating barrier on the second insulation liner layer surface is less than the speed of the first insulation liner layer surface formation insulating barrier, can avoid not filling the closed problem of open top when full at opening, be conducive to form void-free groove isolation construction.
Although the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (13)
1. a formation method for groove isolation construction, is characterized in that, comprising:
Semiconductor substrate is provided, in described Semiconductor substrate, there is opening;
Form the first insulation liner layer in the sidewall surfaces of described opening;
Form the second insulation liner layer in the lower surface of described opening;
After forming the first insulation liner layer and the second insulation liner layer, carry out process of surface treatment, make the first insulation liner layer and the second insulation liner layer surface in described opening there is hydrogen-oxygen key, and the hydrogen-oxygen key density on described the second insulation liner layer surface is greater than the hydrogen-oxygen key density on the first insulation liner layer surface;
After process of surface treatment, the first insulation liner layer in described opening and the second insulation liner layer surface form the insulating barrier of filling full described opening.
2. the formation method of groove isolation construction as claimed in claim 1, is characterized in that, the formation technique of described the first insulation liner layer is: sidewall and lower surface at described semiconductor substrate surface and opening deposit the first insulation film; Return the first insulation film described in etching, remove the first insulation film that is positioned at semiconductor substrate surface and open bottom surface, form the first insulation liner layer.
3. the formation method of groove isolation construction as claimed in claim 2, is characterized in that, described time etching technics is anisotropic dry etch process.
4. the formation method of groove isolation construction as claimed in claim 1, is characterized in that, the material of described the first insulation liner layer is silicon nitride, and the material of described the second insulation liner layer is silica.
5. the formation method of groove isolation construction as claimed in claim 4, is characterized in that, the formation technique of described the second insulation liner layer is thermal oxidation technology.
6. the formation method of groove isolation construction as claimed in claim 5, is characterized in that, after thermal oxidation technology, carry out thermal anneal process, the parameter of described thermal anneal process is: temperature is 500 degrees Celsius～800 degrees Celsius, and the time is 30 minutes～90 minutes.
7. the formation method of groove isolation construction as claimed in claim 1, is characterized in that, described process of surface treatment is: temperature is 400 DEG C～550 DEG C, steam H
2the flow of O is 3000 standard ml/min～6000 standard ml/min, and the flow of carrier gas helium is 5000 standard ml/min～15000 standard ml/min, and air pressure is 2 holder～8 holders, and radio-frequency power is 500 watts～1000 watts.
8. the formation method of groove isolation construction as claimed in claim 1, is characterized in that, the depth-to-width ratio of described opening is greater than 8:1.
9. the formation method of groove isolation construction as claimed in claim 1, it is characterized in that, the formation technique of described opening is: form mask layer at semiconductor substrate surface, described mask layer exposes part semiconductor substrate surface, and the material of described mask layer is silicon nitride; Taking described mask layer as mask etching Semiconductor substrate, form opening, described mask layer is removed after forming insulating barrier.
10. the formation method of groove isolation construction as claimed in claim 1, is characterized in that, the formation technique of described insulating barrier is: form and fill full gate mouth insulation film on described Semiconductor substrate, the first insulation liner layer and the second insulation liner layer surface; Adopt CMP (Chemical Mechanical Polishing) process to remove and be positioned at the insulation film of semiconductor substrate surface, until expose Semiconductor substrate.
The 11. formation methods of groove isolation construction as claimed in claim 10, is characterized in that, the material of described insulation film is silica, and formation technique is chemical vapor deposition method.
The 12. formation methods of groove isolation construction as claimed in claim 11, it is characterized in that, the deposition gases of described chemical vapor deposition method comprises tetraethoxysilane and ozone, the flow of described tetraethoxysilane is 500 milli gram/minute～8000 milli gram/minute, the flow of ozone is 5000 standard ml/min～3000 standard ml/min, air pressure is 300 holder～600 holders, and temperature is 400 degrees Celsius～600 degrees Celsius.
The 13. formation methods of groove isolation construction as claimed in claim 12, it is characterized in that, described deposition gases also comprises: nitrogen, oxygen and helium, the flow of nitrogen is 1000 standard ml/min～10000 standard ml/min, the flow of oxygen is 0 standard ml/min～5000 standard ml/min, and the flow of helium is 5000 standard ml/min～20000 standard ml/min.
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109994537A (en) * | 2017-12-29 | 2019-07-09 | 联华电子股份有限公司 | Semiconductor element and preparation method thereof |
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| US8187948B2 (en) * | 2008-02-18 | 2012-05-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Hybrid gap-fill approach for STI formation |
| CN102104040B (en) * | 2009-12-18 | 2013-01-16 | 和舰科技(苏州)有限公司 | Semiconductor device with shallow-trench isolation structure and manufacturing method thereof |
| TWI424529B (en) * | 2010-10-28 | 2014-01-21 | Macronix Int Co Ltd | Semiconductor structure and manufacturing method of the same |
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| CN109994537B (en) * | 2017-12-29 | 2022-09-06 | 联华电子股份有限公司 | Semiconductor element and manufacturing method thereof |
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