CN111192925A - Trench gate MOSFET power semiconductor device and polysilicon filling method and manufacturing method thereof - Google Patents

Trench gate MOSFET power semiconductor device and polysilicon filling method and manufacturing method thereof Download PDF

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CN111192925A
CN111192925A CN202010015337.5A CN202010015337A CN111192925A CN 111192925 A CN111192925 A CN 111192925A CN 202010015337 A CN202010015337 A CN 202010015337A CN 111192925 A CN111192925 A CN 111192925A
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trench
cavity
insulating layer
width
layer
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CN111192925B (en
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不公告发明人
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Hangzhou Silan Microelectronics Co Ltd
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Hangzhou Silan Microelectronics Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET

Abstract

The application discloses a trench gate MOSFET power semiconductor device and a polysilicon filling method and a manufacturing method thereof. The filling method comprises the following steps: forming a trench in an epitaxial layer on a semiconductor substrate; forming an insulating layer on the surface of the epitaxial layer and in the groove, wherein the insulating layer surrounds the groove to form a first cavity; etching part of the insulating layer on the top of the first cavity to enlarge the opening width of the first cavity and form a second cavity; and filling a polysilicon layer in the second cavity. The polysilicon layer is formed after the opening of the first cavity is enlarged to eliminate the defects of holes or gaps and the like in the polysilicon layer, so that the yield and the reliability of the power semiconductor device can be improved, and the service life of the power semiconductor device can be prolonged.

Description

Trench gate MOSFET power semiconductor device and polysilicon filling method and manufacturing method thereof
Technical Field
The invention relates to the technical field of power semiconductor device manufacturing, in particular to a high-voltage-withstanding trench gate MOSFET power semiconductor device and a polysilicon filling method and a manufacturing method thereof.
Background
A schematic configuration of a prior art power semiconductor device is shown in fig. 1. By way of example, the power semiconductor device is a trench-gate MOSFET power semiconductor device.
As shown in fig. 1, trench-gate MOSFET power semiconductor device 100 includes a plurality of trenches 120 located in epitaxial layer 102 on a semiconductor substrate 101.
Fig. 2a to 2h show cross-sectional views of the method of manufacturing the power semiconductor device shown in fig. 1 at different stages, respectively.
As shown in fig. 2a, a trench 120 having a depth h1 is formed in an epitaxial layer 102 on a semiconductor substrate 101.
The depth of the trenches 120 is different for trench-gate MOSFET power semiconductor devices of different withstand voltage classes. The higher the withstand voltage, the deeper the depth of the trench 120 is in general. For example, for devices with a withstand voltage of 120V or more, the depth of the trench 120 is typically 5 μm or more.
As shown in fig. 2b, an insulating layer 121 is formed on the surface of the epitaxial layer 102 and in the trenches 120.
The insulating layer 121 is composed of, for example, an oxide, and a process for forming the insulating layer 121 includes thermal oxidation or chemical vapor deposition CVD, or a combination of both processes.
The insulating layer 121 serves as an isolation layer between the shield conductor and the epitaxial layer in the power semiconductor device. An insulating layer 121 covers the sidewalls and bottom of trench 120 and extends over the surface of epitaxial layer 102. After the inside of the trench 120 is filled with the insulating layer 121, a cavity 151 is formed.
The thickness of the insulating layer 121 is also different for trench-gate power semiconductor devices of different withstand voltage classes. In general, the higher the withstand voltage, the thicker the thickness of the insulating layer 121. For example, for a device with a withstand voltage of 120V or more, the thickness of the insulating layer 121 is 0.6 μm or more.
As shown in fig. 2c, a polysilicon layer 122 is deposited on the surface of the epitaxial layer 102 and the insulating layer 121 within the trench.
Polysilicon layer 122 is not only formed to fill cavities 151 in trenches 120, but also extends over the surface of epitaxial layer 102. In an ideal power semiconductor device, the polysilicon layer 122 should be densely filled in the cavity 151 without defects such as voids or seams. Polysilicon layer 122 is used in the final device to form shield conductors.
For devices with a withstand voltage of 120V or less, the depth of the trench 120 is, for example, less than 5 micrometers, and the thickness of the insulating layer 121 is, for example, less than 0.6 micrometers. Since the trench depth is shallow and the insulating layer thickness is thin, the opening of the trench 120 can be chamfered to enlarge the width of the cavity opening after the insulating layer is formed, thereby facilitating the filling of the polysilicon layer 122 without affecting parameters and performance.
For devices with withstand voltage above 120V, the depth of the trench 120 is, for example, greater than 5 microns, and the thickness of the insulating layer 121 is, for example, greater than 0.6 microns. Since the trench depth is deep and the insulating layer is thick, even if the opening of the trench 120 is chamfered to enlarge the opening width of the cavity after the insulating layer is formed, the polysilicon layer 122 still has defects such as voids or gaps.
Fig. 2d to fig. 2h show the formation processes of the gate dielectric 125, the gate conductor 106, the body region 107, the source region 108, the interlayer dielectric layer 110, the contact regions 111 to 113, the conductive channels 131 to 133, the source electrode 141, the gate electrode 142, the shielding electrode 143, and the drain electrode 144 in the power semiconductor device shown in fig. 1, which are not described herein again because these are conventional processes.
Fig. 3a and 3b show a cross-sectional view and a partially enlarged view, respectively, of the power semiconductor device shown in fig. 1 after forming a polysilicon layer, in which a void or gap in the polysilicon layer is shown, and an insulating layer 121 is formed in the trench 120, and the width a of the opening of the cavity surrounded by the insulating layer 121 is smaller than the width b inside the cavity. This is due to the fact that with the thermal oxidation scheme, the oxide growth rate is slightly higher at the interface near the epitaxial layer, and the thickness is thicker. When the chemical vapor deposition CVD scheme is adopted, the deposited oxide layer at the groove opening part of the groove is thicker. For the trench after depositing the oxide layer, the trench has a trench shape such that the width of the cavity opening is smaller than the width of the cavity inside, and in the subsequent shield conductor deposition groove filling process, due to the shape retention of the shield conductor CVD, when the polysilicon layer 122 is further filled, even if the cavity is not filled, the polysilicon layer 122 closes the cavity opening, so that a void or gap 152 and other defects appear in the polysilicon layer 122, which finally results in the reduction of leakage current and withstand voltage in the power semiconductor device 100, and the reliability is deteriorated.
The presence of voids or gap defects in the shield conductor leads to breakdown or short-circuit failures of the power semiconductor device, which adversely affects the yield, reliability and lifetime of the power semiconductor device.
Disclosure of Invention
In view of the above problems, it is an object of the present invention to provide a trench-gate MOSFET power semiconductor device, a polysilicon filling method and a manufacturing method thereof, by forming a mask layer in a first cavity in a trench of the semiconductor device, and then etching a portion of an insulating layer at a top opening of the first cavity to enlarge an opening of the first cavity; and then depositing a polycrystalline silicon layer to realize polycrystalline filling of the defects such as no gap, hollow and the like, thereby forming a shielding conductor and solving the problem that the defects such as the hollow or the gap exist in the shielding conductor of the trench in the trench gate MOSFET power device.
According to an aspect of the invention, a polysilicon filling method for a trench gate MOSFET power semiconductor device is provided, which comprises the following steps: a) forming an epitaxial layer on a semiconductor substrate, and forming a groove in the epitaxial layer; b) forming an insulating layer on the surface of the epitaxial layer and in the groove, wherein the insulating layer surrounds the groove to form a first cavity; c) etching part of the insulating layer on the top of the first cavity to enlarge the opening width of the first cavity and form a second cavity; d) and filling a polysilicon layer in the second cavity.
Preferably, step c) comprises: forming a mask layer on the surface of the insulating layer and in the first cavity; etching back the mask layer above the first cavity and on the surface of the insulating layer to form a third cavity, wherein a window with the width larger than the opening width of the third cavity is formed on the mask layer on the surface of the insulating layer; and etching a part of the insulating layer above the third cavity by taking the mask layer as a mask so as to enlarge the opening width of the third cavity, wherein the third cavity is a part of the first cavity.
Preferably, the width of the trench is 1 to 5 micrometers and the depth of the trench is 5 to 12 micrometers.
Preferably, the width of the trench is 1 to 3 micrometers and the depth of the trench is 7 to 12 micrometers.
Preferably, the thickness of the insulating layer is 0.1 to 2 micrometers.
Preferably, the thickness of the insulating layer is 0.6 to 1.5 micrometers.
Preferably, the thickness of the insulating layer at the opening of the trench before step c) is greater than the thickness of the insulating layer inside the trench.
Preferably, the width between the sidewalls of the insulating layers at the opening of the trench before step c) is smaller than the maximum width between the sidewalls of the insulating layers inside the trench.
Preferably, the maximum width between the side walls of the insulating layer inside the trench minus the width between the side walls of the insulating layer at the opening of the trench before step c) is greater than or equal to 30 nm.
Preferably, the width W4 between the side walls of the insulating layer at the opening of the trench after the step c) minus the width W3 between the side walls of the insulating layer inside the trench satisfies-30 nm ≦ W4-W3 ≦ 300 nm.
Preferably, the width W4 between the side walls of the insulating layers at the opening of the groove after the step c) minus the width W3 between the side walls of the insulating layers inside the groove satisfies 0 ≦ W4-W3 ≦ 300 nm.
Preferably, the opening width of the first cavity is smaller than the inner width of the first cavity.
Preferably, the value of the inner width of the first cavity minus the value of the opening width of the first cavity is greater than or equal to 30 nanometers.
Preferably, the value of the opening width of the second cavity minus the value of the opening width of the first cavity is greater than or equal to 30 nanometers and less than or equal to 300 nanometers.
Preferably, the value of the opening width of the second cavity minus the value of the internal width of the second cavity is greater than or equal to minus 30 nanometers and less than or equal to 300 nanometers.
Preferably, the value of the opening width of the second cavity minus the value of the internal width of the second cavity is greater than or equal to 0 and less than or equal to 300 nanometers.
Preferably, the etching depth of the mask layer is in the range of 0.5 to 11 μm.
Preferably, the mask layer is etched back, and a part of the insulating layer on the surface of the epitaxial layer and a part of the insulating layer in the trench are exposed.
Preferably, the mask layer includes a dielectric layer or a glue layer.
According to another aspect of the present invention, there is provided a method of manufacturing a trench-gate MOSFET power semiconductor device, comprising: a) forming an epitaxial layer on a semiconductor substrate, and forming a groove in the epitaxial layer; b) forming an insulating layer on the surface of the epitaxial layer and in the groove, wherein the insulating layer surrounds the groove to form a first cavity; c) etching part of the insulating layer on the top of the first cavity to enlarge the opening width of the first cavity and form a second cavity; d) filling a polysilicon layer in the second cavity, wherein the polysilicon layer is used for forming a shielding conductor; e) removing the polycrystalline silicon layer and the insulating layer on the surface of the epitaxial layer and the top of the groove; f) etching back the insulating layer in the trench to form an upper cavity exposing upper sidewalls of the trench and the shield conductor; g) forming a gate dielectric on upper sidewalls of the trench and the shield conductor; h) forming a gate conductor in an upper cavity surrounded by the gate dielectric and insulating layer; i) forming a body region of a second doping type in a region, adjacent to the trench, of the epitaxial layer, wherein the semiconductor substrate is of the first doping type and serves as a drain region, the epitaxial layer is of the first doping type, and the second doping type is opposite to the first doping type; j) forming a source region of the first doping type in the body region; and k) forming electrical connection structures for the gate conductor, the shield conductor, the source region and the drain region.
Preferably, step c) comprises: forming a mask layer on the surface of the insulating layer and in the first cavity; etching back the mask layer above the first cavity and on the surface of the insulating layer to form a third cavity, wherein a window with the width larger than the opening width of the third cavity is formed on the mask layer on the surface of the insulating layer; and etching a part of the insulating layer above the third cavity by taking the mask layer as a mask so as to enlarge the opening width of the third cavity, wherein the third cavity is a part of the first cavity.
Preferably, the width of the trench is 1 to 5 micrometers and the depth of the trench is 5 to 12 micrometers.
Preferably, the width of the trench is 1 to 3 micrometers and the depth of the trench is 7 to 12 micrometers.
Preferably, the thickness of the insulating layer at the surface of the epitaxial layer is 0.1 to 2 μm.
Preferably, the thickness of the insulating layer at the surface of the epitaxial layer is 0.6 to 1.5 micrometers.
Preferably, the thickness of the insulating layer at the opening of the trench before step c) is greater than the thickness of the insulating layer inside the trench.
Preferably, the width between the sidewalls of the insulating layers at the opening of the trench before step c) is smaller than the maximum width between the sidewalls of the insulating layers inside the trench.
Preferably, the maximum width between the side walls of the insulating layers inside the trench minus the width between the side walls of the insulating layers at the opening of the trench before step c) is greater than or equal to 30 nanometers.
Preferably, the width W4 between the side walls of the insulating layers at the opening of the groove after the step c) minus the width W3 between the side walls of the insulating layers inside the groove meets the conditions that W4 is less than or equal to-30 nanometers and W3 is less than or equal to 300 nanometers.
Preferably, the width W4 between the side walls of the insulating layers at the opening of the groove after the step c) minus the width W3 between the side walls of the insulating layers inside the groove satisfies 0 ≦ W4-W3 ≦ 300 nm.
Preferably, the opening width of the first cavity is smaller than the inner width of the first cavity.
Preferably, the value of the inner width of the first cavity minus the value of the opening width of the first cavity is greater than or equal to 30 nanometers.
Preferably, the value of the opening width of the second cavity minus the value of the opening width of the first cavity is greater than or equal to 30 nanometers and less than or equal to 300 nanometers.
Preferably, a value obtained by subtracting the maximum width of the interior of the second cavity from the opening width value of the second cavity satisfies a range of minus 30 nm or more and 300 nm or less.
Preferably, a value obtained by subtracting the maximum width of the interior of the second cavity from the opening width of the second cavity is equal to or greater than 300 nm.
Preferably, the withstand voltage of the trench gate MOSFET power semiconductor device is 120V to 300V.
Preferably, the mask layer is etched back by wet etching.
Preferably, the etching depth range of the etching back of the mask layer is 0.5 to 11 micrometers.
Preferably, the mask layer is etched back to expose a part of the insulating layer on the surface of the epitaxial layer and a part of the insulating layer in the trench.
Preferably, the mask layer includes a dielectric layer or a glue layer.
According to still another aspect of the present invention, there is provided a trench gate MOSFET power semiconductor device formed by the above manufacturing method, including: the semiconductor substrate is used as a drain region; an epitaxial layer on the semiconductor substrate; a trench in the epitaxial layer; an insulating layer in the trench, the insulating layer forming a cavity around the trench; the polycrystalline silicon layer fills the shielding conductor formed by the cavity; a gate dielectric and a gate conductor located on top of the insulating layer in the trench, the gate dielectric located on top sidewalls of the trench and the shield conductor, the gate conductor located between the gate dielectrics; the body region and the source region are positioned in the region, adjacent to the groove, of the epitaxial layer, and the doping types of the body region and the source region are opposite; and an electrical connection structure of the gate conductor, the shield conductor, the source region and the drain region.
Preferably, the width of the trench is 1 to 5 micrometers and the depth of the trench is 5 to 12 micrometers.
Preferably, the width of the trench is 1 to 3 micrometers and the depth of the trench is 7 to 12 micrometers.
Preferably, the thickness of the insulating layer is 0.1 to 2 micrometers.
Preferably, the thickness of the insulating layer is 0.6 to 1.5 micrometers.
Preferably, the width W3 of the side walls of the insulating layers in the groove opening subtracted from the width W4 of the side walls of the insulating layers in the groove opening is-30 nanometers ≤ W4-W3 ≤ 300 nanometers.
Preferably, the width W4 between the insulating layer side walls at the opening of the groove minus the width W3 between the insulating layer side walls inside the groove satisfies 0 nm ≦ W4-W3 ≦ 300 nm.
Preferably, the voltage endurance of the trench gate MOSFET power semiconductor device is 120V to 300V.
Preferably, the electrical connection structure includes a plurality of electrodes respectively connected to the gate conductor, the shield conductor, the source region and the drain region.
Preferably, the electrical connection structure further includes a plurality of conductive channels, the gate conductor, the shield conductor, and the source region are connected to the respective electrodes via the respective conductive channels, and the drain region is in contact with the respective electrodes.
According to the manufacturing method of the trench gate MOSFET power semiconductor device, the mask layer is formed in the first cavity in the trench of the semiconductor device, and then the partial insulating layer at the opening at the top of the first cavity is etched to expand the opening of the first cavity; and then depositing a polycrystalline silicon layer to realize polycrystalline filling of the defects such as no gap, hollow and the like, thereby forming a shielding conductor, solving the problem that the defects such as the hollow or the gap exist in the shielding conductor in the groove in the trench gate MOSFET power semiconductor device, and solving the problem that the hollow or the gap defect exists in the shielding conductor finally caused by the small cavity formed after the trench is covered by the thicker insulating layer in the process of manufacturing the shielding conductor when the trench gate MOSFET power semiconductor device has high withstand voltage, deeper depth of the trench and thicker insulating layer in the trench.
By adopting the technology of the invention, the defects of holes or gaps and the like in the shielding conductor of the device can be reduced, thereby improving the yield and reliability of the power semiconductor device and prolonging the service life. The invention can be applied to a trench gate MOSFET power semiconductor device with the withstand voltage of below 120V, the width of the trench of 1-5 microns, the depth of the trench of 5-12 microns and the thickness of the insulating layer of 0.1-2 microns, and can also be applied to a trench gate MOSFET power semiconductor device with the withstand voltage of above 120V, such as 120V-300V, the width of the trench of 1-3 microns, the depth of the trench of 7-12 microns and the thickness of the insulating layer of 0.6-1.5 microns.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:
fig. 1 shows a schematic block diagram of a power semiconductor device according to the prior art.
Fig. 2a to 2h show cross-sectional views of the method of manufacturing the power semiconductor device shown in fig. 1 at different stages, respectively.
Fig. 3a and 3b show a cross-sectional view and a partially enlarged view, respectively, of the power semiconductor device shown in fig. 1 after forming a polysilicon layer, in which voids or seams in the polysilicon layer are shown.
Fig. 4 shows a flowchart of a method of manufacturing a power semiconductor device according to a first embodiment of the present invention.
Fig. 5a to 5j show cross-sectional views of a method of manufacturing a power semiconductor device according to a first embodiment of the present invention at different stages, respectively.
Detailed Description
The invention will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by like reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale. In addition, certain well known components may not be shown. For simplicity, the semiconductor structure obtained after several steps can be described in one figure.
It will be understood that when a layer or region is referred to as being "on" or "over" another layer or region in describing the structure of the device, it can be directly on the other layer or region or intervening layers or regions may also be present. And, if the device is turned over, that layer, region, or regions would be "under" or "beneath" another layer, region, or regions.
If for the purpose of describing the situation directly above another layer, another region, the expression "a directly above B" or "a above and adjacent to B" will be used herein. In the present application, "a is directly in B" means that a is in B and a is adjacent to B, but not a is in a doped region formed in B.
In the present application, the term "semiconductor structure" refers to the general term for the entire semiconductor structure formed in the various steps of manufacturing a semiconductor device, including all layers or regions that have been formed.
In the following description, numerous specific details of the invention, such as structure, materials, dimensions, processing techniques and techniques of the devices are described in order to provide a more thorough understanding of the invention. However, as will be understood by those skilled in the art, the present invention may be practiced without these specific details.
Unless otherwise specified below, various portions of the semiconductor device may be composed of materials well known to those skilled in the art. Semiconductor materials include, for example, group III-V semiconductors such as GaAs, InP, GaN, SiC, and group IV semiconductors such as Si, Ge.
Fig. 3a and 3b show a cross-sectional view and a partially enlarged view, respectively, of the power semiconductor device shown in fig. 1 after forming a polysilicon layer, in which voids or seams in the polysilicon layer are shown.
In the above method of forming the power semiconductor device 100, the epitaxial layer 102 is formed on the semiconductor substrate 101, the trench 120 is formed in the epitaxial layer 102, the insulating layer 121 is formed in the trench 120 and the cavity 151 surrounded by the insulating layer 121 is formed, and the cavity 151 is filled with the polysilicon layer 122. The opening width of the cavity 151 surrounded by the insulating layer 121 formed in the trench 120 is smaller than the inner width. This is due to the non-uniform thickness of the insulating layer 121 on the sidewalls of the trench 120.
When a thermal oxidation scheme is used, the oxidation growth rate at the interface near the surface of epitaxial layer 102 is slightly higher, and the thickness of insulating layer 121 at the opening of trench 120 is greater than the thickness inside trench 120. When the chemical vapor deposition polycrystal is used, the deposition rate near the surface of the epitaxial layer 102 is slightly higher, and the thickness of the insulating layer 121 at the opening of the trench 120 is still larger than that of the inside of the trench 120.
In the case where the width of the opening of the cavity surrounded by the insulating layer 121 is smaller than the width of the inside of the cavity, if the polysilicon layer 122 is formed by chemical vapor deposition, the conformality of the polysilicon layer may easily cause defects such as voids or gaps 152 in the polysilicon layer.
For devices with a withstand voltage of 120V or less, the depth of the trench 120 is, for example, less than 5 micrometers, and the thickness of the insulating layer 121 is, for example, less than 0.6 micrometers. Since the trench depth is shallow and the insulating layer thickness is thin, the opening of the trench 120 can be chamfered to enlarge the width of the cavity opening after the insulating layer is formed, thereby facilitating the filling of the polysilicon layer 122 without affecting parameters and performance.
For devices with withstand voltage above 120V, the depth of the trench 120 is, for example, greater than 5 microns, and the thickness of the insulating layer 121 is, for example, greater than 0.6 microns. Since the trench depth is deep and the insulating layer is thick, even if the opening of the trench 120 is chamfered to enlarge the opening width of the cavity after the insulating layer is formed, the polysilicon layer 122 still has defects such as voids or gaps.
As shown in fig. 3a and 3b, an insulating layer 121 is formed in the trench 120, and a cavity opening width a surrounded by the insulating layer 121 is smaller than a cavity inner width b. When the polysilicon layer 122 is further formed, even if the cavity is not filled with the polysilicon layer 122, the opening of the cavity is closed by the polysilicon layer 122, so that the material of the polysilicon layer 122 cannot enter the cavity, and thus, a void or a gap 152 occurs in the polysilicon layer 122, which results in a reduction in leakage current and withstand voltage and a deterioration in reliability in the final power semiconductor device 100.
Defects in the polysilicon layer cause breakdown or short-circuit failures of the power semiconductor device, which adversely affects the yield, reliability and lifetime of the power semiconductor device.
Fig. 4 shows a flowchart of a method of manufacturing a power semiconductor device according to a first embodiment of the present invention.
Fig. 5a to 5j show cross-sectional views of a method of manufacturing a power semiconductor device according to a first embodiment of the present invention at different stages, respectively.
In step S01, trenches 220 having a width w1 and a depth h3 are formed in the epitaxial layer 202 on the semiconductor substrate 201, as shown in fig. 5 a.
The semiconductor substrate 201 is also used as a drain region of the final device, the material is, for example, a monocrystalline silicon substrate doped to N type, an epitaxial layer 202 is further formed on the semiconductor substrate 201, and the trench 220 is located in the epitaxial layer 202. The process for forming the trench 220 is, for example, a patterning process including photolithography and etching. For example, a resist mask including an opening pattern of the trench 220 is formed using photolithography, and a portion of the epitaxial layer 202 exposed through the opening is selectively removed using etching.
The depth of the trenches 220 is different for trench-gate power semiconductor devices of different withstand voltage classes. The higher the withstand voltage, the deeper the depth of the trench 220 is. For example, for devices with withstand voltage of 120V or more, the depth of the trench 220 is typically 5 μm or more. In this embodiment, the width w1 of the trench 220 is, for example, 1 to 5 microns and the depth is, for example, 5 to 12 microns, and the width w1 of the trench 220 is, for example, 1 to 3 microns and the depth is, for example, 7 to 12 microns.
In step S02, an insulating layer 221 is formed on the surface of epitaxial layer 202 and in trenches 220, as shown in fig. 5 b.
The insulating layer 221 is composed of, for example, oxide. The process for forming the insulating layer 221 includes thermal oxidation or chemical vapor deposition CVD, or a combination of both processes. The thermal oxidation includes hydrothermal oxidation (HTO) or Selective Reactive Oxidation (SRO), and the Chemical Vapor Deposition (CVD) includes Low Pressure Chemical Vapor Deposition (LPCVD) or sub-atmospheric pressure chemical vapor deposition (SACVD).
The insulating layer 221 serves as an isolation layer between the shield conductor and the epitaxial layer 202 in the power semiconductor device. Insulating layer 221 covers the sidewalls and bottom of trench 220 and extends above the surface of epitaxial layer 202, and cavity 251 is formed after the interior of trench 220 is filled with insulating layer 221.
The thickness of the insulating layer 221 is also different for trench-gate power semiconductor devices of different withstand voltage classes. In general, the higher the withstand voltage, the thicker the thickness of the insulating layer 221. For example, for a device having a withstand voltage of 120V or more, the thickness of the insulating layer 221 needs to be 0.6 μm or more. In the embodiment, the thickness t1 of the insulating layer 221 is 0.1 to 2 microns, and the thickness t1 of the insulating layer 221 can be 0.6 to 1.5 microns. The opening width w2 of the cavity 251 surrounded by the insulating layer 221 is smaller than the inner width w3, i.e. w2< w 3.
If the value obtained by subtracting the opening width w2 of the cavity 251 from the internal width w3 of the cavity 251 surrounded by the insulating layer 221 is 30 nm or more, defects such as voids or gaps are likely to occur in the subsequent shield conductor.
The present invention is adapted to the case where the opening width w2 of the cavity 251 surrounded by the insulating layer 221 is smaller than the inner width w3 by a predetermined difference, but there is no limitation on the shape of the cavity 251. For example, the shape of the cavity 251 is, for example, a shape in which the opening and the bottom are small in width and the middle is large in width, or a shape in which the opening is small in width and the middle is large in width and the bottom is large in width. The cavity 251 may be of any shape, and may even be irregularly shaped.
In step S03, a mask layer 222 is formed on the surface of the insulating layer 221 and in the cavity 251, and etching is performed to expose the insulating layer 221 in the region with the narrower width at the top of the trench, as shown in fig. 5 c.
In this substep, masking layer 222 comprises, for example, a dielectric layer or a glue layer. When a dielectric layer is used to fill the cavity 251, CVD may be used, including LPCVD or SACVD. The dielectric layer is usually made of one or more of polycrystal, silicon nitride and silicon oxynitride. Either a positive or negative photoresist may be selected when filled with a glue layer.
In this sub-step, the insulating layer 221 having a narrow width at the top of the trench is exposed by photolithography and etching, and a cavity 252 is formed. The step usually adopts anisotropic dry etching, and the width W4 of the opening exposed by the insulating layer 221 in the narrow width region at the top of the trench is greater than the width W2 of the opening of the cavity 251, for example, the difference between the two is more than 30 nm and less than 300 nm, that is, 30 nm ≦ W4-W2 ≦ 300 nm.
The distance between the bottom of the cavity 252 and the surface of the epitaxial layer 202 is h4, the range of h4 is determined according to the deposition condition of the insulating layer 221 in the notch, for example, the depth of h4 is 0.5-11 um.
In step S04, the insulating layer in the narrow width region at the top of the trench is etched, and the mask layer 222 on the surface of the epitaxial layer 202 and the insulating layer 221 in the trench is removed to form a cavity 253, as shown in fig. 5 d.
In the sub-step, the mask layer 222 has a window with a width larger than the opening width of the cavity 251 at a position corresponding to the opening portion of the cavity 251, the insulating layer in the region with a narrower width at the top of the trench, that is, the insulating layer at the top of the cavity 252 is etched through the mask layer 222 to enlarge the opening of the cavity 252, usually, anisotropic dry etching is adopted, and the width W4 of the enlarged opening of the cavity 252 and the width W2 of the opening of the cavity 251 satisfy the condition of 30 nm ≦ W4-W2 ≦ 300 nm.
In this sub-step, the mask layer 222 on the surface of the epitaxial layer 202 and the insulating layer 221 in the trench 220 is removed, and the insulating layer 221 in the surface of the epitaxial layer 202 and the trench 220 is remained to form the cavity 253, usually by a wet process. The opening width of the cavity 253 is W4 as well as the opening width of the cavity, the internal width is W3, and the opening width W4 and the internal width W3 meet the conditions that the size is-30 nm and W4-W3 and 300 nm or 0 nm and W4-W3 and 300 nm. Meanwhile, the width W4 of the opening of the cavity 253 and the width W2 of the opening of the cavity 251 meet the condition that the width W4-W2 are more than or equal to 30 nanometers and less than or equal to 300 nanometers.
In step S05, filling of the polysilicon layer 223 is performed, as shown in fig. 5 e. The polysilicon layer 223 is deposited at a temperature of, for example, 500 to 580 degrees, a sheet resistance of 3 to 20 ohms, and a thickness of 50 to 2000 nanometers. Because the width W4 of the notch of the cavity 253 meets the requirements that-30 nm is not less than W4-W3 is not less than 300 nm or 0 nm is not less than W4-W3 is not more than 300 nm, the filled polycrystalline silicon layer is not easy to generate defects such as gaps, holes and the like. Polysilicon layer 223 is used to form shield conductors.
In step S06, the polysilicon layer 223 and the insulating layer 221 on the surface of the epitaxial layer 202 and on the top of the trench 220 are removed, for example, by Chemical Mechanical Planarization (CMP), and the portions of the polysilicon layer 223 and the insulating layer 221 above the surface of the epitaxial layer 202 are removed, as shown in fig. 5 f.
In this step, the portions of the polysilicon layer 223 and the insulating layer 221 located in the trenches 220 remain, and the top ends are flush with the surface of the epitaxial layer 202.
In step S07, the insulating layer 221 in the trench 220 is etched back to form an upper cavity 254, for example, using a selective wet etch, as shown in fig. 5 g.
In this step, the portion of the insulating layer 221 located above the trench 220 is removed, forming an upper cavity 254. The upper sidewalls of the trench 220 and the upper sidewalls of the shield conductors are exposed in the upper cavity 254. The etching depth of the insulating layer 221 is h5, and the range is 0.4 to 2 micrometers according to the parameter requirements of a product threshold value, capacitance and the like.
In step S08, the gate dielectric 225 and the gate conductor 206 are formed in the upper cavity 254 of the trench 220, as shown in fig. 5 h.
In this step, an oxide layer is grown, for example using thermal oxidation, on the surface of epitaxial layer 202, on the upper sidewalls of trenches 220, and on the upper sidewalls of the shield conductor to form a gate dielectric 225. A gate conductor 206 is then deposited. Gate conductor 206 not only fills cavity 254 above trench 220, but also extends above the surface of epitaxial layer 202. For example, using chemical mechanical planarization, the portions of the gate conductor 206 and gate dielectric 225 that are above the surface of the epitaxial layer 202 are removed, leaving the surface of the epitaxial layer 202 re-exposed and the tops of the gate conductor 206 and gate dielectric 225 flush with the surface of the epitaxial layer 202.
In step S09, a body region 207 of P-type is formed in epitaxial layer 202, and a source region 208 of N-type is formed in body region 207, as shown in fig. 5 i.
The process for forming the body region 207 and the source region 208 is, for example, multiple ion implantations. Different types of doped regions are formed by selecting appropriate dopants and then thermally annealing to activate the impurities. In the ion implantation, the lateral positions of body region 207 and source region 208 may be defined using shield conductor and gate conductor 206 as hard masks, so that the photoresist mask may be omitted.
In step S10, an electrical connection structure of the gate conductor 206, the shield conductor, the source region 208 and the drain region is formed, thereby forming the power semiconductor device 200, as shown in fig. 5 j.
In this step, a contact region 211 is formed adjacent to and below source region 208, a contact region 212 is formed in gate conductor 206, and a contact region 213 is formed in the shield conductor. An interlevel dielectric layer 210 is located on the surface of the epitaxial layer 202. Further, conductive vias 231 through 233 are formed through the interlevel dielectric layer 210. Conductive via 231 extends down through source region 208 to contact region 211, conductive via 232 extends down into gate conductor 206 to contact region 212, and conductive via 233 extends down into the shield conductor to contact region 213. Further, a source electrode 241, a gate electrode 242, and a shield electrode 243 are formed on the surface of the interlayer dielectric layer 210 at positions corresponding to the conductive vias 231 to 233, respectively, to provide electrical connection paths to the source region 208, the gate conductor 206, and the shield conductor, respectively, thereby completing the front structure of the power semiconductor device 200.
After the front structure of the power semiconductor device 200 is completed, the drain 244 contacting the drain region is formed on the back surface of the power semiconductor device 200, and since the semiconductor substrate 201 is used as the drain region, the drain 244 directly contacts the semiconductor substrate 201 without a conductive channel.
And a series of subsequent processes such as thinning the back surface, forming a source electrode 241, a gate electrode 242, a shielding electrode 243, a drain electrode 244 on the front surface and the back surface respectively, scribing and the like are performed to complete the complete structure of the power semiconductor device.
In the power semiconductor device 200 according to an embodiment of the present invention, at least a portion of the body region 207 is adjacent to an upper portion of the trench 220. A first portion of the gate dielectric 225 is located on the upper sidewalls of the trench 220, a second portion is located between the gate conductor 206 and the shield conductor, an insulating layer 221 is located on the lower sidewalls of the trench 220, and the first and second portions of the gate dielectric 225 abut the insulating layer 221. Gate conductor 206 is located in an upper portion of trench 220 and is separated from body region 207 in epitaxial layer 202 by a first portion of gate dielectric 225. The shield conductor extends from the upper portion to the lower portion of the trench 220 and is separated from the gate conductor 206 by a second portion of the gate dielectric 225 and from the epitaxial layer 202 by an insulating layer 221.
In the above-described embodiments, it was described that the shield conductor of the split-gate type power semiconductor device is formed of a polysilicon layer deposited after etching the trench opening. However, the present invention is not limited thereto, but may be applied to any type of trench type power semiconductor device. For example, in a trench type power semiconductor device, a polysilicon layer and an insulating layer form a gate conductor and a gate dielectric, respectively, and after forming the polysilicon layer, further include: forming a body region of the second doping type in a region of the epitaxial layer adjacent to the trench; forming a source region of a first doping type in the body region, wherein the second doping type is opposite to the first doping type; and forming an electrical connection structure of the gate conductor and the source region. The gate conductor extends from an upper portion of the trench to a lower portion of the trench and is separated from the body region by a gate dielectric.
In the above embodiment, since the opening width of the cavity surrounded by the insulating layer is smaller than the inner width due to the uneven thickness of the insulating layer on the sidewall of the trench, polycrystalline filling without defects such as a gap, a void, and the like is realized by a method of expanding the opening of the cavity and then filling the polycrystalline silicon layer, so as to form the shield conductor, thereby solving the problem that the defects such as a void, a gap, and the like exist in the shield conductor in the trench gate MOSFET power semiconductor device. However, the present invention is not limited thereto, but may be applied to a trench type power semiconductor device using any conductor as a gate conductor or a shield conductor.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
In accordance with the present invention, as set forth above, these embodiments are not intended to be exhaustive or to limit the invention to the precise embodiments disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated. The invention is limited only by the claims and their full scope and equivalents.

Claims (50)

1. A polysilicon filling method for a trench gate MOSFET power semiconductor device is characterized by comprising the following steps:
a) forming an epitaxial layer on a semiconductor substrate, and forming a groove in the epitaxial layer;
b) forming an insulating layer on the surface of the epitaxial layer and in the groove, wherein the insulating layer surrounds the groove to form a first cavity;
c) etching part of the insulating layer on the top of the first cavity to enlarge the opening width of the first cavity and form a second cavity;
d) and filling a polysilicon layer in the second cavity.
2. The polysilicon filling method as claimed in claim 1, the step c) comprising:
forming a mask layer on the surface of the insulating layer and in the first cavity;
etching back the mask layer above the first cavity and on the surface of the insulating layer to form a third cavity, wherein a window with the width larger than the opening width of the third cavity is formed on the mask layer on the surface of the insulating layer;
etching part of the insulating layer above the third cavity by taking the mask layer as a mask so as to enlarge the opening width of the third cavity,
wherein the third cavity is part of the first cavity.
3. The polysilicon filling method as claimed in claim 1, wherein the width of the trench is 1 to 5 micrometers and the depth of the trench is 5 to 12 micrometers.
4. The polysilicon filling method as claimed in claim 1, wherein the width of the trench is 1 to 3 micrometers and the depth of the trench is 7 to 12 micrometers.
5. The polysilicon filling method as claimed in claim 1, wherein the thickness of the insulating layer is 0.1 to 2 μm.
6. The polysilicon filling method as claimed in claim 1, wherein the thickness of the insulating layer is 0.6 to 1.5 μm.
7. The polysilicon filling method according to claim 1 or 2, wherein the thickness of the insulating layer at the trench opening before step c) is larger than the thickness of the insulating layer inside the trench.
8. The polysilicon filling method according to claim 1 or 2, wherein the width between the insulating layer sidewalls at the opening of the trench before step c) is smaller than the maximum width between the insulating layer sidewalls inside the trench.
9. The polysilicon filling method according to claim 1 or 2, wherein the maximum width between the insulating layer sidewalls inside the trench minus the width between the insulating layer sidewalls at the trench opening before step c) is 30 nm or more.
10. The polysilicon filling method as claimed in claim 1 or 2, wherein the width W4 between the insulating layer sidewalls at the trench opening minus the width W3 between the insulating layer sidewalls inside the trench after step c) satisfies-30 nm ≦ W4-W3 ≦ 300 nm.
11. The polysilicon filling method according to claim 1 or 2, wherein the width W4 between the insulating layer sidewalls at the opening of the trench after step c) minus the width W3 between the insulating layer sidewalls inside the trench satisfies 0 ≦ W4-W3 ≦ 300 nm.
12. The polysilicon filling method as claimed in claim 1, wherein the opening width of the first cavity is smaller than the inner width of the first cavity.
13. The polysilicon filling method as claimed in claim 1, wherein the value of the inner width of the first cavity minus the value of the opening width of the first cavity is equal to or greater than 30 nm.
14. The polysilicon filling method according to claim 1, wherein the value of the opening width of the second cavity minus the value of the opening width of the first cavity is equal to or greater than 30 nm and equal to or less than 300 nm.
15. The polysilicon filling method according to claim 1, wherein a value of an opening width of the second cavity minus a value of an inner width of the second cavity is equal to or greater than minus 30 nm and equal to or less than 300 nm.
16. The polysilicon filling method as claimed in claim 1, wherein the value of the opening width of the second cavity minus the value of the inner width of the second cavity is equal to or greater than 0 and equal to or less than 300 nm.
17. The polysilicon filling method according to any one of claims 2 to 6, wherein the etching depth of the etching back of the mask layer ranges from 0.5 to 11 μm.
18. The polysilicon filling method according to claim 2, wherein the mask layer is etched back to expose a portion of the insulating layer on the surface of the epitaxial layer and a portion of the insulating layer in the trench.
19. The polysilicon filling method according to claim 2, wherein the mask layer comprises a dielectric layer or a glue layer.
20. A method for manufacturing a trench gate MOSFET power semiconductor device comprises the following steps:
a) forming an epitaxial layer on a semiconductor substrate, and forming a groove in the epitaxial layer;
b) forming an insulating layer on the surface of the epitaxial layer and in the groove, wherein the insulating layer surrounds the groove to form a first cavity;
c) etching part of the insulating layer on the top of the first cavity to enlarge the opening width of the first cavity and form a second cavity;
d) filling a polysilicon layer in the second cavity, wherein the polysilicon layer is used for forming a shielding conductor;
e) removing the polycrystalline silicon layer and the insulating layer on the surface of the epitaxial layer and the top of the groove;
f) etching back the insulating layer in the trench to form an upper cavity exposing upper sidewalls of the trench and the shield conductor;
g) forming a gate dielectric on upper sidewalls of the trench and the shield conductor;
h) forming a gate conductor in an upper cavity surrounded by the gate dielectric and insulating layer;
i) forming a body region of a second doping type in a region, adjacent to the trench, of the epitaxial layer, wherein the semiconductor substrate is of the first doping type and serves as a drain region, the epitaxial layer is of the first doping type, and the second doping type is opposite to the first doping type;
j) forming a source region of the first doping type in the body region; and
k) and forming an electrical connection structure of the gate conductor, the shield conductor, the source region and the drain region.
21. The method of manufacturing of claim 20, wherein step c) comprises:
forming a mask layer on the surface of the insulating layer and in the first cavity;
etching back the mask layer above the first cavity and on the surface of the insulating layer to form a third cavity, wherein a window with the width larger than the opening width of the third cavity is formed on the mask layer on the surface of the insulating layer;
etching part of the insulating layer above the third cavity by taking the mask layer as a mask so as to enlarge the opening width of the third cavity,
wherein the third cavity is part of the first cavity.
22. The manufacturing method according to claim 20, wherein the width of the trench is 1 to 5 micrometers and the depth of the trench is 5 to 12 micrometers.
23. The manufacturing method according to claim 20, wherein the width of the trench is 1 to 3 micrometers and the depth of the trench is 7 to 12 micrometers.
24. The method of manufacturing of claim 20, wherein the insulating layer has a thickness of 0.1 to 2 microns at the surface of the epitaxial layer.
25. The method of manufacturing of claim 20, wherein the insulating layer has a thickness of 0.6 to 1.5 microns at the surface of the epitaxial layer.
26. The method of manufacturing of claim 20, wherein a thickness of the insulating layer at the trench opening is greater than a thickness of the insulating layer inside the trench prior to step c).
27. The manufacturing method according to claim 20, wherein a width between the insulating layer sidewalls at the opening of the trench before step c) is smaller than a maximum width between the insulating layer sidewalls inside the trench.
28. The manufacturing method according to claim 20, wherein a maximum width between the insulating layer sidewalls inside the trench minus a width between the insulating layer sidewalls at the opening of the trench before step c) is 30 nm or more.
29. The manufacturing method according to claim 20, wherein a width W4 between the insulating layer sidewalls at the trench opening minus a width W3 between the insulating layer sidewalls inside the trench after step c) satisfies-30 nm ≦ W4-W3 ≦ 300 nm.
30. The manufacturing method according to claim 20, wherein a width W4 between the insulating layer sidewalls at the opening of the trench after step c) minus a width W3 between the insulating layer sidewalls inside the trench satisfies 0 ≦ W4-W3 ≦ 300 nm.
31. The manufacturing method according to claim 20, wherein an opening width of the first cavity is smaller than an inner width of the first cavity.
32. The manufacturing method according to claim 20, wherein a value of an inner width of the first cavity minus a value of an opening width of the first cavity is equal to or greater than 30 nm.
33. The manufacturing method according to claim 20, wherein an opening width value of the second cavity minus an opening width value of the first cavity is equal to or greater than 30 nm and equal to or less than 300 nm.
34. The manufacturing method according to claim 20, wherein a value of an opening width of the second cavity minus an inner maximum width of the second cavity satisfies minus 30 nm or more and 300 nm or less.
35. The manufacturing method according to claim 20, wherein a value of an opening width of the second cavity minus an inner maximum width of the second cavity satisfies a condition of being equal to or greater than nanometer and equal to or less than 300 nanometer.
36. The manufacturing method according to any one of claims 20 to 35, wherein the withstand voltage of the trench-gate MOSFET power semiconductor device is between 120V and 300V.
37. The manufacturing method according to any one of claims 21 to 35, wherein the etching back of the mask layer employs wet etching.
38. The manufacturing method according to any one of claims 21 to 35, wherein an etching depth of the etching back of the mask layer is in a range of 0.5 to 11 μm.
39. The manufacturing method according to claim 21, wherein the mask layer is etched back to expose a part of the insulating layer on the surface of the epitaxial layer and a part of the insulating layer in the trench.
40. The method of manufacturing of claim 21, wherein the mask layer comprises a dielectric layer or a glue layer.
41. A trench-gate MOSFET power semiconductor device formed using the method of manufacture of any one of claims 20 to 40, comprising:
the semiconductor substrate is used as a drain region;
an epitaxial layer on the semiconductor substrate;
a trench in the epitaxial layer;
an insulating layer in the trench, the insulating layer forming a cavity around the trench;
the polycrystalline silicon layer fills the shielding conductor formed by the cavity;
a gate dielectric and a gate conductor located on top of the insulating layer in the trench, the gate dielectric located on top sidewalls of the trench and the shield conductor, the gate conductor located between the gate dielectrics;
the body region and the source region are positioned in the region, adjacent to the groove, of the epitaxial layer, and the doping types of the body region and the source region are opposite; and
an electrical connection structure of the gate conductor, the shield conductor, the source region and the drain region.
42. The trench-gate MOSFET power semiconductor device of claim 41, wherein said trench has a width of 1 to 5 microns and a depth of 5 to 12 microns.
43. The trench-gate MOSFET power semiconductor device of claim 41, wherein said trench has a width of 1 to 3 microns and a depth of 7 to 12 microns.
44. The trench-gate MOSFET power semiconductor device of claim 41, wherein said insulating layer has a thickness of 0.1 to 2 microns.
45. The trench-gate MOSFET power semiconductor device of claim 41, wherein said insulating layer has a thickness of 0.6 to 1.5 microns.
46. The trench-gate MOSFET power semiconductor device of claim 41, wherein a width W4 between said insulating layer sidewalls at said trench opening minus a width W3 between said insulating layer sidewalls inside said trench satisfies-30 nanometers ≦ W4-W3 ≦ 300 nanometers.
47. The trench-gate MOSFET power semiconductor device of claim 41, wherein a width W4 between said insulating layer sidewalls at said trench opening minus a width W3 between said insulating layer sidewalls inside said trench satisfies 0 nm ≦ W4-W3 ≦ 300 nm.
48. The trench-gate MOSFET power semiconductor device of any one of claims 42 to 47, wherein said trench-gate MOSFET power semiconductor device has a withstand voltage of 120V to 300V.
49. The trench-gate MOSFET power semiconductor device of claim 41, wherein said electrical connection structure comprises a plurality of electrodes connected to said gate conductor, said shield conductor, said source region and said drain region, respectively.
50. The trench-gate MOSFET power semiconductor device of claim 49, wherein said electrical connection structure further comprises a plurality of conductive channels, said gate conductor, said shield conductor, said source region being connected to respective electrodes via respective conductive channels, said drain region being in contact with respective electrodes.
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