CN116631858A - Gate structure of trench MOSFET, manufacturing method of gate structure and trench MOSFET - Google Patents

Gate structure of trench MOSFET, manufacturing method of gate structure and trench MOSFET Download PDF

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Publication number
CN116631858A
CN116631858A CN202310660491.1A CN202310660491A CN116631858A CN 116631858 A CN116631858 A CN 116631858A CN 202310660491 A CN202310660491 A CN 202310660491A CN 116631858 A CN116631858 A CN 116631858A
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insulating layer
gate
trench
layer
forming
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董仕达
刘坚
蔡金勇
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Hangzhou Xinmai Semiconductor Technology Co ltd
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Hangzhou Xinmai Semiconductor Technology Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

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  • Microelectronics & Electronic Packaging (AREA)
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  • Electrodes Of Semiconductors (AREA)

Abstract

The application discloses a gate structure of a trench MOSFET, a manufacturing method thereof and the trench MOSFET, comprising: forming a trench in the epitaxial layer; forming a shielding gate and a first insulating layer at the lower part of the trench, the first insulating layer isolating the shielding gate and the epitaxial layer from each other; forming a second insulating layer having a protruding upper edge on top of the shield gate; a control gate and a gate dielectric are formed in an upper portion of the trench, the gate dielectric isolating the control gate and the epitaxial layer from each other, a second insulating layer between the control gate and the shield gate, wherein a protruding upper edge of the second insulating layer forms a transition curve between a sidewall and a bottom wall of the control gate corresponding to the upper edge. The application improves the forming step of the control grid to obtain the control grid with the included angle of the bottom wall and the side wall being obtuse angle, thereby reducing the electric field intensity at the bottom of the control grid, reducing the probability of the grid dielectric being broken down in advance and protecting the grid dielectric.

Description

Gate structure of trench MOSFET, manufacturing method of gate structure and trench MOSFET
Technical Field
The present application relates to the field of semiconductor technologies, and in particular, to a gate structure of a trench MOSFET, a method for manufacturing the same, and a trench MOSFET.
Background
The trench MOSFET (Metal Oxide Semiconductor Field Effect Transistor ) device has the advantages of high input impedance, small driving current, high switching speed, good high-temperature characteristic and the like, and is widely applied to the field of power electronics.
In a general method for manufacturing a trench MOSFET device, a method for manufacturing a control gate includes etching back an oxide layer in a trench to form a recess; depositing polysilicon in the recess; the polysilicon is etched back to form the control gate. In the manufacturing method, the included angle between the side wall and the bottom wall of the formed control grid is a right angle, so that the electric field intensity of the area is high, the damage to grid oxygen is high, and early breakdown can be caused.
Disclosure of Invention
In view of the foregoing, it is an object of the present application to provide a gate structure of a trench MOSFET, a method for manufacturing the same, and a trench MOSFET, in which a forming step of a control gate is improved to obtain a control gate having an obtuse angle between a bottom and a sidewall, so as to reduce an electric field intensity at the bottom of the control gate, reduce a probability of a gate dielectric being broken down in advance, and protect the gate dielectric.
The application provides a manufacturing method of a gate structure of a trench MOSFET, which comprises the following steps:
forming a trench in the epitaxial layer;
forming a shielding gate and a first insulating layer at a lower portion of the trench, the first insulating layer isolating the shielding gate and the epitaxial layer from each other;
forming a second insulating layer having a protruding upper edge on top of the shield gate;
forming a control gate and a gate dielectric in an upper portion of the trench, the gate dielectric isolating the control gate and the epitaxial layer from each other, the second insulating layer being located between the control gate and the shield gate,
the protruding upper edge of the second insulating layer enables a transition curved surface corresponding to the upper edge to be formed between the side wall and the bottom wall of the control grid.
Drawings
The above and other objects, features and advantages of the present application will become more apparent from the following description of embodiments of the present application with reference to the accompanying drawings in which:
fig. 1 shows a cross-sectional view of a trench MOSFET;
fig. 2 shows a cross-sectional view of a trench MOSFET of an embodiment of the application;
fig. 3a to 3f show cross-sectional views of stages of a method of manufacturing a trench MOSFET device according to an embodiment of the application.
Detailed Description
In the following, like elements are denoted by like reference numerals throughout the various figures. For clarity, the various features of the drawings are not drawn to scale. Furthermore, some well-known portions may not be shown. The semiconductor structure obtained after several steps may be depicted in one figure for simplicity.
When describing the structure of a device, when a layer, an area, is referred to as being "on" or "over" another layer, another area, it can be directly on the other layer, another area, or other layers or areas can be included between the layer, another area, and the other layer, another area. And if the device is flipped, the one layer, one region, will be "under" or "under" the other layer, another region.
If, for the purposes of describing a situation directly overlying another layer, another region, the expression "directly overlying … …" or "overlying … … and adjoining" will be used herein.
Unless specifically indicated below, the various portions of the semiconductor device may be composed of materials known to those skilled in the art. The semiconductor material includes, for example, a III-V semiconductor such as gallium arsenide (GaAs), gallium nitride (GaN), etc., a IV-IV semiconductor such as silicon carbide (SiC), etc., II-VIGroup compound semiconductors such as cadmium sulfide (CdS), cadmium telluride (CdTe), and the like, and group IV semiconductors such as silicon (Si), germanium (Ge), and the like. The gate conductor may be formed of various materials capable of conducting electricity, such as a metal layer, a doped polysilicon layer, or a laminated gate conductor including a metal layer and a doped polysilicon layer, or other conductive materials, such as TaC, tiN, taSiN, hfSiN, tiSiN, tiCN, taAlC, tiAlN, taN, ptSix, ni 3 Si, pt, ru, W, and combinations of various conductive materials. The gate dielectric may be made of SiO 2 Or dielectric constant greater than SiO 2 For example, comprising oxides, nitrides, oxynitrides, silicates, aluminates, titanates. Also, the gate dielectric may be formed of not only a material known to those skilled in the art but also a material for a gate dielectric developed in the future.
Fig. 2 shows a cross-sectional view of a trench MOSFET of a first embodiment of the application. In the present application, the first doping type is one of N-type and P-type, and the second doping type is the other of N-type and P-type. An N-type semiconductor layer may be formed by implanting an N-type dopant, such as P, as, into the semiconductor layer. A P-type semiconductor layer may be formed by doping a P-type dopant, such as B, into the semiconductor layer.
The trench MOSFET 100 includes a substrate 101 and an epitaxial layer 111 thereon, the substrate 101 being of a first doping type, in one embodiment heavily N-doped. An epitaxial layer 111 is located on the first surface of the substrate 101, the epitaxial layer 111 being lightly doped with respect to the substrate 101.
The trench MOSFET 100 includes a gate structure extending from the upper surface of the epitaxial layer 111 into the interior thereof, the gate structure including a trench 112 in the epitaxial layer 111, the trench 112 extending from the upper surface of the epitaxial layer 111 into the interior thereof, terminating in the epitaxial layer 111; a dielectric layer and an electrode conductor inside the trench 112, wherein the dielectric layer inside the trench 112 comprises a first insulating layer 1131, a gate dielectric 1132, and a second insulating layer 1133. The electrode conductors include shield gates 115 and control gates 116. A first insulating layer 1131 and a shield gate 115 are located at a lower portion of the trench 112, the first insulating layer 1131 isolating the shield gate 115 and the epitaxial layer 111 from each other; a second insulating layer 1133 is positioned on top of the shield gate 115, the second insulating layer 1133 having a protruding upper edge; a gate dielectric 1132 and a control gate 116 are located at an upper portion of the trench 112, the gate dielectric 1132 isolating the control gate 116 and the epitaxial layer 111 from each other, and a second insulating layer 1133 is located between the control gate 116 and the shield gate 115, wherein an upper edge of the second insulating layer 1133 protrudes such that a transition curve corresponding to the upper edge is formed between the sidewall and the bottom wall of the control gate 116.
The trench MOSFET 100 further includes a body region 118 located in the epitaxial layer 111 and adjacent to the trench 112, wherein the body region 118 is of the second doping type. A source region 120 of a first doping type is formed in the body region 118; forming a contact region 119 of a second doping type in the body region 118; a third insulating layer 1134 formed over the source region 120 and the gate conductor 116; a conductive channel 121 penetrating the third insulating layer 1134 and the source region 120 to the contact region 119 is formed immediately adjacent to the source region 120; a source electrode 122 is formed over the third insulating layer 1134, the source electrode 122 being connected to the contact region 119 via the conductive via 121.
In this embodiment, the complete interlayer dielectric layer includes two parts, namely, the second insulating layer 1133 and a part of the gate dielectric layer 1132, and for convenience of description, the part of the gate dielectric layer 1132 located between the control gate 116 and the shield gate 115 is referred to as gate dielectric 1132b, and the part located on the upper sidewall of the trench 112 is referred to as gate dielectric 1132a. In the application, the forming step of the second insulating layer 1133 is improved, so that a trench MOSFET with an obtuse transitional curved surface at the joint of the bottom wall and the side wall of the gate dielectric 1132b is obtained, namely, a control gate with an obtuse included angle between the side wall and the bottom wall is obtained, the electric field intensity at the bottom of the control gate is reduced, the probability that the gate dielectric is broken down in advance is reduced, and the gate dielectric is protected.
Fig. 3a to 3f show sectional views of stages of a method of manufacturing a trench MOSFET device according to a first embodiment of the application. The method for manufacturing the trench MOSFET device according to the embodiment of the present application will be described with reference to fig. 3a to 3 f.
Fig. 3a shows a cross-sectional view of a trench MOSFET device in a first embodiment of the application at an initial stage of its manufacture, after forming the trench 112, the first insulating layer 1131 and the shield gate 115; as shown in fig. 3a, an epitaxial layer 111 is formed on a substrate 101, and a trench 112 is formed in the epitaxial layer 111, and a first insulating layer 1131, a shield gate 115, and a second insulating layer 1133 are sequentially formed in the trench 112.
In this step, an epitaxial layer 111 is formed on a first surface of a semiconductor substrate 101, the substrate 101 having a first doping type. In one embodiment, the material of the substrate 101 may be an N-type monocrystalline silicon substrate.
A patterned first mask PR1 is formed on the upper surface of the epitaxial layer 111, and a trench 112 is formed in the epitaxial layer 111 via the first mask PR1.
In this step, a first mask PR1 is formed, for example, using a deposition process, a patterned first mask PR1 is formed using photolithography, and then the epitaxial layer 111 is etched via the patterned first mask PR1 to form a trench 112 in the epitaxial layer 111. In one embodiment, the etching may be a dry etching, such as ion milling, plasma etching, reactive ion etching, laser ablation, or wet etching. In one embodiment, the first mask PR1 may be a photoresist mask, and after forming the trench 112, the first mask PR1 is removed.
Further, a first insulating layer 1131 is formed in the trench 112.
In one embodiment, a first insulating layer 1131 is formed inside the trench 112 and on the upper surface of the epitaxial layer 111 by thermal oxidation or chemical vapor deposition, i.e. the first insulating layer 1131 covers the bottom and the sidewalls of the trench 112 and the upper surface of the epitaxial layer 111, and the first insulating layer 1131 forms a cavity around the sidewalls of the trench 112.
In one embodiment, the first insulating layer 1131 may be composed of an oxide or nitride, for example, silicon oxide or silicon nitride. Thermal oxidation includes hydrothermal oxidation HTO or selective reactive oxidation SRO (Selective Reactive Oxidation), chemical vapor deposition CVD includes low pressure chemical vapor deposition LPCVD or sub-atmospheric pressure chemical vapor deposition SACVD.
Further, a polysilicon layer is filled in the cavity formed around the first insulating layer 1131, and etched back to form the shield gate 115.
In this step, the polysilicon layer located above the epitaxial layer 111 and above the trench 112 is removed by back etching, so that the upper end of the polysilicon layer is terminated in the middle of the trench 112, and the remaining polysilicon layer forms the shield gate 115. The first insulating layer 1131 isolates the shield gate 115 from the epitaxial layer 111. In one embodiment, the etch back may be a dry etch.
In other embodiments, a chemical mechanical planarization process may be used to remove the portion of the polysilicon layer above the epi layer 111, and then etch back the polysilicon layer in the trench 112, such that the upper end of the polysilicon layer terminates in the middle of the trench 112, forming the shield gate 115.
Further, the first insulating layer 1131 is etched back. In this step, an etching process is used to remove the first insulating layer 1131 on the upper surface of the epitaxial layer 111 and the upper portion of the trench 112, such that the first insulating layer 1131 is located between the sidewall of the trench 112 and the shield gate 115, and the first insulating layer 1131 does not cover the top of the shield gate 115. The surface of the first insulating layer 1131 is not lower than the surface of the shield gate 115; in one embodiment, the etching process may be wet etching to Etch a textured surface on a relatively flat film surface, thereby increasing optical path, reducing light reflection, wet etching using diluted HF or BOE (Buffered Oxide etching solution), etc.
Further, a second insulating layer 1133 is formed on the upper surface of the first insulating layer 1131 and the upper surface of the shield gate 115 in the trench.
In this step, an insulating material is deposited by a deposition process and etched back to form a second insulating layer 1133 having a certain thickness, wherein the second insulating layer 1133 covers the upper surface of the first insulating layer 1131 and the upper surface of the shield gate 115, and the first insulating layer 1131 and the second insulating layer 1133 together surround the shield gate 115.
In this embodiment, the second insulating layer 1133 is, for example, a silicon oxide layer, and the second insulating layer 1133 isolates the control gate 116 from the shielding gate 115, which is formed later.
In this embodiment, since the second insulating layer 1133 is etched back in the subsequent step, the thickness of the second insulating layer 1133 shown in fig. 3a is larger than that of the conventional device.
As shown in fig. 3b, a sacrificial layer 114 is formed on the upper surface of the second insulating layer 1133, the upper sidewalls of the trench 112, and the upper surface of the epitaxial layer 111.
In this step, a deposition process is used to form the sacrificial layer 114, wherein the sacrificial layer 114 covers the upper surface of the second insulating layer 1133, the upper sidewalls of the trenches 112, and the upper surface of the epitaxial layer 111.
In this embodiment, the sacrificial layer 114 is, for example, a silicon nitride layer. In other embodiments, the material of the sacrificial layer 114 may be other materials that do not react with the etchant of the second insulating layer 1133.
As shown in fig. 3c, the sacrificial layer 114 on the upper surface of the epitaxial layer 111 and a portion of the upper surface of the second insulating layer 1133 are removed.
In this step, the sacrificial layer 114 on the upper surface of the epitaxial layer 111 and part of the sacrificial layer 114 on the upper surface of the second insulating layer 1133 are removed by an etching process, and only the sacrificial layer 114 on the sidewall of the trench 112 remains. The lower end of the remaining sacrificial layer 114 is in contact with the surface of the second insulating layer 1133. Alternatively, the sacrificial layer 114 forms a cavity around the upper sidewall of the trench 112 and the upper surface of the second insulating layer 1133, and the sacrificial layer 114 at the bottom of the cavity is removed.
In this embodiment, the etching process is, for example, dry etching.
As shown in fig. 3d, the second insulating layer 1133 is etched back using the sacrificial layer 114 as a mask.
In this step, the sacrificial layer 114 is used as a mask to etch the surface of the second insulating layer 1133 exposed in the trench 1112 using an etching process to form a recess in the second insulating layer 1133. Wherein, when etching the second insulating layer 1133, both lateral etching and longitudinal etching are performed simultaneously.
In this embodiment, the etching process is, for example, wet etching. The surface of the second insulating layer 1133 is etched by wet etching, and the etched second insulating layer 1133 has a protruding upper edge near the side wall of the trench 112, and an included angle between the protruding upper edge and the upper surface at the center of the second insulating layer 1133 is an obtuse angle. Wet etching may use a diluted BOE solution (Buffered-Oxide-Etch), etc.
In other embodiments, the etching process may also be a dry etch.
In this embodiment, in the process of etching the surface of the second insulating layer 1133, the ratio of the lateral etching rate to the longitudinal etching rate is 1:1 to 3:1, those skilled in the art may adjust the etch rate according to a specific embodiment.
The etching process is controlled by controlling the etching time so that the etched second insulating layer 1133 has a protruding upper edge, and the groove at the center of the second insulating layer 1133 is not communicated with the sidewall of the trench 112. Further, the thickness of the second insulating layer 1133 at the protruding upper edge upper surface is greater than the thickness of the gate dielectric formed in the subsequent step at the trench sidewall.
In this embodiment, by controlling the angle at the corner of the groove of the second insulating layer 1133, the degree of the included angle between the sidewall and the bottom wall of the control gate formed in the subsequent step can be controlled.
As shown in fig. 3e, the sacrificial layer 114 is removed and a gate dielectric 1132 is formed over the trench 112.
In this step, a deposition process is used to form a gate dielectric 1132, wherein the gate dielectric 1132 covers the upper surface of the second insulating layer 1133, the upper sidewalls of the trenches 112, and the upper surface of the epitaxial layer, and the gate dielectric 1132 forms a cavity around the upper sidewalls of the trenches 112 and the upper surface of the second insulating layer 1133.
Referring to fig. 3e, the first distance L1 is, for example, a thickness at an upper surface of a protruding upper edge formed after the second insulating layer 1133 is etched; the second distance L2 is, for example, the thickness of the gate dielectric 1132 at the sidewalls of the trench 112. In this embodiment, the first distance L1 is greater than the second distance L2. Further, since the first distance L1 is greater than the second distance L2, a portion of the gate dielectric 1132 located at an angle between the sidewall and the bottom wall may appear to be convex toward the cavity, as shown in the dashed box in fig. 3 e.
In this embodiment, the first distance L1 is greater than the second distance L2, which can reduce the breakdown probability of the gate dielectric 1132 at the bottom corner of the control gate, on the one hand, and is more advantageous for forming an obtuse transition surface, on the other hand.
In this embodiment, the gate dielectric 1132 is located at the portion where the included angle between the sidewall and the bottom wall protrudes toward the cavity, so that the distance between the trench sidewall and the included angle between the sidewall and the bottom wall of the subsequently formed control gate 116 is further increased, thereby further reducing the electric field strength at the bottom of the control gate 116, preventing early breakdown, and protecting the gate dielectric 1132.
In this embodiment, the gate dielectric 1132 is, for example, a silicon oxide layer, and the gate dielectric 1132 isolates the subsequently formed control gate 116 from the epitaxial layer 111.
In this embodiment, the gate dielectric 1132 is a conformal layer, so the angle between the sidewall and the bottom wall of the gate dielectric 1132 maintains the shape of the angle between the sidewall and the bottom wall of the second insulating layer 1133, and thus the angle between the sidewall and the bottom wall of the gate dielectric 1132 is also an obtuse angle. In a subsequent step, the control gate 116 is deposited in a cavity formed by the gate dielectric 1132 around the upper sidewalls of the trench 112 and the upper surface of the second insulating layer 1133, so that the angle between the sidewalls and bottom wall of the control gate 116 is also obtuse.
In this embodiment, the etching speed of the surface of the second insulating layer 1133 is controlled, so that the angle between the sidewall and the bottom wall of the control gate 116 is, for example, about 125 °. Further, the angle between the sidewall and the bottom wall of the second insulating layer 1133 and the angle between the sidewall and the bottom wall of the gate dielectric 1132 are also, for example, about 125 °.
In this embodiment, the gate dielectric 1132 includes two parts, one part of the gate dielectric 1132a is located on the upper sidewall of the trench 112 and is used to isolate the control gate 116 from the epitaxial layer 111, and the other part of the gate dielectric 1132b is located on the upper surface of the second insulating layer 1133, which will be used to isolate the shield gate 115 from the control gate 116, so different reference numerals are used to distinguish the gate dielectrics 1132 in different regions. In this embodiment, the second insulating layer 1133 and the gate dielectric 1132b together form an interlayer dielectric layer that is used to isolate the shield gate 115 and the control gate 116.
As shown in fig. 3f, a control gate 116 is formed in the trench 112, a body region 118 and a source region 120 are formed in the epitaxial layer 111, a third insulating layer 1134 is formed on the upper surface of the epitaxial layer 111, a conductive via 121 is formed through the third insulating layer 1134 and reaches the contact region 119, and a source electrode 122 is formed on the surface of the third insulating layer 1134.
In this step, a polysilicon layer is deposited in a cavity formed by the gate dielectric 1132 around the upper sidewalls of the trench 112 and the upper surface of the second insulating layer 1133 using a deposition process to form the control gate 116.
Further, different ions are implanted in the upper portion of the epitaxial layer 111 by an ion implantation process to form the body region 118 and the source region 120. In this embodiment, the body region 118 is of a second doping type, wherein the second doping type is opposite to the first doping type. A region of body region 118 is defined using a photoresist mask and a first ion implantation is performed within the region defined by the photoresist mask, forming body region 118 in epitaxial layer 111 adjacent trench 112, and the photoresist mask is removed after body region 118 is formed. A region of the source region 120 is defined using a photoresist mask and a second ion implantation is performed within the region defined by the photoresist mask to form the source region 120 of the first doping type in the body region 118. By controlling the parameters of the ion implantation, such as implantation energy and dose, the desired depth and the desired doping concentration can be achieved, the depth of body region 118 not exceeding the depth of extension of control gate 116 in trench 112. Body region 118 and source region 120 are adjacent to trench 112, respectively, and control gate 116 is isolated from body region 118 and source region 120 by gate dielectric 1132.
Further, a third insulating layer 1134 is formed on the upper surface of the epitaxial layer 111 and the upper surface of the control gate 116.
In this step, a third insulating layer 1134 is formed on the upper surface of the epitaxial layer 111 and the upper surface of the control gate 116 by a deposition process, and further chemical mechanical planarization is performed to obtain a flat surface. A third insulating layer 1134 covers the top surfaces of epitaxial layer 111 and control gate 116.
In this embodiment, the third insulating layer 1134 is, for example, borophosphosilicate glass.
Further, a contact hole is formed to extend through the third insulating layer 1134 and the source region 120 to the inside of the body region 118.
In this step, for example, a second mask PR2 is formed on the third insulating layer 1134 by a deposition process, a patterned second mask PR2 is formed by photolithography, and then the source region 120 and the body region 118 are etched through the patterned second mask PR2 to form a contact hole extending from the upper surface of the third insulating layer 1134 toward the substrate 101, penetrating the third insulating layer 1134 and the source region 120, and stopping inside the body region 118. In one embodiment, the etching may be a dry etching, such as ion milling, plasma etching, reactive ion etching, laser ablation, or wet etching. In an embodiment, the second mask PR2 may be a photoresist mask, and after forming the contact hole, the second mask PR2 is removed.
Further, a contact region 119 of a second doping type is formed in the body region 118.
In this step, a single ion implantation is performed on the body region 118 via the contact hole, and a contact region 119 of the second doping type is formed in the body region 118.
In this embodiment, since the contact hole extends into the body region 118, ions can be directly implanted into the body region 118 during the process of forming the contact region 119 by ion implantation through the contact hole, and the ion implantation time is shortened in this embodiment compared to the process of ion implantation from the upper surface of the source region 120.
Further, a conductive path 121 and a source electrode 122 are formed.
In this step, a metal layer is formed by a deposition process, covers the third insulating layer 1134, and fills the contact hole, contacting the contact region 119. In this embodiment, the portion of the metal layer filled in the contact hole forms the conductive channel 120, and the portion of the metal layer located on the upper surface of the third insulating layer 1134 forms the source electrode 122. Conductive via 120 extends to contact region 119.
According to the application, the forming step of the second insulating layer is improved, so that the corner angle at the joint of the second insulating layer and the grid dielectric medium is an obtuse angle, and the included angle between the side wall and the bottom wall of the control grid is also an obtuse angle, thereby reducing the electric field intensity at the bottom of the control grid, preventing early breakdown and protecting the grid dielectric medium.
Embodiments in accordance with the present application, as described above, are not intended to be exhaustive or to limit the application to the precise embodiments disclosed. The embodiments were chosen and described in order to best explain the principles of the application and the practical application, to thereby enable others skilled in the art to best utilize the application and various modifications as are suited to the particular use contemplated.

Claims (10)

1. A method of fabricating a gate structure of a trench MOSFET, comprising:
forming a trench in the epitaxial layer;
forming a shielding gate and a first insulating layer at a lower portion of the trench, the first insulating layer isolating the shielding gate and the epitaxial layer from each other;
forming a second insulating layer having a protruding upper edge on top of the shield gate;
forming a control gate and a gate dielectric in an upper portion of the trench, the gate dielectric isolating the control gate and the epitaxial layer from each other, the second insulating layer being located between the control gate and the shield gate,
the protruding upper edge of the second insulating layer enables a transition curved surface corresponding to the upper edge to be formed between the side wall and the bottom wall of the control grid.
2. The gate structure manufacturing method according to claim 1, wherein the second insulating layer is etched such that an angle between an upper surface at a center of the second insulating layer and an upper edge of the second insulating layer protruding is an obtuse angle.
3. The gate structure manufacturing method of claim 2, wherein the step of forming a control gate and a gate dielectric at an upper portion of the trench comprises:
forming a gate dielectric above the second insulating layer, the gate dielectric forming a cavity around the trench sidewalls and the second insulating layer, a transition curve corresponding to the second insulating layer being formed between the sidewalls and bottom wall of the gate dielectric;
the control gate is formed in the cavity,
the transition curved surface between the side wall and the bottom wall of the control grid is an obtuse angle.
4. The gate structure manufacturing method according to claim 3, wherein the protruding upper edge of the second insulating layer makes a transition curve of the sidewall and the bottom wall of the gate dielectric have a protrusion toward the control gate, and a transition curve of the sidewall and the bottom wall of the control gate have a recess toward the inside of the control gate.
5. The gate structure manufacturing method according to claim 1, wherein the step of forming a second insulating layer on top of the shield gate comprises:
depositing an insulating material on top of the shield gate in the trench;
etching back the insulating material in the groove to obtain a second insulating layer with a certain thickness;
forming a sacrificial layer over the second insulating layer and the trench sidewalls within the trench, the sacrificial layer forming a cavity along the second insulating layer and the trench;
removing the sacrificial layer at the bottom of the cavity; and
and etching the second insulating layer by taking the remaining sacrificial layer as a mask to obtain the second insulating layer with the protruding upper edge at the side wall of the groove.
6. The method of manufacturing a gate structure according to claim 5, wherein in the step of etching the second insulating layer with the remaining sacrificial layer as a mask, the second insulating layer is simultaneously subjected to lateral etching and longitudinal etching.
7. The gate structure manufacturing method according to claim 6, wherein a ratio of the lateral etching rate to the longitudinal etching rate is 1:1 to 3:1.
8. the gate structure manufacturing method according to claim 1, wherein a thickness of the second insulating layer at the protruding upper edge surface is a first distance, a thickness of the gate dielectric at the trench sidewall is a second distance, and the first distance is greater than the second distance.
9. A gate structure of a trench MOSFET, comprising:
a trench in the epitaxial layer;
a first insulating layer and a shielding gate positioned at the lower part of the trench, wherein the first insulating layer isolates the shielding gate and the epitaxial layer from each other;
a second insulating layer on top of the shield gate, the second insulating layer having a protruding upper edge;
a gate dielectric and a control gate in an upper portion of the trench, the gate dielectric isolating the control gate and the epitaxial layer from each other, the second insulating layer being between the control gate and the shield gate,
the protruding upper edge of the second insulating layer enables a transition curved surface corresponding to the upper edge to be formed between the side wall and the bottom wall of the control grid.
10. A trench MOSFET comprising:
a substrate;
an epitaxial layer on the upper surface of the substrate,
a gate structure as claimed in any one of claims 1 to 8, located in the epitaxial layer, extending from an upper surface of the epitaxial layer into the interior thereof;
IA23000128
the body region, the source region and the contact region are positioned in the epitaxial layer;
the third insulating layer is positioned on the surface of the epitaxial layer far away from the substrate;
a conductive via extending through the third insulating layer and to a contact region in the epitaxial layer;
and a source electrode on the third insulating layer and electrically connected with the conductive channel.
CN202310660491.1A 2023-06-06 2023-06-06 Gate structure of trench MOSFET, manufacturing method of gate structure and trench MOSFET Pending CN116631858A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117727620A (en) * 2024-02-06 2024-03-19 深圳市顾邦半导体科技有限公司 Preparation method of shielded gate power device and shielded gate power device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117727620A (en) * 2024-02-06 2024-03-19 深圳市顾邦半导体科技有限公司 Preparation method of shielded gate power device and shielded gate power device
CN117727620B (en) * 2024-02-06 2024-04-12 深圳市顾邦半导体科技有限公司 Preparation method of shielded gate power device and shielded gate power device

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