CN116092943B - Air gap isolation structure of trench MOSFET and manufacturing method thereof - Google Patents

Air gap isolation structure of trench MOSFET and manufacturing method thereof Download PDF

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CN116092943B
CN116092943B CN202310201463.3A CN202310201463A CN116092943B CN 116092943 B CN116092943 B CN 116092943B CN 202310201463 A CN202310201463 A CN 202310201463A CN 116092943 B CN116092943 B CN 116092943B
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dielectric layer
air gap
trench
support structure
conductor
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CN116092943A (en
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王振翰
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Hangzhou Xinmai Semiconductor Technology Co ltd
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Hangzhou Xinmai Semiconductor Technology Co ltd
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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    • H01L29/0638—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
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    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors

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Abstract

The application discloses an air gap isolation structure of a trench MOSFET and a manufacturing method thereof, wherein the manufacturing method comprises the following steps: forming a trench extending from an upper surface of the epitaxial layer of the first doping type to an inside thereof; forming a support structure within the trench, and an air gap beneath the support structure; forming a gate conductor and a gate dielectric layer above the support structure, wherein the gate dielectric layer covers the side wall of the groove and isolates the gate conductor from the epitaxial layer; and forming a body region located inside the epitaxial layer and adjacent to the trench; wherein the support structure supports the gate conductor. In this application, bearing structure supports the gate conductor, and the electric leakage path of gate conductor has been cut off to the air gap.

Description

Air gap isolation structure of trench MOSFET and manufacturing method thereof
Technical Field
The present disclosure relates to semiconductor technology, and more particularly, to an air gap isolation structure of a trench MOSFET and a method for fabricating the same.
Background
The trench MOSFET (Metal Oxide Semiconductor Field Effect Transistor ) has the advantages of high input impedance, small driving current, high switching speed, good high-temperature characteristic and the like, and is widely applied to the field of power electronics.
A typical trench MOSFET includes a trench within an epitaxial layer and a gate conductor within the trench. Because the electric field intensity at the bottom of the trench is higher, leakage current is easy to generate between the gate conductor and the epitaxial layer, thereby reducing the reliability of the trench MOSFET.
Disclosure of Invention
In view of the foregoing, an object of the present application is to provide an air gap isolation structure of a trench MOSFET and a method for manufacturing the same, in which a supporting structure is formed inside a trench and an air gap is formed below the supporting structure, the supporting structure supports a gate conductor, and the air gap interrupts a leakage path of the gate conductor.
A first aspect of the present application provides a method for manufacturing an air gap isolation structure of a trench MOSFET, including:
forming a trench extending from an upper surface of the epitaxial layer of the first doping type to an inside thereof;
forming a support structure within the trench, and an air gap beneath the support structure;
forming a gate conductor and a gate dielectric layer above the support structure, wherein the gate dielectric layer covers the side wall of the groove and isolates the gate conductor from the epitaxial layer; and
forming a body region positioned inside the epitaxial layer and adjacent to the groove;
Wherein the support structure supports the gate conductor.
A second aspect of the present application provides an air gap isolation structure of a trench MOSFET, comprising:
an epitaxial layer of a first doping type;
a trench extending from an upper surface of the epitaxial layer to an interior thereof;
a support structure located within the trench;
an air gap located below the support structure;
the grid conductor and the grid dielectric layer are positioned above the supporting structure, and the grid dielectric layer covers the side wall of the groove and isolates the grid conductor from the epitaxial layer; and
a body region located inside the epitaxial layer and adjacent to the trench;
wherein the support structure supports the gate conductor.
Drawings
The above and other objects, features and advantages of the present application will become more apparent from the following description of embodiments of the present application with reference to the accompanying drawings in which:
fig. 1 shows a cross-sectional view of a trench MOSFET according to a first embodiment of the present application;
fig. 2 to 8 are sectional views showing stages of a method of manufacturing a trench MOSFET device according to a first embodiment of the present application;
FIG. 9 shows a schematic representation of the second dielectric layer after the first portion is oxidized;
FIG. 10 shows a schematic representation of a porous support structure of a second dielectric layer;
Fig. 11 is a cross-sectional view of a trench MOSFET according to a second embodiment of the present application;
fig. 12 to 21 are sectional views showing stages of a method of manufacturing a trench MOSFET device according to an embodiment of the present application;
fig. 22 is a cross-sectional view of a trench MOSFET according to a third embodiment of the present application;
fig. 23 to 33 are sectional views showing stages of a method of manufacturing a trench MOSFET device according to a third embodiment of the present application.
Detailed Description
In the following, like elements are denoted by like reference numerals throughout the various figures. For clarity, the various features of the drawings are not drawn to scale. Furthermore, some well-known portions may not be shown. The semiconductor structure obtained after several steps may be depicted in one figure for simplicity.
When describing the structure of a device, when a layer, an area, is referred to as being "on" or "over" another layer, another area, it can be directly on the other layer, another area, or other layers or areas can be included between the layer, another area, and the other layer, another area. And if the device is flipped, the one layer, one region, will be "under" or "under" the other layer, another region.
If, for the purposes of describing a situation directly overlying another layer, another region, the expression "directly overlying … …" or "overlying … … and adjoining" will be used herein.
Unless specifically indicated below, the various portions of the semiconductor device may be composed of materials known to those skilled in the art. Semiconductor materials include, for example, group III-V semiconductors such as gallium arsenide (GaAs), gallium nitride (GaN), and the like, group IV-IV semiconductors such as silicon carbide (SiC), and the like, group II-VI compound semiconductors such as cadmium sulfide (CdS), cadmium telluride (CdTe), and the like, and group IV semiconductors such as silicon (Si), germanium (Ge), and the like. The gate conductor may be formed of various materials capable of conducting electricity, such as a metal layer, a doped polysilicon layer, or a laminated gate conductor including a metal layer and a doped polysilicon layer, or other conductive materials, such as TaC, tiN, taSiN, hfSiN, tiSiN, tiCN, taAlC, tiAlN, taN, ptSix, ni 3 Si, pt, ru, W and a method for producing the sameCombinations of various conductive materials. The gate dielectric may be made of SiO 2 Or dielectric constant greater than SiO 2 For example, comprising oxides, nitrides, oxynitrides, silicates, aluminates, titanates. Also, the gate dielectric may be formed of not only a material known to those skilled in the art but also a material for a gate dielectric developed in the future.
Fig. 1 is a cross-sectional view of a trench MOSFET according to a first embodiment of the present application. In this application, the first doping type is one of N-type and P-type, and the second doping type is the other of N-type and P-type. An N-type semiconductor layer may be formed by implanting an N-type dopant, such as P, as, into the semiconductor layer. A P-type semiconductor layer may be formed by doping a P-type dopant, such as B, into the semiconductor layer.
As shown in fig. 1, the trench MOSFET 100 includes a substrate 101 and an epitaxial layer 111 thereon, the substrate 101 being of a first doping type, in one embodiment heavily N-doped. An epitaxial layer 111 is located on the first surface of the substrate 101, the epitaxial layer 111 being lightly doped with respect to the substrate 101. A drain electrode 124 is formed on the second surface of the substrate 101.
The trench MOSFET 100 includes a trench 112 extending from the upper surface of the epitaxial layer 111 into the interior thereof; a support structure 117 at the bottom of trench 112, an air gap 116 below support structure 117, a gate dielectric layer 1133 and a gate conductor 118 above support structure 117. The trench 112 extends from the upper surface of the epitaxial layer 111 to the inside thereof, terminating in the epitaxial layer 111. The support structure 117 is located at the bottom of the trench 112 with an air gap 116 between the support structure and the bottom of the trench 112. The gate dielectric layer 1133 covers the inner surface of the upper portion of the trench 112, the gate conductor 118 is located above the support structure 117, the sidewall is isolated from the epitaxial layer 111 by the gate dielectric layer 1133, the support structure 117 supports the gate conductor 118, and the gate conductor 118 is isolated from the bottom of the trench 112 by the air gap 116. The material of the support structure 117 is, for example, porous silicon oxide.
The trench MOSFET 100 includes a body region 119 of a second doping type located in the epitaxial layer 111 and adjacent to the trench 112, a source region 121 of a first doping type formed in the body region 119; a body contact region 120 of a second doping type formed in the body region 119; an interlayer dielectric layer 122 formed over the source region 121 and the gate conductor 118; a conductive via 125 formed in close proximity to source region 121 through interlayer dielectric layer 122 and source region 121 to body contact region 120; a source electrode 123 formed over the interlayer dielectric layer 122, and a drain electrode 124 formed at a surface of the substrate 101 remote from the epitaxial layer 111, the source electrode 123 being connected to the body contact region 120 via a conductive via 125. The interlayer dielectric layer 122 may be an oxide layer having a certain thickness, for example, silicon oxide.
The trench MOSFET provided in this embodiment forms a support structure between the gate conductor and the trench bottom, which on the one hand provides support for the gate conductor, and on the other hand is a porous structure providing channels forming air gaps. Further, an air gap is formed between the supporting structure and the bottom of the groove, and the air gap cuts off a channel for current leakage of the gate conductor and prevents the current leakage of the gate conductor to the epitaxial layer.
Further, the support structure is porous silicon oxide with a dielectric constant less than 4 and a dielectric constant of 1 for the air gap, forming a lower dielectric constant isolation structure between the gate conductor and the epitaxial layer. In one embodiment, the dielectric constant of the air gap may be adjusted by ambient vacuum during the manufacturing process.
Fig. 2 to 8 are sectional views showing stages of a method of manufacturing a trench MOSFET device according to a first embodiment of the present application.
As shown in fig. 2, an epitaxial layer 111 is formed on the substrate 101, and a trench 112 is formed in the epitaxial layer 111.
In this step, an epitaxial layer 111 is formed on a semiconductor substrate 101, the substrate 101 functioning as a drain region of the device, having a first doping type. In one embodiment, the material of the substrate 101 may be a single crystal silicon substrate doped to an N-type.
Next, a mask is formed, for example, using a deposition process, a patterned mask is formed using photolithography, and then the epitaxial layer 111, which is not covered with the mask, is etched to form a trench 112 in the epitaxial layer 111. In one embodiment, the etching may be a dry etching, such as ion milling etching, plasma etching, reactive ion etching, laser ablation. In one embodiment, the mask may be a photoresist mask that is removed after the trenches 112 are formed.
As shown in fig. 3, a second dielectric layer 1132 is formed.
In this step, a second dielectric layer 1132 is formed within trench 112 by a deposition process. The second dielectric layer 1132 covers the trench 112 and the upper surface of the epitaxial layer 111. The second dielectric layer is, for example, siGe.
The second dielectric layer on the upper surface of the epitaxial layer 111 is removed by a chemical mechanical polishing process, and then the second dielectric layer in the trench 112 is etched back, so that a second dielectric layer 1132 with a certain thickness remains at the bottom of the trench 112. The second dielectric layer 1132 includes a stacked second portion 1132b and a first portion 1132a in order from bottom to top.
As shown in fig. 4, the first portion 1132a, which is located on top of the second dielectric layer 1132, is oxidized.
In this step, the second dielectric layer 1132 is oxidized, for example, at a temperature of 400 ℃ to 1000 ℃. The selective ratio of the oxidation of the silicon (Si) element and the germanium (Ge) element in the second dielectric layer 1132 is greater than 50, so that the silicon (Si) element in the second dielectric layer 1132 is oxidized to form silicon oxide in the oxidation process, and the germanium (Ge) element is reserved and uniformly distributed in the silicon oxide. As shown in fig. 9.
The oxidized thickness of the second dielectric layer 1132 is controlled by controlling the time of the oxidation such that the second portion 1132b located at the lower portion of the second dielectric layer 1132 remains. I.e., through an oxidation process, a first portion 1132a located above the second dielectric layer 1132 is oxidized and a second portion 1132b located below the second dielectric layer 1132 remains SiGe. The thicknesses of the first portion 1132a and the second portion 1132b may be set according to needs, which is not limited in this embodiment.
As shown in fig. 5, the second dielectric layer 1132 is etched such that the first portion 1132a of the second dielectric layer 1132 forms a porous support structure 117, as particularly shown in fig. 10. The second portion 1132b of the second dielectric layer 1132 is removed entirely to form an air gap 116 between the porous support structure 117 and the bottom of the trench 112.
In this step, a chemical dry etch (chemical dry etch) is used such that the first portion 1132a of the second dielectric layer 1132 is etched to form a porous support structure 117, and then the second portion 1132b of the second dielectric layer 1132 is etched through the porous support structure 117 such that the second portion 1132b of the second dielectric layer 1132 is etched away entirely.
In this embodiment, the second dielectric layer 1132 is etched, for example, using gaseous chloride (HCL), wherein the germanium (Ge) element and the silicon oxide (SiO) in the first portion 1132a of the second dielectric layer 1132 2 ) The etching selectivity is greater than 50, so that germanium (Ge) element in the first portion 1132a of the second dielectric layer 1132 is etched away during the etching process, while silicon oxide (SiO 2 ) Is retained and forms porous silica.
Further, the gaseous chlorine ions etch the second portion 1132b of the second dielectric layer 1132 via the porous silicon oxide such that the second portion 1132b of the second dielectric layer 1132 is entirely etched away while the porous silicon oxide of the first portion 1132a remains.
Through the above steps, an air gap 116 is formed between the porous support structure 117 and the bottom of the trench 112, i.e., an air gap 116 is formed between the support structure 117 and the bottom of the trench 112.
As shown in fig. 6, a gate dielectric layer 1133 and a gate conductor 118 are formed.
In this step, a gate dielectric layer 1133 is formed on the trench sidewalls of the support structure 117 and the upper surface of the epitaxial layer 111, for example, using a thermal oxidation technique, and the trench 112 sidewalls are covered by the gate dielectric layer 1133.
And filling a polysilicon layer in the groove 112 covered with the gate dielectric layer 1133 by adopting a low-pressure chemical vapor deposition mode, wherein the polysilicon layer is positioned above the groove 112 and the epitaxial layer 111. Then, the portion of the polysilicon layer above the epitaxial layer 111 is removed by back etching or chemical mechanical planarization, so that the upper end of the polysilicon layer is terminated at the opening of the trench, and the upper surface of the polysilicon layer is flush with the upper surface of the epitaxial layer 111, forming the gate conductor 118.
Wherein the support structure 117 supports the gate conductor 118, the support structure 117 having a thickness sufficient to support the gate conductor 118; at the same time, the support structure 117 and the air gap 116 isolate the gate conductor 118 from the bottom of the trench 112.
As shown in fig. 7, a body region 119 and a source region 121 are formed in the epitaxial layer 111 in a region adjacent to the trench 112.
Body region 119 is of a second doping type, wherein the second doping type is opposite the first doping type. A first ion implantation is performed to form a body region 119 in epitaxial layer 111 adjacent trench 112. A second ion implantation is performed to form source regions 121 of the first doping type in the body regions 119. By controlling the parameters of the ion implantation, such as implantation energy and dose, the desired depth and the desired doping concentration can be achieved, the depth of the body region 119 not exceeding the depth of extension of the gate conductor 118 in the trench 112. Using a photoresist mask, the laterally extending regions of body region 119 and source region 121 may be controlled. Body region 119 and source region 121 are adjacent to trenches 112, respectively, and are isolated from gate conductor 118 by gate dielectric layer 1133.
As shown in fig. 8, an interlayer dielectric layer 122 is formed over the source region 121.
An interlayer dielectric layer 122 is formed over the source region 121 by a deposition process, and further subjected to chemical mechanical planarization to obtain a planar surface. The interlayer dielectric layer 122 covers the source region 121 and the top surface of the gate conductor 118, and a portion of the gate dielectric layer 1133 located on the first surface of the epitaxial layer 111 may or may not be removed by etching after the source region 121 is formed, is conformal with the interlayer dielectric layer 122, and is located above the source region 121.
A body contact region 120 of the second doping type is formed in the body region 119 through an etching process and an ion implantation process, a conductive channel 125 penetrating the interlayer dielectric layer 122 and the source region 121 to the body contact region 120 is formed through the etching process, and a source electrode 123 is formed over the interlayer dielectric layer 122, the source electrode 123 being connected to the body contact region 120 via the conductive channel 125. A drain electrode 124 is formed on the second surface of the substrate 101 by a deposition process, resulting in the trench MOSFET 100 shown in fig. 1.
In this embodiment, the source electrode 123, the gate conductor 118, and the drain electrode 124 may be formed of conductive materials, respectively, and in one embodiment, may be a metal material such as aluminum alloy or copper.
According to the manufacturing method of the trench MOSFET, a supporting structure is formed between the bottom of the trench and the gate conductor, the supporting structure provides support for the gate conductor on one hand, and on the other hand, the supporting structure is of a porous structure and provides a channel for forming an air gap; an air gap is formed between the supporting structure and the bottom of the groove, and the air gap cuts off a channel for current leakage of the gate conductor and prevents the current leakage of the gate conductor.
In this embodiment, the second dielectric layer is formed inside the trench, and the second dielectric layer is made of SiGe, and the second dielectric layer (SiGe layer) is partially oxidized, so that the porous support structure and the air gap are formed respectively by using different etching selectivity ratios before and after the oxidation of the second dielectric layer (SiGe layer).
In this embodiment, in the process of oxidizing the second dielectric layer (SiGe layer), the silicon (Si) element in the second dielectric layer (SiGe layer) is oxidized to form a silicon oxide layer, and the germanium (Ge) element is kept in an original state, so that the germanium (Ge) is uniformly distributed inside the silicon oxide layer, so that holes uniformly distributed are formed in the silicon oxide layer after the germanium (Ge) is etched away, and further, the portion of the second dielectric layer, which is not oxidized, can be rapidly and uniformly removed through the porous silicon oxide to form an air gap.
In this embodiment, the dielectric constant of the supporting structure is less than 4, the dielectric constant of the air gap is 1, and a lower dielectric constant isolation structure is formed between the gate conductor and the bottom of the trench. In one embodiment, the dielectric constant of the air gap may be adjusted by ambient vacuum during the manufacturing process.
Fig. 11 is a cross-sectional view of a trench MOSFET according to a second embodiment of the present application. As shown in fig. 11, the trench MOSFET 100 includes a substrate 101 and an epitaxial layer 111 thereon, the substrate 101 being of a first doping type, in one embodiment heavily N-doped. An epitaxial layer 111 is located on the first surface of the substrate 101, the epitaxial layer 111 being lightly doped with respect to the substrate 101. A drain electrode 124 is formed on the second surface of the substrate 101.
The trench MOSFET 100 includes a trench 112 extending from the upper surface of the epitaxial layer 111 into the interior thereof; a first dielectric layer 1131 and a first conductor 115 at the lower portion of trench 112, a support structure 117 at the middle of trench 112, and a gate dielectric layer 1133 and a gate conductor 118 at the upper portion of trench 112. The trench 112 extends from the upper surface of the epitaxial layer 111 to the inside thereof, terminating in the epitaxial layer 111. The first dielectric layer 1131 covers the inner surface of the lower portion of the trench 112 and the first conductor 115 is located in a cavity formed by the first dielectric layer 1131 around the lower portion of the trench. The first conductor 115 is isolated from the epitaxial layer 111 by a first dielectric layer 1131.
The support structure 117 is located above the first conductor 115 and the first dielectric layer 1131 with an air gap 116 between the first conductor 115 and the top of the first dielectric layer 1131. The gate dielectric layer 1133 covers the inner surface of the upper portion of the trench, the gate conductor 118 is located above the support structure 117, and the sidewall is isolated from the epitaxial layer 111 by the gate dielectric layer 1133, the support structure 117 supports the gate conductor 118, and is isolated from the first conductor 115 by the support structure 118 and the air gap 116. The material of the support structure 117 is, for example, porous silicon oxide.
The trench MOSFET 100 includes a body region 119 of a second doping type located in the epitaxial layer 111 and adjacent to the trench 112, a source region 121 of a first doping type formed in the body region 119; a body contact region 120 of a second doping type formed in the body region 119; an interlayer dielectric layer 122 formed over the source region 121 and the gate conductor 118; a conductive via 125 formed in close proximity to source region 121 through interlayer dielectric layer 122 and source region 121 to body contact region 120; a source electrode 123 formed over the interlayer dielectric layer 122, and a drain electrode 124 formed at a surface of the substrate 101 remote from the epitaxial layer 111, the source electrode 123 being connected to the body contact region 120 via a conductive via 125. The interlayer dielectric layer 122 may be an oxide layer having a certain thickness, for example, silicon oxide.
The trench MOSFET provided by the embodiment forms an air gap between the first conductor and the gate conductor, and the air gap cuts off a current leakage channel between the first conductor and the gate conductor and prevents current leakage between the first conductor and the gate conductor.
A support structure is formed between the first conductor and the gate conductor, which support structure provides support for the gate conductor on the one hand and which is a porous structure providing channels forming air gaps on the other hand.
Further, the support structure has a dielectric constant less than 4, the air gap has a dielectric constant of 1, and a lower dielectric constant isolation structure is formed between the first conductor and the gate conductor. In one embodiment, the dielectric constant of the air gap may be adjusted by ambient vacuum during the manufacturing process.
Fig. 12 to 21 are sectional views showing stages of a method of manufacturing a trench MOSFET device according to a second embodiment of the present application.
As shown in fig. 12, an epitaxial layer 111 is formed on the substrate 101, and a trench 112 is formed in the epitaxial layer 111.
In this step, an epitaxial layer 111 is formed on a semiconductor substrate 101, the substrate 101 functioning as a drain region of the device, having a first doping type. In one embodiment, the material of the substrate 101 may be a single crystal silicon substrate doped to an N-type.
Next, a mask is formed, for example, using a deposition process, a patterned mask is formed using photolithography, and then the epitaxial layer 111, which is not covered with the mask, is etched to form a trench 112 in the epitaxial layer 111. In one embodiment, the etching may be a dry etching, such as ion milling etching, plasma etching, reactive ion etching, laser ablation. In one embodiment, the mask may be a photoresist mask that is removed after the trenches 112 are formed.
As shown in fig. 13, a first dielectric layer 1131 and a polysilicon layer 1141 are formed in the trench 112.
In one embodiment, a first dielectric layer 1131 is formed inside the trench 112 and on the upper surface of the epitaxial layer 111 by thermal oxidation or chemical vapor deposition, i.e., the first dielectric layer 1131 covers the bottom, the sidewalls, and the upper surface of the epitaxial layer 111 of the trench 112. In an embodiment, the first dielectric layer 1131 may be composed of an oxide or nitride, such as silicon oxide or silicon nitride. Thermal oxidation includes hydrothermal oxidation HTO or selective reactive oxidation SRO (Selective Reactive Oxidation), chemical vapor deposition CVD includes low pressure chemical vapor deposition LPCVD or sub-atmospheric pressure chemical vapor deposition SACVD.
A polysilicon layer 1141 is formed by low pressure chemical vapor deposition inside the trench 112 and on the surface of the first dielectric layer 1131 above the epitaxial layer 111. The first dielectric layer 1131 isolates the polysilicon layer 1141 from the epitaxial layer 111.
As shown in fig. 14, the first dielectric layer 1131 and the polysilicon layer 1141 are etched back.
In this step, the polysilicon layer 1141 is subjected to chemical mechanical polishing, and then the polysilicon layer 1141 is etched back, so that the surface of the first dielectric layer 1131 above the epitaxial layer 111 and the polysilicon layer 1141 above the trench 112 are removed, and the remaining portion of the polysilicon layer 1141 becomes the first conductor 115. In one embodiment, the etch back may be a dry etch.
The first dielectric layer 1131 is etched by an etching process, and the first dielectric layer 1131 located on the upper surface of the epitaxial layer 111 and on the upper portion of the trench 112 is removed, so that the first dielectric layer 1131 is located between the sidewall of the trench 112 and the first conductor 115, and the top of the first conductor 115 is not covered by the first dielectric layer 1131. The surface of the first dielectric layer 1131 is lower than the surface of the first conductor 115; in one embodiment, the etching process may be wet etching to Etch a textured surface on a relatively flat film surface, thereby increasing optical path, reducing light reflection, wet etching using diluted HF or BOE (Buffered Oxide etching solution), etc.
As shown in fig. 15, a second dielectric layer 1132 is formed.
In this step, a second dielectric layer 1132 is formed within trench 112 by a deposition process. A second dielectric layer 1132 is located inside the trench 112 and covers the upper surface of the epitaxial layer 111, in particular, the second dielectric layer 1132 covers the first conductor 115 and the top of the first dielectric layer 1131 and the upper surface of the epitaxial layer 111. The second dielectric layer is, for example, siGe.
The second dielectric layer on the upper surface of the epitaxial layer 111 is removed by a chemical mechanical polishing process, and then the second dielectric layer 1132 in the trench 112 is etched back, so that the second dielectric layer 1132 with a certain thickness remains at the bottom of the trench 112. The second dielectric layer 1132 includes a stacked second portion 1132b and a first portion 1132a in order from bottom to top.
The steps shown in fig. 16 to 21 are the same as those shown in fig. 4 to 8 in the first embodiment, and the description of this embodiment is omitted here.
In the method for manufacturing the trench MOSFET provided in the embodiment, a supporting structure is formed above the first dielectric layer and the first conductor, the supporting structure provides support for the gate conductor on one hand, and provides a channel for forming an air gap for the porous structure on the other hand; an air gap is formed between the support structure and the top of the first dielectric layer and the top of the first conductor, and the air gap interrupts a current leakage channel between the first conductor and the gate conductor, so that current leakage between the first conductor and the gate conductor is prevented.
In this embodiment, a second dielectric layer is formed on a portion of a sidewall of the trench and on top of the first dielectric layer and the first conductor, and the second dielectric layer is made of SiGe, and by partially oxidizing the second dielectric layer (SiGe layer), a porous support structure and an air gap are formed respectively by using different etching selectivity ratios before and after oxidation of the second dielectric layer (SiGe layer).
In this embodiment, in the process of oxidizing the second dielectric layer (SiGe layer), the silicon (Si) element in the second dielectric layer (SiGe layer) is oxidized to form a silicon oxide layer, and the germanium (Ge) element is kept in an original state, so that the germanium (Ge) is uniformly distributed inside the silicon oxide layer, so that holes uniformly distributed are formed in the silicon oxide layer after the germanium (Ge) is etched away, and further, the portion of the second dielectric layer, which is not oxidized, can be rapidly and uniformly removed through the porous silicon oxide to form an air gap.
In this embodiment, the dielectric constant of the supporting structure is less than 4, the dielectric constant of the air gap is 1, and a lower dielectric constant isolation structure is formed between the gate conductor and the bottom of the trench. In one embodiment, the dielectric constant of the air gap may be adjusted by ambient vacuum during the manufacturing process.
Fig. 22 is a cross-sectional view of a trench MOSFET according to a third embodiment of the present application. As shown in fig. 22, the trench MOSFET 100 includes a substrate 101 and an epitaxial layer 111 thereon, the substrate 101 being of a first doping type, in one embodiment heavily N-doped. An epitaxial layer 111 is located on the first surface of the substrate 101, the epitaxial layer 111 being lightly doped with respect to the substrate 101. A drain electrode 124 is formed on the second surface of the substrate 101.
The trench MOSFET 100 includes a trench 112 extending from the upper surface of the epitaxial layer 111 into the interior thereof; a first support structure 117a located at a lower portion of trench 112, a first dielectric layer 1131 and a first conductor 115 located on first support structure 117a, a support structure 117 located at a middle portion of trench 112, and a gate dielectric layer 1133 and a gate conductor 118 located at an upper portion of trench 112.
The trench 112 extends from the upper surface of the epitaxial layer 111 to the inside thereof, terminating in the epitaxial layer 111. The first support structure 117a is located at the lower portion of the trench 112, and has a first air gap 116a between the first support structure and the bottom of the trench 112. The first dielectric layer 1131 and the first conductor 115 are located on a first support structure 117a, and the first support structure 117a supports the first dielectric layer 1131 and the first conductor 115. The first dielectric layer 1131 covers a portion of the inner surface of the trench 112 and the first conductor 115 is located within a cavity formed by the first dielectric layer 1131 and the first support structure 117a around the lower portion of the trench. The first conductor 115 is isolated from the sidewalls of the trench 112 via a first dielectric layer 1131; isolated from the bottom of the trench 112 by the first support structure 117a and the first air gap 116a.
The support structure 117 is located above the first conductor 115 and the first dielectric layer 1131 with an air gap 116 between the first conductor 115 and the top of the first dielectric layer 1131. The gate dielectric layer 1133 covers the inner surface of the upper portion of the trench, the gate conductor 118 is located above the support structure 117, and the sidewall is isolated from the epitaxial layer 111 by the gate dielectric layer 1133, the support structure 117 supports the gate conductor 118, and is isolated from the first conductor 115 by the support structure 118 and the air gap 116.
The material of the first support structure 117a and the support structure 117 is, for example, porous silicon oxide.
The trench MOSFET 100 includes a body region 119 of a second doping type located in the epitaxial layer 111 and adjacent to the trench 112, a source region 121 of a first doping type formed in the body region 119; a body contact region 120 of a second doping type formed in the body region 119; an interlayer dielectric layer 122 formed over the source region 121 and the gate conductor 118; a conductive via 125 formed in close proximity to source region 121 through interlayer dielectric layer 122 and source region 121 to body contact region 120; a source electrode 123 formed over the interlayer dielectric layer 122, and a drain electrode 124 formed at a surface of the substrate 101 remote from the epitaxial layer 111, the source electrode 123 being connected to the body contact region 120 via a conductive via 125. The interlayer dielectric layer 122 may be an oxide layer having a certain thickness, for example, silicon oxide.
The trench MOSFET provided by the embodiment forms an air gap between the first conductor and the gate conductor, and the air gap cuts off a current leakage channel between the first conductor and the gate conductor and prevents current leakage between the first conductor and the gate conductor. Similarly, a first air gap is formed between the first conductor and the bottom of the groove, and the first air gap cuts off a current leakage channel between the first conductor and the bottom of the groove to prevent current leakage between the first conductor and the bottom of the groove.
A first support structure is formed between the first conductor and the bottom of the trench, the first support structure providing support for the first conductor on the one hand, and the porous structure providing a channel down to the first air gap on the other hand. Similarly, a support structure is formed between the first conductor and the gate conductor, the support structure providing support for the gate conductor on the one hand and providing a channel forming an air gap on the other hand.
Further, the dielectric constants of the supporting structure and the first supporting structure are smaller than 4, the dielectric constants of the air gap and the first air gap are 1, and an isolation structure with a lower dielectric constant is formed between the first conductor and the gate conductor and between the first conductor and the bottom of the groove. In one embodiment, the dielectric constants of the air gap and the first air gap may be adjusted by ambient vacuum during the manufacturing process.
Fig. 23 to 33 are sectional views showing stages of a method of manufacturing a trench MOSFET device according to a third embodiment of the present application.
As shown in fig. 23, an epitaxial layer 111 is formed on the substrate 101, and a trench 112 is formed in the epitaxial layer 111.
In this step, an epitaxial layer 111 is formed on a semiconductor substrate 101, the substrate 101 functioning as a drain region of the device, having a first doping type. In one embodiment, the material of the substrate 101 may be a single crystal silicon substrate doped to an N-type.
Next, a mask is formed, for example, using a deposition process, a patterned mask is formed using photolithography, and then the epitaxial layer 111, which is not covered with the mask, is etched to form a trench 112 in the epitaxial layer 111. In one embodiment, the etching may be a dry etching, such as ion milling etching, plasma etching, reactive ion etching, laser ablation. In one embodiment, the mask may be a photoresist mask that is removed after the trenches 112 are formed.
As shown in fig. 24, a third dielectric layer 1134 is formed.
In this step, a third dielectric layer 1134 is formed within trench 112 by a deposition process. The third dielectric layer 1134 covers the trench 112 and the upper surface of the epitaxial layer 111. The third dielectric layer 1134 is, for example, siGe.
The third dielectric layer 1134 on the upper surface of the epitaxial layer 111 is removed by a chemical mechanical polishing process, and then the third dielectric layer 1134 in the trench 112 is etched back, so that the third dielectric layer 1134 with a certain thickness remains at the bottom of the trench 112. The third dielectric layer 1134 includes a fourth portion 1134b and a third portion 1134a stacked in this order from bottom to top.
As shown in fig. 25, a third portion 1134a, which is located on top of the third dielectric layer 1134, is oxidized.
In this step, the third dielectric layer 1134 is oxidized, for example, at a temperature of 400 ℃ to 1000 ℃. The selective ratio of the oxidation of the silicon (Si) element and the germanium (Ge) element in the third dielectric layer 1134 is greater than 50, so that the silicon (Si) element in the third dielectric layer 1134 is oxidized to form silicon oxide in the oxidation process, and the germanium (Ge) element is reserved and uniformly distributed in the silicon oxide.
The oxidized thickness of the third dielectric layer 1134 is controlled by controlling the time of the oxidation such that the fourth portion 1134b located at the lower portion of the third dielectric layer 1134 remains. That is, through the oxidation process, the third portion 1134a located on top of the third dielectric layer 1134 is oxidized and the fourth portion 1134b located on bottom of the third dielectric layer 1134 remains SiGe. The thicknesses of the third portion 1134a and the fourth portion 1134b may be set according to need, which is not limited in this embodiment.
As shown in fig. 26, the third dielectric layer 1134 is etched such that the third portion 1134a of the third dielectric layer 1134 forms a porous first support structure 117a. The fourth portion 1134b of the third dielectric layer 1134 is removed entirely to form a first air gap 116a between the porous first support structure 117a and the bottom of the trench 112.
In this step, a chemical dry etch (chemical dry etch) is used such that the third portion 1134a of the third dielectric layer 1134 is etched to form a porous first support structure 117a, and then the fourth portion 1134b of the third dielectric layer 1134 is etched through the porous first support structure 117a such that the fourth portion 1134b of the third dielectric layer 1134 is etched away entirely.
In this embodiment, the third dielectric layer 1134 is etched, for example, using gaseous chloride (HCL), where the germanium (Ge) element and the silicon oxide (SiO) in the third portion 1134a of the third dielectric layer 1134 2 ) The etching selectivity is greater than 50, so that germanium (Ge) element in the third portion 1134a of the third dielectric layer 1134 is etched away and silicon oxide (SiO 2 ) Is retained and forms porous silica.
Further, the gaseous chlorine ions etch the fourth portion 1134b of the third dielectric layer 1134 via the porous silicon oxide such that the fourth portion 1134b of the third dielectric layer 1134 is entirely etched away while the porous silicon oxide of the third portion 1134a remains.
Through the above steps, a first air gap 116a is formed between the porous first support structure 117a and the bottom of the trench 112, i.e. a first air gap 116a is formed between the first support structure 117a and the bottom of the trench 112.
As shown in fig. 27, a first dielectric layer 1131 and a first conductor 115 are formed in the trench 112 over the first support structure 117 b.
In one embodiment, a first dielectric layer 1131 is formed inside the trench 112 above the first support structure 117b and on the upper surface of the epitaxial layer 111 by thermal oxidation or chemical vapor deposition, i.e., the first dielectric layer 1131 covers the sidewalls of the trench 112 above the first support structure 117b and the upper surface of the epitaxial layer 111. In an embodiment, the first dielectric layer 1131 may be composed of an oxide or nitride, such as silicon oxide or silicon nitride. Thermal oxidation includes hydrothermal oxidation HTO or selective reactive oxidation SRO (Selective Reactive Oxidation), chemical vapor deposition CVD includes low pressure chemical vapor deposition LPCVD or sub-atmospheric pressure chemical vapor deposition SACVD.
A polysilicon layer is formed by low pressure chemical vapor deposition within trench 112 and on the surface of first dielectric layer 1131 over epitaxial layer 111. The first dielectric layer 1131 isolates the polysilicon layer from the epitaxial layer 111.
Next, the first dielectric layer 1131 and the polysilicon layer are etched back.
In this step, the polysilicon layer is subjected to chemical mechanical polishing, and then the polysilicon layer is etched back, so that the surface of the first dielectric layer 1131 above the epitaxial layer 111 and the polysilicon layer above the trench 112 are removed, and the remaining polysilicon layer becomes the first conductor 115. In one embodiment, the etch back may be a dry etch.
The first dielectric layer 1131 is etched by an etching process, and the first dielectric layer 1131 located on the upper surface of the epitaxial layer 111 and on the upper portion of the trench 112 is removed, so that the first dielectric layer 1131 is located between the sidewall of the trench 112 and the first conductor 115, and the top of the first conductor 115 is not covered by the first dielectric layer 1131. The surface of the first dielectric layer 1131 is lower than the surface of the first conductor 115; in one embodiment, the etching process may be wet etching to Etch a textured surface on a relatively flat film surface, thereby increasing optical path, reducing light reflection, wet etching using diluted HF or BOE (Buffered Oxide etching solution), etc.
As shown in fig. 28, a second dielectric layer 1132 is formed.
In this step, a second dielectric layer 1132 is formed within trench 112 by a deposition process. A second dielectric layer 1132 is located inside the trench 112 and covers the upper surface of the epitaxial layer 111, in particular, the second dielectric layer 1132 covers the first conductor 115 and the top of the first dielectric layer 1131 and the upper surface of the epitaxial layer 111. The second dielectric layer is, for example, siGe.
The second dielectric layer on the upper surface of the epitaxial layer 111 is removed by a chemical mechanical polishing process, and then the second dielectric layer 1132 in the trench 112 is etched back, so that the second dielectric layer 1132 with a certain thickness remains at the bottom of the trench 112. The second dielectric layer 1132 includes a stacked second portion 1132b and a first portion 1132a in order from bottom to top.
The steps shown in fig. 29 to 33 are the same as those shown in fig. 4 to 8 in the first embodiment, and the description of this embodiment is omitted here.
In the method for manufacturing the trench MOSFET provided in the embodiment, a first support structure is formed between the bottom of the trench and the first conductor, the first support structure provides support for the first conductor on one hand, and provides a channel for forming the first air gap for the porous structure on the other hand; a first air gap is formed between the first supporting structure and the bottom of the groove, and the first air gap cuts off a current leakage channel of the first conductor and prevents the current leakage of the first conductor.
In this embodiment, the third dielectric layer is formed in the trench, and the third dielectric layer is made of SiGe, and the third dielectric layer (SiGe layer) is partially oxidized, so that the porous first support structure and the first air gap are formed respectively by using different etching selectivity ratios before and after the oxidation of the third dielectric layer (SiGe layer). Similarly, a support structure and an air gap are formed.
In this embodiment, in the oxidation process of the third dielectric layer and the second dielectric layer (SiGe layer), the silicon (Si) element in the third dielectric layer and the second dielectric layer (SiGe layer) is oxidized to form a silicon oxide layer, and the germanium (Ge) element is kept in an original state, so that the germanium (Ge) is uniformly distributed inside the silicon oxide layer to be etched away in the subsequent step, holes with uniform distribution are formed in the silicon oxide layer, and further the portions of the third dielectric layer and the second oxide layer, which are not oxidized, can be rapidly and uniformly removed through porous silicon oxide to form the first air gap and the air gap.
In this embodiment, the first support structure and the support structure have a dielectric constant of less than 4, the first air gap and the air gap have a dielectric constant of 1, and a lower dielectric constant isolation structure is formed between the first conductor and the bottom of the trench and between the gate conductor and the first conductor. In one embodiment, the dielectric constants of the air gap and the first air gap may be adjusted by ambient vacuum during the manufacturing process.
The embodiments according to the present application, as described above, are not intended to be exhaustive or to limit the invention to the precise embodiments disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various modifications as are suited to the particular use contemplated. This application is to be limited only by the claims and the full scope and equivalents thereof.

Claims (28)

1. A method of fabricating an air gap isolation structure of a trench MOSFET, comprising:
forming a trench extending from an upper surface of the epitaxial layer of the first doping type to an inside thereof;
forming a second dielectric layer positioned in the groove, wherein the second dielectric layer is a SiGe layer and comprises a first part positioned at the upper part and a second part positioned at the lower part;
oxidizing the first portion of the second dielectric layer;
etching the first part of the second dielectric layer to form a porous structure, wherein the porous structure is used as a supporting structure for forming a grid conductor; and
etching the second part of the second dielectric layer through the porous structure to form an air gap;
forming a gate conductor and a gate dielectric layer above the support structure, wherein the gate dielectric layer covers the side wall of the groove and isolates the gate conductor from the epitaxial layer; and
forming a body region positioned inside the epitaxial layer and adjacent to the groove;
wherein the support structure supports the gate conductor.
2. The method of claim 1, wherein forming the second dielectric layer within the trench comprises:
Forming a second dielectric layer, wherein the second dielectric layer is positioned in the groove and on the upper surface of the epitaxial layer;
removing the second dielectric layer on the upper surface of the epitaxial layer;
and etching the second dielectric layer in the groove back to form the second dielectric layer positioned in the groove.
3. The method of claim 1, wherein the first portion of the second dielectric layer and the second portion of the second dielectric layer are etched using a chemical dry etch.
4. The method of claim 3, wherein the first portion of the second dielectric layer and the second portion of the second dielectric layer are etched using gaseous chloride ions.
5. The method of claim 1, wherein the porous structure is a porous silicon oxide layer.
6. The method of claim 1, wherein the air gap is located between the support structure and the trench bottom, the support structure and the air gap isolating the gate conductor from the trench bottom.
7. The method of claim 1, wherein forming the support structure and the air gap further comprises:
and forming a first dielectric layer and a first conductor which are positioned at the lower part of the groove, wherein the first dielectric layer covers the inner surface of the lower part of the groove, and the first conductor is isolated from the epitaxial layer.
8. The method of claim 7, wherein forming the support structure and the air gap further comprises:
forming a first support structure located at a lower portion of the trench and a first air gap between the first support structure and a bottom of the trench;
and forming a first dielectric layer and a first conductor in the groove above the first supporting structure, wherein the first dielectric layer covers part of the side wall of the groove above the first supporting structure, and the first conductor is isolated from the side wall of the groove.
9. The method of claim 8, wherein forming the first support structure and a first air gap between the first support structure and a trench bottom comprises:
forming a third dielectric layer at the bottom of the groove, wherein the third dielectric layer comprises a third part at the upper part and a fourth part at the lower part;
oxidizing a third portion of the third dielectric layer;
etching a third part of the third dielectric layer to form a porous structure, wherein the porous structure is used as a first support structure for forming a first conductor; and
and etching the fourth part of the third dielectric layer through the porous structure to form a first air gap.
10. The method of claim 9, wherein forming the third dielectric layer at the bottom of the trench comprises:
forming a third dielectric layer, wherein the third dielectric layer is positioned in the groove and on the upper surface of the epitaxial layer;
removing the third dielectric layer on the upper surface of the epitaxial layer;
and etching the third dielectric layer in the groove back to form the third dielectric layer at the bottom of the groove.
11. The method of claim 9 or 10, wherein the third dielectric layer is a SiGe layer.
12. The method of claim 9, wherein the third portion of the third dielectric layer and the fourth portion of the third dielectric layer are etched using chemical dry etching.
13. The method of claim 12, wherein the third portion of the third dielectric layer and the fourth portion of the third dielectric layer are etched using gaseous chloride ions.
14. The method of claim 9, wherein the porous structure formed by etching the third portion of the third dielectric layer is a porous silicon oxide layer.
15. The method of claim 8, wherein the first support structure has a dielectric constant of less than 4 and the first air gap has a dielectric constant of 1.
16. The method of claim 8 or 9, wherein the support structure is located above the first dielectric layer and first conductor, the air gap is located between the support structure and the top of the first dielectric layer and first conductor, the support structure and the air gap isolating the gate conductor from the first dielectric layer and first conductor.
17. The method of claim 1, wherein the support structure has a dielectric constant of less than 4 and the air gap has a dielectric constant of 1.
18. An air gap isolation structure of a trench MOSFET comprising:
an epitaxial layer of a first doping type;
a trench extending from an upper surface of the epitaxial layer to an interior thereof;
a support structure located within the trench;
an air gap located below the support structure;
the grid conductor and the grid dielectric layer are positioned above the supporting structure, and the grid dielectric layer covers the side wall of the groove and isolates the grid conductor from the epitaxial layer; and
a body region located inside the epitaxial layer and adjacent to the trench;
the support structure supports the gate conductor;
wherein the forming method of the supporting structure and the air gap comprises the following steps:
Forming a second dielectric layer positioned in the groove, wherein the second dielectric layer is a SiGe layer and comprises a first part positioned at the upper part and a second part positioned at the lower part;
oxidizing the first portion of the second dielectric layer;
etching the first part of the second dielectric layer to form a porous structure, wherein the porous structure is used as a supporting structure for forming a grid conductor; and
and etching the second part of the second dielectric layer through the porous structure to form an air gap.
19. The air gap isolation structure of a trench MOSFET of claim 18 wherein the air gap is located between the support structure and the trench bottom, the support structure and the air gap isolating the gate conductor from the trench bottom.
20. The air gap isolation structure of trench MOSFET of claim 18 further comprising a first dielectric layer located in a lower portion of the trench and a first conductor, the first dielectric layer covering an inner surface of the lower portion of the trench, isolating the first conductor from the epitaxial layer.
21. The air gap isolation structure of a trench MOSFET of claim 20, further comprising:
The first supporting structure is positioned at the lower part of the groove;
a first air gap between the first support structure and the trench bottom;
a first dielectric layer and a first conductor over the first support structure, the first dielectric layer covering a portion of sidewalls of the trench over the first support structure, isolating the first conductor from the trench sidewalls.
22. The air gap isolation structure of a trench MOSFET of claim 21, wherein the first support structure is a porous structure.
23. The air gap isolation structure of a trench MOSFET of claim 21 wherein the first support structure is a porous silicon oxide layer.
24. The air gap isolation structure of a trench MOSFET of claim 21 wherein the first support structure has a dielectric constant of less than 4 and the first air gap has a dielectric constant of 1.
25. The air gap isolation structure of a trench MOSFET of claim 20 or 21 wherein the support structure is located above the first dielectric layer and first conductor, the air gap is located between the support structure and the top of the first dielectric layer and first conductor, the support structure and the air gap isolate the gate conductor from the first dielectric layer and first conductor.
26. The air gap isolation structure of a trench MOSFET of claim 18, wherein the support structure is a porous structure.
27. The air gap isolation structure of a trench MOSFET of claim 18, wherein the support structure is a porous silicon oxide layer.
28. The air gap isolation structure of a trench MOSFET of claim 18, wherein the support structure has a dielectric constant of less than 4 and the air gap has a dielectric constant of 1.
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