CN113206148B - Trench MOSFET and manufacturing method thereof - Google Patents

Trench MOSFET and manufacturing method thereof Download PDF

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Publication number
CN113206148B
CN113206148B CN202110381679.3A CN202110381679A CN113206148B CN 113206148 B CN113206148 B CN 113206148B CN 202110381679 A CN202110381679 A CN 202110381679A CN 113206148 B CN113206148 B CN 113206148B
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gate
conductor
trench
insulating layer
semiconductor substrate
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CN113206148A (en
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王加坤
孙鹤
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Hangzhou Xinmai Semiconductor Technology Co ltd
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Hangzhou Xinmai Semiconductor Technology Co ltd
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66666—Vertical transistors

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Abstract

Disclosed are a trench MOSFET and a method of manufacturing the same, the trench MOSFET including: a semiconductor substrate of a first doping type; a trench extending from an upper surface of the semiconductor substrate to an inside thereof; a first insulating layer and a shielding conductor located inside the trench, the first insulating layer being located at a lower sidewall and bottom of the trench and separating the shielding conductor from the semiconductor substrate; the gate dielectric layer is positioned on the side wall of the upper part of the groove and separates the gate conductor from the semiconductor substrate; and a gate conductive path connected to the gate conductor; the thickness of the position of the gate conductor connected with the gate conducting channel meets the process requirement of the through hole, the through hole is not formed, the problem of short circuit between the gate and the shielding conductor is avoided to a great extent, and the reliability of the MOSFET is improved.

Description

Trench MOSFET and manufacturing method thereof
Technical Field
The present invention relates to semiconductor technology, and more particularly, to a trench MOSFET and a method of manufacturing the trench MOSFET.
Background
The shielded gate trench MOSFET is used as a power device and has the characteristics of high breakdown voltage, low on-resistance and high switching speed.
The conventional shielded gate trench MOSFET device, as shown in fig. 1, includes a gate contact hole 101 for connecting the gate conductor 102 and a source contact hole 103 for connecting the body contact region 104, where the gate conductor 102 of the shielded gate trench MOSFET is of a structure with thin middle and thick two sides, and the conventional gate conductor connection mode is to punch a contact hole in the middle of the gate conductor, where the gate conductor is thinner, and if the quality of an oxide layer below the gate conductor is poor, it is easy to cause a short circuit between the gate conductor and the shielding conductor below.
Disclosure of Invention
Accordingly, the present invention is directed to a trench MOSFET and a method for fabricating the same, which solves the gate-source alignment problem.
According to a first aspect of the present invention, there is provided a trench MOSFET comprising: a semiconductor substrate of a first doping type; a trench extending from an upper surface of the semiconductor substrate to an inside thereof; a first insulating layer and a shielding conductor located inside the trench, the first insulating layer being located at a lower sidewall and bottom of the trench and separating the shielding conductor from the semiconductor substrate; the gate dielectric layer is positioned on the side wall of the upper part of the groove and separates the gate conductor from the semiconductor substrate; and a gate conductive path connected to the gate conductor; the thickness of the gate conductor connected with the gate conductive channel meets the process requirement of the through hole and cannot be penetrated.
Preferably, the gate conductor in one trench corresponds to one or two gate conductive channels.
Preferably, when the gate conductor has a different thickness in the vertical direction of the trench MOSFET, the gate conductive path extends to a portion where the gate conductor is thicker.
Preferably, the gate conductor is located at least on an upper surface of the first insulating layer.
Preferably, the gate conductor and the shield conductor are isolated by a second insulating layer, and the second insulating layer is formed by oxidizing a portion of the shield conductor.
Preferably, an upper surface of the shielding conductor is lower than a lower surface of the gate conductor.
Preferably, the upper surface of the shielding conductor is not lower than the lower surface of the gate conductor.
Preferably, the gate conductor has an inverted "concave" shape, and a thickness of a portion of the gate conductor on the shield conductor is smaller than a thickness of a portion thereof on the first insulating layer.
Preferably, the gate conductor includes a first portion and a second portion separated from each other, the first portion and the second portion being separated by the second insulating layer.
Preferably, the gate conductor includes a first portion and a second portion separated from each other, the first portion and the second portion being located on both sides of the shield conductor, respectively.
Preferably, the width of the upper section of the shield conductor between the gate conductors is smaller than the width of the lower section of the shield conductor.
Preferably, the shielding conductor is a polysilicon material.
Preferably, when the number of the gate conductive channels is one, one of the gate conductive channels is in contact with any thicker portion of the gate conductor.
Preferably, when the number of the gate conductive channels is two, the two gate conductive channels are respectively in contact with the thicker portions of the two gate conductors.
Preferably, the number of the gate conductive channels is two, and the two gate conductive channels are respectively contacted with the first part and the second part.
Preferably, the method further comprises: the semiconductor device comprises a semiconductor substrate, an interlayer dielectric layer, a gate metal electrode, a source metal electrode and a drain electrode, wherein the interlayer dielectric layer is arranged on the upper surface of the semiconductor substrate, the gate metal electrode and the source metal electrode are arranged on the interlayer dielectric layer, and the drain electrode is arranged on the lower surface of the semiconductor substrate, wherein the gate metal electrode and the source metal electrode are separated.
Preferably, the gate conductive path includes a contact hole extending from an upper surface of the interlayer dielectric layer into the gate conductor, and a metal filled in the contact hole, the gate metal electrode being in contact with the gate conductor through the gate conductive path.
Preferably, the method further comprises: the body regions are positioned at two sides of the groove, extend from the upper surface of the semiconductor substrate to the inside of the groove, and are adjacent to the groove; a source region of a first doping type located in the body region adjacent to the trench, and a body contact region of a second doping type located in the body region.
Preferably, the source metal electrode further comprises a source region conductive channel extending from the upper surface of the interlayer dielectric layer to the body contact region through the source region, and the source metal electrode is in contact with the body contact region through the source region conductive channel.
Preferably, the semiconductor base comprises a substrate of a first doping type and an epitaxial semiconductor layer of the first doping type on the substrate, the trench being located in the epitaxial semiconductor layer.
According to a second aspect of the present invention, there is provided a method of manufacturing a trench MOSFET, comprising: forming a trench extending from an upper surface into an interior of a semiconductor substrate, the semiconductor substrate being of a first doping type; forming a first insulating layer and a shielding conductor in the trench, wherein the first insulating layer is positioned on the lower side wall and the bottom of the trench and separates the shielding conductor from the semiconductor substrate, and the upper surface of the shielding conductor is higher than the upper surface of the first insulating layer; forming a gate dielectric layer on the side wall of the upper part of the groove, which is not covered by the first insulating layer, filling a gate conductor on the upper part of the groove, and isolating the gate conductor from the semiconductor substrate by the gate dielectric layer; wherein, the part of the shielding conductor exposed by the first insulating layer is oxidized at the same time of forming the gate dielectric layer.
Preferably, the gate dielectric layer is formed by a thermal oxidation process.
Preferably, the shield conductor and the gate conductor are separated by a second insulating layer formed by oxidizing the shield conductor.
Preferably, one or two gate conductive channels are formed in connection with the gate conductor.
Preferably, when the upper surface of the shield conductor is lower than the upper surface of the trench and the exposed portion of the shield conductor by the first insulating layer is completely oxidized, the gate conductor forms an inverted "concave" shape, and the thickness of the portion of the gate conductor on the shield conductor is smaller than the thickness of the portion thereof on the first insulating layer.
Preferably, when the upper surface of the shield conductor is not lower than the upper surface of the trench and the exposed portion of the shield conductor by the first insulating layer is completely oxidized, the gate conductor forms two portions separated from each other, separated by the second insulating layer.
Preferably, when the upper surface of the shielding conductor is lower than the upper surface of the trench, and the exposed part of the shielding conductor by the first insulating layer is not completely oxidized, the gate conductor is positioned at two parts separated from each other, and is positioned at two sides of the non-oxidized shielding conductor respectively.
Preferably, the width of the upper section of the shield conductor between the gate conductors is smaller than the width of the lower section of the shield conductor.
Preferably, the method further comprises: forming an interlayer dielectric layer positioned on the upper surface of the semiconductor substrate; forming a gate metal electrode and a source metal electrode on the upper surface of the interlayer dielectric layer, and forming a drain electrode on the lower surface of the semiconductor substrate.
Preferably, the method for forming the gate conductive channel includes: forming a contact hole extending from the upper surface of the interlayer dielectric layer to the gate conductor before forming the gate metal electrode; and filling metal in the contact hole.
Preferably, when the number of the gate conductive channels is one, one of the gate conductive channels is in contact with any thicker portion of the gate conductor.
Preferably, when the number of the gate conductive channels is two, the two gate conductive channels are respectively in contact with the thicker portions of the two gate conductors.
Preferably, the number of the gate conductive channels is two, and the two gate conductive channels are respectively contacted with the first part and the first part.
Preferably, the method further comprises: forming a body region of a second doping type extending from the upper surface of the semiconductor substrate to the inside of the semiconductor substrate at two sides of the groove, wherein the body region is adjacent to the groove; a source region of a first doping type is formed in the body region adjacent to the trench, and a body contact region of a second doping type is formed in the body region.
Preferably, a source region conductive path is formed extending from the upper surface of the interlayer dielectric layer to the body contact region.
Preferably, the semiconductor base comprises a substrate of a first doping type and an epitaxial layer of the first doping type on the substrate, and the trench is located in the epitaxial layer.
According to the trench MOSFET and the manufacturing method thereof, the shielding conductor exposed by the first insulating layer is oxidized to form the second insulating layer in the process of forming the gate dielectric layer, and then the gate conductor is deposited, so that the steps of the process are simplified, and the process cost is reduced. In addition, the grid conductive channels are arranged at thicker parts on two sides of the grid conductor, so that the grid conductive channels are prevented from being positioned at thinner positions in the middle of the grid conductor, short circuits between the grid conductor and the shielding conductor are caused, and MOS reliability is improved.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the present invention with reference to the accompanying drawings, in which:
FIG. 1 shows a cross-sectional view of a prior art trench MOSFET;
fig. 2 shows a cross-sectional view of a trench MOSFET according to a first embodiment of the invention;
fig. 3 shows a cross-sectional view of a trench MOSFET according to a second embodiment of the invention;
fig. 4 shows a cross-sectional view of a trench MOSFET according to a third embodiment of the invention;
fig. 5a-5c show cross-sectional views of various stages of a method of manufacturing a trench MOSFET according to an embodiment of the invention.
Detailed Description
The invention will be described in more detail below with reference to the accompanying drawings. Like elements are denoted by like reference numerals throughout the various figures. For clarity, the various features of the drawings are not drawn to scale. Furthermore, some well-known portions may not be shown. The semiconductor structure obtained after several steps may be depicted in one figure for simplicity.
It will be understood that when a layer, an area, or a structure of a device is described as being "on" or "over" another layer, another area, it can be referred to as being directly on the other layer, another area, or further layers or areas can be included between the other layer, another area, etc. And if the device is flipped, the one layer, one region, will be "under" or "beneath" the other layer, another region.
If, for the purposes of describing a situation directly on top of another layer, another region, the expression "a directly on top of B" or "a directly on top of B and adjoining it" will be used herein. In this application, "a is directly in B" means that a is in B and a is directly adjacent to B, rather than a being in the doped region formed in B.
In this application, the term "semiconductor structure" refers to a generic term for the entire semiconductor structure formed in the various steps of fabricating a semiconductor device, including all layers or regions that have been formed. The term "laterally extending" refers to extending in a direction generally perpendicular to the direction of the depth of the trench.
Numerous specific details of the invention, such as device structures, materials, dimensions, processing techniques and technologies, are set forth in the following description in order to provide a thorough understanding of the invention. However, as will be understood by those skilled in the art, the present invention may be practiced without these specific details.
Unless specifically indicated below, the various portions of the semiconductor device may be composed of materials known to those skilled in the art. Semiconductor materials include, for example, group III-V semiconductors such as GaAs, inP, gaN, siC, and group IV semiconductors such as Si, ge. The gate conductor may be formed of various materials capable of conducting electricity, such as a metal layer, a doped polysilicon layer, or a laminated gate conductor including a metal layer and a doped polysilicon layer, or other conductive materials, such as TaC, tiN, taSiN, hfSiN, tiSiN, tiCN, taAlC, tiAlN, taN, ptSix, ni 3 Si, pt, ru, W, and combinations of the various conductive materials. The gate dielectric may be made of SiO 2 Or dielectric constant greater than SiO 2 For example, comprising oxides, nitrides, oxynitrides, silicates, aluminates, titanates. Also, the gate dielectric may be formed of not only a material known to those skilled in the art but also a material for a gate dielectric developed in the future.
The invention discloses a trench MOSFET, which is characterized by comprising the following components: a semiconductor substrate of a first doping type; a trench extending from an upper surface of the semiconductor substrate to an inside thereof; a first insulating layer and a shielding conductor located inside the trench, the first insulating layer being located at a lower sidewall and bottom of the trench and separating the shielding conductor from the semiconductor substrate; the gate dielectric layer is positioned on the side wall of the upper part of the groove and separates the gate conductor from the semiconductor substrate; and a gate conductive path connected to the gate conductor; the thickness of the gate conductor connected with the gate conductive channel meets the process requirement of the through hole and cannot be penetrated.
In particular, the present invention may be presented in various forms, some examples of which are described below.
Fig. 2 shows a cross-sectional view of a trench MOSFET according to a first embodiment of the invention.
The trench MOSFET includes a semiconductor substrate, a trench 203 in the semiconductor substrate, a first insulating layer 204 inside the trench 203, a shield conductor 205, a gate dielectric layer 206 and a gate conductor 207, and a gate conductive via 212 connected to the gate conductor 207. Specifically, the trench 203 extends from the upper surface of the semiconductor substrate into the interior thereof, and the trench 203 terminates within the semiconductor substrate. The first insulating layer 204 is located at the lower sidewall and bottom of the trench 203 and separates the shield conductor 205 from the semiconductor substrate. The gate dielectric layer 206 and the gate conductor 207 are located at the upper portion of the trench, the gate dielectric layer 206 is located at the upper sidewall of the trench 203 and separates the gate conductor 207 from the semiconductor substrate, and the gate conductor 207 is located at least on the upper surface of the first insulating layer 204. The shield conductor 205 is isolated from the gate conductor 207 by a second insulating layer 208, the second insulating layer 208 being formed by oxidizing a portion of the shield conductor 205. Wherein the thickness of the gate conductor 207 connected to the gate conductive via 212 satisfies the process requirement of a via hole and is not penetrated. The gate conductor 207 in one trench corresponds to one or two gate conductive channels 212. In this embodiment, the first insulating layer 204 may be composed of oxide or nitride, for example, silicon oxide or silicon nitride; the gate dielectric layer 206 and the second insulating layer 208 are oxide layers formed by a thermal oxidation process. The shield conductor 205 and the gate conductor 207 may be composed of polysilicon.
In this embodiment, the upper surface of the shielding conductor 205 is lower than the upper surface of the gate conductor 207, the gate conductor 207 has an inverted "concave" shape, and the thickness of the portion of the gate conductor 207 on the shielding conductor 205 is smaller than the thickness of the portion thereof on the first insulating layer 204, i.e., the gate conductor 207 includes two thicker portions. When the number of the gate conductive channels 212 is one, the gate conductive channels 212 are connected to any thicker portion of the gate conductor 207; when the number of the gate conductive channels 212 is two, the two gate conductive channels 212 are respectively connected to two thicker portions of the gate conductor 207.
The trench MOSFET further includes an interlayer dielectric layer 216 on the upper surface of the semiconductor substrate and a metal electrode over the interlayer dielectric layer 216. The metal electrodes include a gate metal electrode 215 and a source metal electrode 214. The gate conductive via 212 includes a first contact hole extending from the upper surface of the interlayer dielectric layer 216 into the gate conductor 207 and a metal material filling the first contact hole. The gate metal electrode 215 is in contact with the gate conductor 207 through the gate conductive via 212.
The trench MOSFET further includes a body region 209, a source region 210, and a body contact region 211 in the semiconductor substrate. Specifically, the body 209 is located in an upper region of the semiconductor substrate adjacent to the trench and is of the second doping type, wherein the junction depth of the body 209 does not exceed the depth of the gate conductor 207 in the trench; source region 210 is located in the body region 209 and is of a first doping type; and a body contact region 211 is located in the body region 209 and is of a second doping type. The doping concentration of the body contact region 211 is greater than that of the body region 209 to reduce the subsequent ohmic contact resistance with the source electrode. Wherein the second doping type is opposite to the first doping type, the first doping type is one of an N type and a P type, and the second doping type is the other of the N type and the P type. The trench MOSFET further includes a source region conductive channel 213, the source region conductive channel 213 including a second contact hole extending from an upper surface of the interlayer dielectric layer 216 through the source region 210 to the body contact region 211 and a metal material filled in the second contact hole. The source metal electrode 214 is in contact with the body contact region 211 through the source region conductive via 213.
In the present application, the semiconductor base comprises a semiconductor substrate 201 and an epitaxial semiconductor layer 202 located thereon, said semiconductor substrate 201 being composed of, for example, silicon and being of a first doping type. The first doping type is one of N-type and P-type, and the second doping type is the other of N-type and P-type. To form the N-type epitaxial semiconductor layer or region, an N-type dopant (e.g., P, as) may be implanted into the epitaxial semiconductor layer and region. To form the P-type epitaxial semiconductor layer or region, a P-type dopant (e.g., B) may be incorporated into the epitaxial semiconductor layer and region. In one example, the semiconductor substrate 201 is N-type doped.
An epitaxial semiconductor layer 202 of a first doping type is located on the surface of the semiconductor substrate 201 opposite to the drain electrode 220 (i.e. on the first surface of the semiconductor substrate 201), said trench 203 being located in said epitaxial semiconductor layer 202. The epitaxial semiconductor layer 202 is composed of, for example, silicon, and the epitaxial semiconductor layer 202 is a lightly doped layer with respect to the semiconductor substrate 201. The second surface of the semiconductor substrate is thinned by a thinning technique, and a drain electrode 220 is formed on the second surface. In some embodiments, a buffer layer may be further disposed between the semiconductor substrate 201 and the epitaxial semiconductor layer 202, where the buffer layer has the same doping type as the semiconductor substrate, in order to reduce interface instability between the semiconductor substrate and the epitaxial semiconductor layer due to defects of the substrate.
Fig. 3 shows a cross-sectional view of a trench MOSFET according to a second embodiment of the invention.
The trench MOSFET of the present embodiment is different from the trench MOSFET of the first embodiment in that the gate conductor has a different shape, and other structures are identical, which will not be described herein.
In this embodiment, the upper surface of the shielding conductor 305 is lower than the lower surface of the gate conductor 307, and the gate conductor 307 includes a first portion and a second portion separated from each other, and the first portion and the second portion are separated by the second insulating layer 308. The number of the gate conductive channels 312 is two, and the two gate conductive channels 312 are respectively in contact with the first portion and the second portion of the gate conductor 307.
Fig. 4 shows a cross-sectional view of a trench MOSFET according to a third embodiment of the invention.
The trench MOSFET of this embodiment is different from the trench MOSFET of the first embodiment in that the shapes of the gate conductor and the shield conductor are different, and other structures are identical, which will not be described herein.
In this embodiment, the upper surface of the shielding conductor 405 is not lower than the lower surface of the gate conductor 407, and the gate conductor 407 includes a first portion and a second portion that are separated from each other, and the first portion and the second portion are located on two sides of the shielding conductor 405, respectively. The width of the upper section of the shield conductor 405 between the gate conductors 407 is smaller than the width of the lower section of the shield conductor 405. The number of the gate conductive channels 412 is two, and the two gate conductive channels 412 are respectively in contact with the first portion and the second portion of the gate conductor 407.
According to the trench MOSFET structure provided by the invention, the thickness of the position of the gate conductor connected with the gate conducting channel meets the process requirement of the through hole by changing the position of the gate conducting channel, so that the gate conductor cannot be penetrated, the problem of short circuit between the gate and the shielding conductor is avoided to a great extent, and the MOS reliability is improved.
The invention provides a method for manufacturing a trench MOSFET, which comprises the following steps: forming a trench extending from an upper surface into an interior of a semiconductor substrate, the semiconductor substrate being of a first doping type; forming a first insulating layer and a shielding conductor in the trench, wherein the first insulating layer is positioned on the lower side wall and the bottom of the trench and separates the shielding conductor from the semiconductor substrate, and the upper surface of the shielding conductor is higher than the upper surface of the first insulating layer; forming a gate dielectric layer on the side wall of the upper part of the groove, which is not covered by the first insulating layer, filling a gate conductor on the upper part of the groove, and isolating the gate conductor from the semiconductor substrate by the gate dielectric layer; wherein, the part of the shielding conductor exposed by the first insulating layer is oxidized at the same time of forming the gate dielectric layer.
In particular, fig. 5a to 5c describe various stages of a method of manufacturing a trench MOSFET according to the invention.
As shown in fig. 5a, a trench 203 is formed in the semiconductor substrate extending from the surface to the inside thereof. Specifically, in the present application, the semiconductor base includes a semiconductor substrate 201 and an epitaxial semiconductor layer 202 on the semiconductor substrate 201. Forming a patterned barrier layer on the epitaxial semiconductor layer 202; the epitaxial semiconductor layer 202 is etched with the barrier layer as a mask, and a trench 203 is further formed in the epitaxial semiconductor layer 202. The trench extends from the upper surface of the epitaxial semiconductor layer 202 into the epitaxial semiconductor layer 202. For example, the etching time can be controlled, and the depth of the trench can be controlled.
Subsequently, a first insulating layer and an electrode conductor are formed within the trench. Specifically, a first insulating layer 204 is formed inside the trench 203 by thermal oxidation or chemical vapor deposition, i.e. the first insulating layer 204 covers the bottom and the side walls of the trench; the first insulating layer 204 may be composed of oxide or nitride, for example, silicon oxide or silicon nitride.
A shield conductor 205 is then formed inside the trench by means of low pressure chemical vapor deposition. The first insulating layer 204 separates the shield conductor 205 from the epitaxial semiconductor layer 202. The shield conductor 205 may be comprised of polysilicon.
As shown in fig. 5b, the shield conductor 205 is etched back selectively with respect to the first insulating layer 202 such that the upper surface of the shield conductor 205 is lower than the upper surface of the trench 203; the first insulating layer 204 is then etched such that the upper surface of the first insulating layer 204 is lower than the upper surface of the shield conductor 205.
Of course, in other embodiments, the shield conductor may alternatively not be etched back such that the upper surface of the shield conductor is not lower than the upper surface of the trench 203.
Subsequently, in fig. 5c, an oxide layer is formed on the sidewalls of the upper portion of the trench, which is the gate dielectric layer 206, using a thermal oxidation technique, such that the sidewalls of the upper portion of the trench are covered by the formed gate dielectric layer 206. Meanwhile, during the thermal oxidation process, the shielding conductor 205 exposed by the first insulating layer 204 is also completely oxidized into the second insulating layer 208, and the first insulating layer 204, the second insulating layer 208 and the gate dielectric layer 206 form conformality. Wherein the thermal oxidation technique is generally a chemical reaction of silicon with a gas containing an oxidizing substance, such as water vapor and oxygen, at high temperature to produce a layer of dense silicon dioxide (SiO) 2 ) Thin films are an important process in silicon planar technology.
Further, a low-pressure chemical vapor deposition method is adopted to fill the gate conductor 207 in the trench covered with the gate dielectric layer 206. Specifically, the gate conductor 207 fills the entire trench. Since there is a shield conductor oxidized into a second insulating layer, the gate conductor is formed in an inverted concave shape, i.e., with a thickness in the middle thereof being smaller than that of the two sides thereof, specifically, a thickness of the gate conductor above the shield conductor is smaller than that of the gate conductor above the first insulating layer.
In another embodiment, when the upper surface of the shielding conductor 205 in the step of fig. 5b is lower than the upper surface of the trench 203, and the shielding conductor 205 exposed by the first insulating layer 204 in the step of fig. 5c is not completely oxidized, the width of the upper section of the shielding conductor exposed by the first insulating layer is smaller than the width of the lower section thereof, and both sides of the upper section thereof are covered with a second insulating layer formed by oxidation. After the gate conductor is subsequently formed, the structure of the gate conductor 407 and the shield conductor 405 as shown in fig. 4 is formed. The gate conductor 407 includes two portions on either side of the upper section of the shield conductor 405, separated from the shield conductor by a second insulating layer 408.
In another embodiment, when the upper surface of the shielding conductor 205 in the step of fig. 5b is not lower than the upper surface of the trench 203, and the shielding conductor 205 exposed by the first insulating layer 204 in the step of fig. 5c is completely oxidized, after the gate conductor is formed again, the gate conductor 307 and the shielding conductor 305 shown in fig. 3 are formed, and the upper surface of the shielding conductor 305 is lower than the lower surface of the gate conductor 307, and the shielding conductor 305 includes two separated parts, and the two parts are separated by the second insulating layer 308 formed by oxidizing the shielding conductor.
Subsequently, in fig. 2, a first ion implantation is performed using conventional body implantation and drive-in techniques, forming a body region 209 of the second doping type in an upper region of the epitaxial semiconductor layer 202 adjacent to the trench, said body region 209 extending from the upper surface of said epitaxial semiconductor layer 202 into the interior thereof. Further, a second ion implantation is performed to form a source region 210 of the first doping type in the body region 209, the source region 210 extending from the upper surface of the epitaxial semiconductor layer 202 to the inside thereof, the junction depth of the source region 210 being smaller than the junction depth of the body region 209. The body 209 of the second type of doping type is of opposite type to the epitaxial semiconductor layer 202 of the first type of doping type. By controlling the parameters of the ion implantation, such as implantation energy and dose, the desired depth and the desired doping concentration can be achieved, the depth of the body 209 not exceeding the depth of extension of the gate conductor 207 in the trench. Preferably, body region 209 and source region 210 are adjacent to the trenches, respectively, separated from gate conductor 207 by gate dielectric layer 206. During the formation of the body region 209 and the source region 210, the gate dielectric layer remaining on the upper surface of the epitaxial semiconductor layer 202 in the above process is not removed and may be used to protect the surface of the epitaxial semiconductor layer 202 from damage during ion implantation.
An interlayer dielectric layer 216 is formed on the upper surface of the epitaxial semiconductor layer 202. In this embodiment, specifically, a dielectric layer is formed on the upper surface of the epitaxial semiconductor layer 202; further performing chemical mechanical planarization to remove a portion of the dielectric layer to obtain a planar surface. The interlayer dielectric layer 120 is an oxide layer, for example, silicon oxide. The interlayer dielectric layer 216 may be formed by a deposition process. Of course, those skilled in the art may also use other methods to remove a portion of the dielectric layer to obtain a planar surface, and no limitation is placed thereon.
Subsequently, etching portions of the interlayer dielectric layer 216 and the gate conductor to form a first contact hole, and etching portions of the interlayer dielectric layer 216 and the source region 210 to form a second contact hole; and then performing a third ion implantation, and forming a body contact region 211 in the body region 209 through the second contact hole by adopting a self-alignment process, wherein the body contact region 211 is positioned on the surface of the etched body region 209, and the body contact region 211 is of a second doping type. Metal is filled in the first contact hole and the second contact hole to form a gate conductive path 212 and a source conductive path 213, respectively. In this embodiment, the gate conductor in one trench corresponds to one or two gate conductive channels 212, and when the number of the gate conductive channels 212 is one, the gate conductive channels 212 are connected to any thicker portion of the gate conductor 207; when the number of the gate conductive channels 212 is two, the two gate conductive channels 212 are respectively connected to two thicker portions of the gate conductor 207.
In another embodiment, when the gate conductor structure as shown in fig. 3 and fig. 4 is formed, the number of the gate conductive channels is two, and the two gate conductive channels are respectively connected with the two portions of the gate conductor.
Subsequently, a metal is deposited on the interlayer dielectric layer 216 to form a gate metal electrode 215 and a source metal electrode 214, the gate metal electrode 215 being in contact with the gate conductor 207 through the gate conductive channel 212, the source metal electrode 214 being in contact with the source region 210 and the body contact region 211 through the source region conductive channel 213. Subsequently, a drain electrode 220 is formed on the second surface of the semiconductor substrate 201 thinned by the thinning technique by the above known deposition process.
In the above-described embodiments, the gate electrode 215, the source electrode 214, and the drain electrode 220 may be formed of conductive materials, including metal materials such as aluminum alloy or copper, respectively.
According to the method for forming the trench MOSFET structure, the shielding conductor exposed by the first insulating layer is oxidized to form the second insulating layer in the process of forming the gate dielectric layer, and then the gate conductor is deposited, so that the steps of the process are simplified, and the process cost is reduced. In addition, the grid conductive channels are arranged at thicker parts on two sides of the grid conductor, so that the grid conductive channels are prevented from being positioned at thinner positions in the middle of the grid conductor, short circuits between the grid conductor and the shielding conductor are caused, and MOS reliability is improved.
It should be noted that in this document relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
Embodiments in accordance with the present invention, as described above, are not intended to be exhaustive or to limit the invention to the precise embodiments disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various modifications as are suited to the particular use contemplated. The invention is limited only by the claims and the full scope and equivalents thereof.

Claims (33)

1. A trench MOSFET comprising:
a semiconductor substrate of a first doping type;
a trench extending from an upper surface of the semiconductor substrate to an inside thereof;
a first insulating layer and a shielding conductor located inside the trench, the first insulating layer being located at a lower sidewall and bottom of the trench and separating the shielding conductor from the semiconductor substrate;
the gate dielectric layer is positioned on the side wall of the upper part of the groove and separates the gate conductor from the semiconductor substrate; and
a gate conductive path connected to the gate conductor;
the thickness of the position of the gate conductor connected with the gate conductive channel meets the process requirement of a through hole and cannot be penetrated;
wherein when the gate conductor has different thicknesses in the vertical direction of the trench MOSFET, the gate conductive path extends to a portion where the gate conductor is thicker.
2. The trench MOSFET of claim 1 wherein the gate conductor in one trench corresponds to one or two gate conductive channels.
3. The trench MOSFET of claim 1, wherein the gate conductor is located at least on an upper surface of the first insulating layer.
4. The trench MOSFET of claim 2, wherein the gate conductor and the shield conductor are separated by a second insulating layer formed by oxidizing a portion of the shield conductor.
5. The trench MOSFET of claim 4 wherein an upper surface of the shield conductor is lower than a lower surface of the gate conductor.
6. The trench MOSFET of claim 4 wherein an upper surface of the shield conductor is not lower than a lower surface of the gate conductor.
7. The trench MOSFET of claim 5 wherein the gate conductor has an inverted "concave" shape, and a portion of the gate conductor on the shield conductor has a thickness that is less than a portion of the gate conductor on the first insulating layer.
8. The trench MOSFET of claim 5 wherein the gate conductor comprises a first portion and a second portion separated from each other, the first portion and the second portion being separated by the second insulating layer.
9. The trench MOSFET of claim 6 wherein the gate conductor comprises first and second portions separated from each other, the first and second portions being on opposite sides of the shield conductor, respectively.
10. The trench MOSFET of claim 9 wherein a width of an upper segment of the shield conductor between the gate conductors is less than a width of a lower segment of the shield conductor.
11. The trench MOSFET of claim 1, wherein the shield conductor is a polysilicon material.
12. The trench MOSFET of claim 7 wherein one of said gate conductive channels is in contact with any thicker portion of said gate conductor when said number of gate conductive channels is one.
13. The trench MOSFET of claim 7 wherein when the number of said gate conductive channels is two, two said gate conductive channels are in contact with respective thicker portions of two said gate conductors.
14. The trench MOSFET of claim 8 or 9, wherein the number of gate conductive channels is two, the two gate conductive channels being in contact with the first portion and the second portion, respectively.
15. The trench MOSFET of claim 1, further comprising:
an interlayer dielectric layer on the upper surface of the semiconductor substrate,
a gate metal electrode and a source metal electrode on the interlayer dielectric layer, an
A drain electrode on the lower surface of the semiconductor substrate,
wherein the gate metal electrode and the source metal electrode are spaced apart.
16. The trench MOSFET of claim 15 wherein the gate conductive channel comprises a contact hole extending from an upper surface of the interlayer dielectric layer into the gate conductor, and metal filling the contact hole, the gate metal electrode being in contact with the gate conductor through the gate conductive channel.
17. The trench MOSFET of claim 15, further comprising:
the body regions are positioned at two sides of the groove, extend from the upper surface of the semiconductor substrate to the inside of the groove, and are adjacent to the groove;
a source region of a first doping type located in the body region adjacent to the trench, and
and a body contact region of a second doping type in the body region.
18. The trench MOSFET of claim 17 further comprising a source conductive channel extending from an upper surface of said interlevel dielectric layer through said source region to said body contact region, said source metal electrode being in contact with said body contact region through said source conductive channel.
19. The trench MOSFET of claim 1 wherein the semiconductor base comprises a substrate of a first doping type and an epitaxial semiconductor layer of the first doping type on the substrate, the trench being in the epitaxial semiconductor layer.
20. A method of fabricating a trench MOSFET, comprising:
forming a trench extending from an upper surface into an interior of a semiconductor substrate, the semiconductor substrate being of a first doping type;
forming a first insulating layer and a shielding conductor in the trench, wherein the first insulating layer is positioned on the lower side wall and the bottom of the trench and separates the shielding conductor from the semiconductor substrate, and the upper surface of the shielding conductor is higher than the upper surface of the first insulating layer;
forming a gate dielectric layer on the side wall of the upper part of the groove which is not covered by the first insulating layer,
filling a gate conductor at the upper part of the groove, and isolating the gate conductor from the semiconductor substrate by the gate dielectric layer; and
forming one or two gate conductive channels connected to the gate conductor;
wherein, the part of the shielding conductor exposed by the first insulating layer is oxidized at the same time of forming the gate dielectric layer;
wherein when the number of the gate conductive channels is one, one of the gate conductive channels is in contact with any thicker portion of the gate conductor.
21. The method of claim 20, wherein the gate dielectric layer is formed by a thermal oxidation process.
22. The method of claim 20, wherein the shield conductor and the gate conductor are separated by a second insulating layer formed by oxidizing the shield conductor.
23. The method of claim 20, wherein when the upper surface of the shield conductor is lower than the upper surface of the trench and the exposed portion of the shield conductor is fully oxidized, the gate conductor forms an inverted "concave" shape and the portion of the gate conductor on the shield conductor has a thickness that is less than the thickness of the portion of the gate conductor on the first insulating layer.
24. The method of claim 22, wherein the gate conductor forms two parts separated from each other by the second insulating layer when an upper surface of the shield conductor is not lower than an upper surface of the trench and a portion of the shield conductor exposed by the first insulating layer is completely oxidized.
25. The method of claim 20, wherein when an upper surface of the shield conductor is lower than an upper surface of the trench and a portion of the shield conductor exposed by the first insulating layer is incompletely oxidized, the gate conductor is located at both sides of the shield conductor which are not oxidized, including two portions separated from each other.
26. The method of claim 25, wherein a width of an upper section of the shield conductor between the gate conductors is less than a width of a lower section of the shield conductor.
27. The method as recited in claim 20, further comprising:
forming an interlayer dielectric layer positioned on the upper surface of the semiconductor substrate;
forming a gate metal electrode and a source metal electrode on the upper surface of the interlayer dielectric layer, and
a drain electrode is formed on a lower surface of the semiconductor substrate.
28. The method of claim 27, wherein forming the gate conductive channel comprises:
forming a contact hole extending from the upper surface of the interlayer dielectric layer to the gate conductor before forming the gate metal electrode; and
and filling metal in the contact hole.
29. The method of claim 20, wherein when the number of gate conductive channels is two, the two gate conductive channels are respectively in contact with the thicker portions of the two gate conductors.
30. A method according to claim 24 or 25, wherein the number of gate conductive channels is two, the two gate conductive channels being in contact with the two parts separately from each other.
31. The method as recited in claim 27, further comprising:
forming a body region of a second doping type extending from the upper surface of the semiconductor substrate to the inside of the semiconductor substrate at two sides of the groove, wherein the body region is adjacent to the groove;
forming a source region of a first doping type in the body region adjacent to the trench, and
a body contact region of a second doping type is formed in the body region.
32. The method of claim 31 further comprising forming a source region conductive via extending from an upper surface of the interlevel dielectric layer to the body contact region.
33. The method of claim 20, wherein the semiconductor base comprises a substrate of a first doping type and an epitaxial layer of the first doping type on the substrate, the trench being in the epitaxial layer.
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