CN102104040B - Semiconductor device with shallow-trench isolation structure and manufacturing method thereof - Google Patents
Semiconductor device with shallow-trench isolation structure and manufacturing method thereof Download PDFInfo
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- CN102104040B CN102104040B CN 200910261618 CN200910261618A CN102104040B CN 102104040 B CN102104040 B CN 102104040B CN 200910261618 CN200910261618 CN 200910261618 CN 200910261618 A CN200910261618 A CN 200910261618A CN 102104040 B CN102104040 B CN 102104040B
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Abstract
The invention provides a semiconductor device with a shallow-trench isolation structure (STI) and a manufacturing method thereof. The semiconductor device comprises a gate oxide layer and an SiN layer which are deposited on a silicon substrate, a groove etched on a wafer, a liner oxide layer, a liner SiN layer under partial extension line of the corner of the gate oxide layer, a thickened oxide layer outside the liner oxide layer above the liner SiN layer, and a high-density plasma (HDP) layer. Due to the protecting effect of the liner SiN layer to the silicon substrate, when a thickened oxide layer grows in a feed pipe, the silicon substrate inside cannot be consumed, so the characteristic dimension (CD) in an active region can be ensured to be invariant. By adopting the thickened oxide layer, the thickness of the oxide layer at the corner of the gate oxide layer can be improved. Meanwhile, the problems of performance shift in the conventional STI manufacturing process and reduced tolerance of a SiN photo window can be avoided.
Description
Technical field
The present invention relates to a kind of semiconductor device and manufacture method thereof, more specifically relate to a kind of semiconductor device and manufacture method thereof with shallow groove isolation structure.
Background technology
Shallow-trench isolation technology (hereinafter to be referred as STI) is the development along with the deep submicron integrated circuit technology, and a kind of emerging place isolation technology that produces.Have but on wafer, grow
During above gate oxide, the oxidated layer thickness of wafer gate oxide corner portions (corner is the gate oxide part adjacent with groove) will be lower than the oxidated layer thickness of active region (active area) flat part.As shown in Figure 1, the thickness when liner oxide (liner oxide) is
The time, the oxidated layer thickness of flat part has 15.3nm, and corner portions only have 10.7nm, is the former 70%.The phenomenon of this corner portions oxide layer attenuation easily causes the puncture of gate oxide, affects circuit reliability, and can reduce wafer through the time insulation breakdown performance (time dependent dielectric breakdown, TDDB).
But found through experiments, the oxide skin(coating) by the outside further growth at interior lining oxide layer thickens can solve the problem of corner portions oxide layer attenuation.The thickness of the oxide that covers when corner portions as shown in Figure 2, from
Be increased to
The time, the oxidated layer thickness of flat part is 13.9nm, corner portions be 15.6nm, be the former 110%, compare the trend that slight thickening is arranged, overcome defects.But when the oxide skin(coating) that growth thickens, consume the inner silicon chip of a part, the characteristic size (CD) of active region is dwindled, produce the problems such as voltage drift (performanceshift).If in the situation of figure (ADI) characteristic size that increases the photoresistance definition, keep the characteristic size of active region constant, can cause again the problem that SiN gold-tinted process volume (photo window) tolerance diminishes.
Summary of the invention
In order to overcome the problems referred to above and defective, the purpose of this invention is to provide a kind of semiconductor device with shallow groove isolation structure, this semiconductor device can at the bottom of improving the gate oxide corner portions in the oxide thickness, can not cause damage to silicon chip.
Semiconductor device with shallow groove isolation structure of the present invention, be included in the gate oxide and the SiN layer that deposit on the silicon chip, etched groove on wafer, interior lining oxide layer, with the dielectric material of filling at groove, also be included in the liner passivation layer of the corner portions located extended line below of gate oxide, and the oxide skin(coating) that thickens of lining oxide layer outside above the liner passivation layer in, the liner passivation layer is positioned at the groove inner surface with the oxide skin(coating) that thickens.
The purpose of liner passivation layer is the protective effect to silicon chip, when when advancing the oxide skin(coating) that boiler tube growth thickens, can not consume inner silicon chip, can guarantee that the characteristic size CD of active region can not change.At present passivation commonly used can be as liner passivation layer of the present invention, such as SiN, and AlN, nitrogen oxide etc.
Preferred as technique scheme, described liner passivation is liner SiN layer.
Preferred as technique scheme, described dielectric material is high-density plasma HDP layer.Preferred as technique scheme, the thickness of described liner SiN layer be 50～
Another object of the present invention provides a kind of method of making the chip architecture of above-mentioned shallow-trench isolation technology.
Manufacture method with semiconductor device of shallow groove isolation structure of the present invention comprises:
Step 1: provide a silicon chip, lining oxide layer and SiN layer on described substrate, forming successively;
Step 2: apply photoresistance, define pattern on photoresistance;
Step 3: etching forms groove at wafer, and removes photoresistance;
Step 4: lining oxide layer and liner passivation layer on top and groove, forming successively;
Step 5: apply photoresistance;
Step 6: photoresistance and liner passivation layer are removed in etching gradually, and the photoresistance to the groove is cut to and exposes the liner passivation layer;
Step 7: continue to be etched with remove gate oxide extended line top the liner passivation layer;
Step 8: the residual photoresistance in the groove is removed fully, made bottom portion of groove continue to remain with the liner passivation layer;
Step 9: the corner portions located at gate oxide forms the oxide skin(coating) that thickens;
Step 10: filled dielectric material on top and groove;
Step 11: unnecessary dielectric material is removed in chemico-mechanical polishing (STI CMP).
Compare with existing STI manufacture process, the present invention has mainly increased step 4-9, by depositing respectively liner passivation layer and photoresistance, and by etching away part liner passivation layer and photoresistance, is formed on the semiconductor device that bottom portion of groove remains with the liner passivation layer structure.This structure is owing to having the liner passivation layer to the protective effect of silicon chip, therefore when advancing the oxide skin(coating) that the boiler tube growth thickens, can not consume inner silicon chip, can guarantee that the characteristic size CD of active region can not change.
The present invention can improve the thickness of gate oxide corner portions oxide by cover the oxide skin(coating) that thickens in the gate oxide corner portions located.Also can not cause simultaneously voltage drift in the existing STI manufacture process, and cause the problem that SiN gold-tinted process volume (photo window) tolerance diminishes.
Description of drawings
Fig. 1 is that oxide skin(coating) is
The time gate oxide SEM figure;
Fig. 2 is that oxide skin(coating) is
The time gate oxide SEM figure;
Fig. 3 A-Fig. 3 H is the processing step flow chart of the preferred embodiments of the present invention.
Embodiment
Below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in further detail.For the person of ordinary skill in the field, from detailed description of the invention, above and other purpose of the present invention, feature and advantage will be apparent.
The processing step flow chart of the preferred embodiments of the present invention has the method for the semiconductor device of shallow groove isolation structure in the present embodiment shown in Fig. 3 A-Fig. 3 H, comprising:
Step 1 a: silicon chip 11 is provided, on described substrate, forms successively gate oxide 12 and SiN layer 13, adopt thermal oxidation method to form gate oxide 12, adopt chemical vapour deposition technique deposition SiN layer 13;
Step 2: apply photoresistance 14, define pattern on photoresistance, as shown in Figure 3A;
Step 3: etching forms groove at wafer, and removes photoresistance 14, shown in Fig. 3 B;
Step 4: lining oxide layer 15 and liner SiN layer 16 in forming successively on top and groove, shown in Fig. 3 C, the thickness of preferred liner oxide layer 16 is
The thickness of liner SiN layer 16 is
Step 5: apply photoresistance 104, shown in Fig. 3 D;
Step 6: by the formula of control dry ecthing, photoresistance 104 and liner SiN layer 16 are removed in dry ecthing gradually, and the photoresistance to the groove is cut to and exposes liner SiN layer, shown in Fig. 3 E;
Step 7: by the formula of control dry ecthing, continue dry ecthing with remove gate oxide extended line top liner SiN layer, the gate oxide extended line is the straight line that overlaps with the lowermost end of the gate oxide 12 of silicon chip 11 tops shown in dotted line X among Fig. 3 F;
Step 8: by plasma cleaning and acid tank, residual photoresistance in the groove is removed fully, make bottom portion of groove continue to remain with liner SiN layer, the liner SiN layer that remains is below the gate oxide extended line, and be positioned at the inner surface of groove, so that the corner portions located 12C of gate oxide 12 is only by interior lining oxide layer 15 coverings, shown in Fig. 3 F;
The liner SiN layer that remains can be below gate oxide extended line X any position.
Step 9: advance the oxide skin(coating) 105 that boiler tube thickens in the corner portions located 12C of gate oxide growth, so that the upper capped oxide thickness of final corner portions located 12C is
Stopping so that other place can not produce thick oxide layer of liner passivation layer, this oxide skin(coating) that thickens can guarantee that the oxidated layer thickness of gate oxide corner portions is suitable with the flat part, overcomes the phenomenon of corner portions oxide layer attenuation, shown in Fig. 3 G;
Step 10: adopt high density plasma deposition (HDP), fill oxide on top and groove;
Step 11: unnecessary oxide is removed in chemico-mechanical polishing (STI CMP).
The final chip architecture of the semiconductor device with shallow groove isolation structure that forms of making is shown in Fig. 3 H, include the gate oxide and the SiN layer that deposit on the silicon chip, etched groove on wafer, interior lining oxide layer, liner SiN layer below the corner portions located extended line of gate oxide, the oxide skin(coating) that thickens of lining oxide layer outside in above liner SiN layer, and high-density plasma HDP layer.Owing to liner SiN layer being arranged to the protective effect of silicon chip, therefore when advancing the oxide skin(coating) that the boiler tube growth thickens, can not consume inner silicon chip, can guarantee that the characteristic size CD of active region can not change.The present invention can improve the thickness of gate oxide corner portions oxide by cover the oxide skin(coating) that thickens in the gate oxide corner portions located.Also can not cause simultaneously in the existing STI manufacture process voltage drift and cause the problem that SiN gold-tinted process volume (photo window) tolerance diminishes.
Although; the present invention clearly demonstrates by above embodiment and accompanying drawing thereof; yet in the situation that do not deviate from spirit of the present invention and essence thereof; the person of ordinary skill in the field works as can make according to the present invention various corresponding variations and correction, but these corresponding variations and correction all should belong to the protection range of claim of the present invention.
Claims (8)
1. semiconductor device with shallow groove isolation structure, it is characterized in that, comprise silicon chip, the upper surface of described silicon chip deposits gate oxide, the upper surface of described gate oxide deposits the SiN layer, etching has the groove that is through in the described silicon chip on the described SiN layer, the top of the inner surface of described groove and described SiN layer all is formed with interior lining oxide layer, the outside of described interior lining oxide layer is formed with the liner passivation layer, described liner passivation layer is positioned at the below of extended line of the lowermost end of described gate oxide, the top of described liner passivation layer is formed with the oxide skin(coating) that thickens, described oxide skin(coating) is positioned at the outside of the lining oxide layer on the inner surface of described groove, and on the groove and interior lining oxide layer top all is filled with dielectric material.
2. the semiconductor device with shallow groove isolation structure as claimed in claim 1 is characterized in that, described liner passivation layer is liner SiN layer.
3. the semiconductor device with shallow groove isolation structure as claimed in claim 1 is characterized in that, described dielectric material is high-density plasma HDP layer.
4. the semiconductor device with shallow groove isolation structure as claimed in claim 2 is characterized in that, the thickness of described liner SiN layer is
5. described manufacture method with semiconductor device of shallow groove isolation structure of claim 1 comprises step:
Step 1: provide a silicon chip, lining oxide layer and SiN layer on described substrate, forming successively;
Step 2: apply photoresistance, define pattern on photoresistance;
Step 3: etching forms groove at wafer, and removes photoresistance;
Step 4: lining oxide layer and liner passivation layer on top and groove, forming successively;
Step 5: apply photoresistance;
Step 6: photoresistance and liner passivation layer are removed in etching gradually, and the photoresistance to the groove is cut to and exposes the liner passivation layer;
Step 7: continue to be etched with remove gate oxide extended line top the liner passivation layer;
Step 8: the residual photoresistance in the groove is removed fully, made bottom portion of groove continue to remain with the liner passivation layer;
Step 9: the corner portions located at gate oxide forms the oxide skin(coating) that thickens;
Step 10: filled dielectric material on top and groove;
Step 11: unnecessary dielectric material is removed in chemico-mechanical polishing.
6. the manufacture method with semiconductor device of shallow groove isolation structure as claimed in claim 5 is characterized in that, described liner passivation layer is liner SiN layer.
7. the manufacture method with semiconductor device of shallow groove isolation structure as claimed in claim 5 is characterized in that, described dielectric material is high-density plasma HDP layer.
8. the manufacture method with semiconductor device of shallow groove isolation structure as claimed in claim 6 is characterized in that, the thickness of described liner SiN layer is
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5387540A (en) * | 1993-09-30 | 1995-02-07 | Motorola Inc. | Method of forming trench isolation structure in an integrated circuit |
| KR20040046514A (en) * | 2002-11-27 | 2004-06-05 | 주식회사 하이닉스반도체 | Method for forming a isolation layer in semiconductor device |
| CN101075574A (en) * | 2007-06-12 | 2007-11-21 | 上海宏力半导体制造有限公司 | Method for producing shallow groove isolating structure of high-voltage assembly |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5387540A (en) * | 1993-09-30 | 1995-02-07 | Motorola Inc. | Method of forming trench isolation structure in an integrated circuit |
| KR20040046514A (en) * | 2002-11-27 | 2004-06-05 | 주식회사 하이닉스반도체 | Method for forming a isolation layer in semiconductor device |
| CN101075574A (en) * | 2007-06-12 | 2007-11-21 | 上海宏力半导体制造有限公司 | Method for producing shallow groove isolating structure of high-voltage assembly |
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Address after: 215123 333 Xinghua street, Suzhou Industrial Park, Jiangsu Patentee after: Warship chip manufacturing (Suzhou) Limited by Share Ltd Address before: 215025 Xinghua street, Suzhou Industrial Park, Suzhou, Jiangsu 333 Patentee before: Hejian Technology (Suzhou) Co., Ltd. |