CN106449362B - A method of improving stress memory technological effect - Google Patents
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- CN106449362B CN106449362B CN201610885707.4A CN201610885707A CN106449362B CN 106449362 B CN106449362 B CN 106449362B CN 201610885707 A CN201610885707 A CN 201610885707A CN 106449362 B CN106449362 B CN 106449362B
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- 238000000034 method Methods 0.000 title claims abstract description 28
- 230000000694 effects Effects 0.000 title claims abstract description 14
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 95
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 95
- 230000007704 transition Effects 0.000 claims abstract description 56
- 239000000758 substrate Substances 0.000 claims abstract description 27
- 239000004065 semiconductor Substances 0.000 claims abstract description 26
- 238000011065 in-situ storage Methods 0.000 claims abstract description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 10
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 claims description 7
- 238000005137 deposition process Methods 0.000 claims description 5
- 239000000377 silicon dioxide Substances 0.000 claims description 5
- 229910021529 ammonia Inorganic materials 0.000 claims description 3
- MROCJMGDEKINLD-UHFFFAOYSA-N dichlorosilane Chemical compound Cl[SiH2]Cl MROCJMGDEKINLD-UHFFFAOYSA-N 0.000 claims description 3
- 235000012239 silicon dioxide Nutrition 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims 1
- 238000000151 deposition Methods 0.000 abstract description 11
- 230000008021 deposition Effects 0.000 abstract description 8
- 238000010438 heat treatment Methods 0.000 abstract description 5
- 229920006395 saturated elastomer Polymers 0.000 abstract description 3
- 239000010408 film Substances 0.000 description 45
- 239000002253 acid Substances 0.000 description 5
- 125000004429 atom Chemical group 0.000 description 4
- 230000008602 contraction Effects 0.000 description 4
- 238000002360 preparation method Methods 0.000 description 3
- 208000037656 Respiratory Sounds Diseases 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 125000004435 hydrogen atom Chemical group [H]* 0.000 description 2
- 229910000069 nitrogen hydride Inorganic materials 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 206010011376 Crepitations Diseases 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 230000001737 promoting effect Effects 0.000 description 1
- 239000012495 reaction gas Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000007669 thermal treatment Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
- C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
- C23C16/34—Nitrides
- C23C16/345—Silicon nitride
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- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
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- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
- C23C16/52—Controlling or regulating the coating process
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/0228—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
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- H01L29/66409—Unipolar field-effect transistors
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Abstract
The present invention provides a kind of methods for improving stress memory technological effect, come to form transition silicon nitride film in patterned semiconductor substrate surface by using atomic layer in-situ deposition technique, then stress memory silicon nitride layer is formed on transition silicon nitride film, make full use of the surface saturated reaction of atomic layer in-situ deposition technology, and the feature that thickness is controllable and highly stable, to prepare with high-purity and highdensity transition silicon nitride film, even if can also realize good stepcoverage than high structure for vertical width, the transition silicon nitride film not will receive the influence of Post isothermal treatment and change stress value, so as to avoid the existing stress memory silicon nitride layer crack due to caused by significantly shrinking after the heat treatment, and then sour the problem of being peeled off side wall by crack hole.
Description
Technical field
The present invention relates to technical field of integrated circuits, and in particular to a method of improve stress memory technological effect.
Background technique
Stress memory technique (SMT) technique plays an important role for promoting NMOS device speed, and the technology is by big
It can change electron mobility in channel in 1Gpa tensile stress, to improve the driving current of NMOS device.Mature SMT at present
Technique is to carry out amorphizing ion injection after side wall has deposited to source, drain electrode, it is slow to have grown one layer of very thin silica
After rushing layer, high stress silicon nitride can be deposited using PECVD in whole wafer, then be removed by a photoetching and dry etching
The silicon nitride of PMOS area, while acid tank also inevitably washes off the silica buffer layer exposed, is next exactly high
Temperature annealing.
The preparation of usual high stress silicon nitride is using SiH4, NH3And N2By plasma enhanced chemical vapor depositing operation come real
Existing, preparation initial stage can be answered by changing the parameters such as reaction temperature (400-500 DEG C), gas flow, radio-frequency power to change height
H atom content and tensile stress size in power silicon nitride, the H atom content in usual high stress silicon nitride is low, and tensile stress is high.But
It is to be directed to 28nm and following CMOS chip, more stringent requirements are proposed to SMT technology for the processing procedure of Poly/SiON and HKMG,
Therefore in order to further decrease H content, tensile stress is improved, deposition plus ultraviolet light complicated technology are needed.Ultraviolet light work
The introduction of skill can interrupt original Si -- H bond and N-H key in silicon nitride, form stronger silazine link, but ultraviolet light work
Skill can bring risk, and this processing can make high stress silicon nitride film volume contraction, if high stress silicon nitride film is covered
Region have it is biggish protrusion or recess, it is easy in subsequent heat treatment technique these protrusion or recess will form and split
Line, once acid tank washes off the high stress silicon nitride film of SMT, acid can enter the region side wall (Spacer) by these crackles, into
And the problems such as causing side wall to peel off appearance, and then influence the device stabilization and manufacturing process of advanced process.
Summary of the invention
In order to overcome the above problems, the present invention is intended to provide it is a kind of improve stress memory technological effect method, to avoid
The contraction of high stress silicon nitride film.
In order to achieve the above object, the present invention provides a kind of methods for improving stress memory technological effect, comprising:
Step 01: a patterned semiconductor substrate is provided；Grid and side wall are formed on the patterned semiconductor substrate；
Step 02: one layer of transition silicon nitride is formed in the patterned semiconductor substrate surface using atom layer deposition process
Film；
Step 03: stress memory silicon nitride layer is formed on the transition silicon nitride film.
Preferably, the thickness of the transition silicon nitride film is less than the thickness of the stress memory silicon nitride layer.
Preferably, the transition silicon nitride film with a thickness of
Preferably, the reaction temperature of the transition silicon nitride film is greater than or equal to the anti-of the stress memory silicon nitride layer
Answer temperature.
Preferably, the reaction temperature of the transition silicon nitride film is 400~600 DEG C.
Preferably, tensile stress suffered by the transition silicon nitride film is less than suffered by the stress memory silicon nitride layer
Tensile stress.
Preferably, the content of the Si -- H bond in the transition silicon nitride film and N-H key is nitrogenized less than the stress memory
The content of Si -- H bond and N-H key in silicon layer.
Preferably, in the step 02, used radio-frequency power is 90~120W.
Preferably, the step 02 specifically includes: alternating be passed through dichlorosilane and ammonia, repeatedly recycle reaction in-situ to
Transition silicon nitride film is generated on a semiconductor substrate.
Preferably, in the step 02, before the semiconductor substrate surface forms one layer of transition silicon nitride film,
Further include: layer of silicon dioxide transition zone is formed in the patterned semiconductor substrate surface.
The method of improvement stress memory technological effect of the invention, comes by using atomic layer in-situ deposition technique in figure
Change semiconductor substrate surface formed transition silicon nitride film, make full use of atomic layer in-situ deposition technology surface saturated reaction,
And the feature that thickness is controllable and highly stable, to prepare with high-purity and highdensity transition silicon nitride film, i.e.,
Just good stepcoverage can also be realized than high structure for vertical width, it has been found that obtain using atomic layer in-situ deposition technology
The transition silicon nitride film stress with higher arrived, the transition silicon nitride film not will receive the shadow of Post isothermal treatment (RTA)
It rings and changes stress value, made after the heat treatment by significantly shrinking so as to avoid existing stress memory silicon nitride layer
At crack, and then acid the problem of being peeled off side wall by crack hole.Further, transition silicon nitride film is substantially all in 400-
Carried out between 600 DEG C, on the one hand reduce industry heat budget, second aspect within this temperature range in-situ deposition transition nitridation
Stress suffered by silicon thin film is tensile stress, the third aspect make obtained transition silicon nitride film have less Si -- H bond and
N-H key, to further avoid the generation of the above problem.Therefore, transition silicon nitride film can be thin with stress memory silicon nitride
Film complements each other, and for improving stress memory technique, solves crack problem.
Detailed description of the invention
Fig. 1 is the flow diagram of the method for the improvement stress memory technological effect of a preferred embodiment of the invention
Fig. 2-4 is each preparation step of the method for the improvement stress memory technological effect of a preferred embodiment of the invention
Schematic diagram
Specific embodiment
To keep the contents of the present invention more clear and easy to understand, below in conjunction with Figure of description, the contents of the present invention are made into one
Walk explanation.Certainly the invention is not limited to the specific embodiment, general replacement known to those skilled in the art
It is included within the scope of protection of the present invention.
Below in conjunction with attached drawing 1-4 and specific embodiment, invention is further described in detail.It should be noted that attached drawing is equal
The present embodiment is aided in illustrating to facilitate, clearly reach using very simplified form, using non-accurate ratio, and only
Purpose.
Referring to Fig. 1, a kind of method of improvement stress memory technological effect of the present embodiment, comprising:
Step 01: referring to Fig. 2, providing a patterned semiconductor substrate 01；
Specifically, being formed with grid 02 and side wall 03 on patterned semiconductor substrate 01；02 bottom of grid also has grid oxygen
Layer 04.Patterned semiconductor substrate 01 may include NMOS and PMOS.
Step 02: referring to Fig. 3, forming one layer of mistake on 01 surface of patterned semiconductor substrate using atom layer deposition process
Cross silicon nitride film 05；
Specifically, before 01 surface of semiconductor substrate forms one layer of transition silicon nitride film 05, firstly, graphical half
01 surface of conductor substrate forms layer of silicon dioxide transition zone (not shown), then re-forms transition silicon nitride film 05.
Here, it is alternately passed through dichlorosilane and ammonia into reaction chamber, recycles reaction in-situ repeatedly to serve as a contrast in semiconductor
Generate transition silicon nitride film 05 on bottom 01, transition silicon nitride film 05, be covered in the top of grid 02 and 03 surface of side wall and
Exposed 01 surface of semiconductor substrate.Used radio frequency when transition silicon nitride film 05 is prepared using atom layer deposition process
Power is 90~120W, and the reaction carries out at a lower temperature, and reaction temperature can be 400~600 DEG C；For example, can
To use TEL ALD board, radio-frequency power 100W, temperature is 550 DEG C, low temperature pre-deposition layerMistake
Cross silicon nitride (Si3N4) film 05, there is good shape-retaining ability to the side wall of NMOS and PMOS.Here, lower reaction temperature,
So that the stress that transition silicon nitride film 05 is subject to is tensile stress, and tensile stress suffered by transition silicon nitride film 05 is less than
Tensile stress suffered by subsequent stress memory silicon nitride layer 06 (as shown in Figure 4), Si -- H bond in transition silicon nitride film 05 and
The content of N-H key is less than the content of Si -- H bond and N-H key in stress memory silicon nitride layer 06 (as shown in Figure 4), to make
Cross transition of the silicon nitride film 05 as 01 surface of stress memory silicon nitride layer 06 (as shown in Figure 4) and patterned semiconductor substrate
When layer, contraction can be generated to avoid stress memory silicon nitride layer first, secondly, can also provide for patterned semiconductor substrate 01
High stress causes patterned semiconductor substrate to crack so that existing stress memory silicon nitride layer be avoided to generate contraction, after
Continuous acid enters the generation that side wall causes side wall spallation problems by crackle.
Here, the reaction temperature of transition silicon nitride film 05 can be greater than or equal to 06 (such as Fig. 4 of stress memory silicon nitride layer
It is shown) reaction temperature so that the surface saturated reaction of the patterned semiconductor substrate 01 in atom layer deposition process is more
Add sufficiently, so that transition silicon nitride film 05 has higher consistency and purity；In addition, the thickness of transition silicon nitride film 05
The thickness of stress memory silicon nitride layer 06 (as shown in Figure 4), the thickness and stress memory of transition silicon nitride film 05 can be less than
The thickness of silicon nitride layer 06 (as shown in Figure 4) should be designed as reasonable ratio, if the thickness of transition silicon nitride film 05 according to
It so will appear the existing above problem.Transition silicon nitride film 05 not only acts as the effect of deformation isolation, and transition silicon nitride
Film 05 and the collaboration (as shown in Figure 4) of stress memory silicon nitride layer 06, which are got up, applies stress to 01 surface of patterned semiconductor substrate
Effect, therefore, only the thickness of transition silicon nitride film 05 be less than stress memory silicon nitride layer 06 (as shown in Figure 4) thickness
When, it can be only achieved said effect, preferably, the ratio can be 1:30~1:4.
Step 03: referring to Fig. 4, forming stress memory silicon nitride layer 06 on transition silicon nitride film 05.
Specifically, here, in mistake under conditions of using plasma enhancing chemical vapor deposition process and ultraviolet light
It crosses deposition stress on silicon nitride film 05 and remembers silicon nitride layer 06, used reaction gas can be SiH4And NH3, reaction temperature
Degree can be 300~500 DEG C, and the heating temperature of ultraviolet light can be 350~400 DEG C,The stress memory of thickness
Silicon nitride layer 06, for example, reaction temperature is 400 DEG C, the heating temperature of ultraviolet light can be 385 DEG C, and deposition obtainsIt is thick
The stress memory silicon nitride layer 06 of degree.
It is then also possible to remove the stress memory silicon nitride layer 06 and transition silicon nitride film 05 of PMOS area, then to whole
A substrate carries out rapid thermal treatment, removes all stress memory silicon nitride layer 06 and transition silicon nitride film 05 later.
Although the present invention is disclosed as above with preferred embodiment, right embodiment is illustrated only for the purposes of explanation, and
It is non-to limit the present invention, those skilled in the art can make without departing from the spirit and scope of the present invention it is several more
Dynamic and retouching, the protection scope that the present invention is advocated should be subject to claims.
Claims (9)
1. a kind of method for improving stress memory technological effect characterized by comprising
Step 01: a patterned semiconductor substrate is provided；Grid and side wall are formed on the patterned semiconductor substrate；
Step 02: thin in the patterned semiconductor substrate surface one layer of transition silicon nitride of formation using atom layer deposition process
Film, the transition silicon nitride film not will receive the influence of Post isothermal treatment (RTA) and change stress value；
Step 03: stress memory silicon nitride layer is formed on the transition silicon nitride film, in the transition silicon nitride film
Content of the content of Si -- H bond and N-H key less than Si -- H bond and N-H key in the stress memory silicon nitride layer.
2. the method according to claim 1, wherein the thickness of the transition silicon nitride film is less than the stress
Remember the thickness of silicon nitride layer.
3. according to the method described in claim 2, it is characterized in that, the transition silicon nitride film with a thickness of
4. the method according to claim 1, wherein the reaction temperature of the transition silicon nitride film is higher than or waits
In the reaction temperature of the stress memory silicon nitride layer.
5. according to the method described in claim 4, it is characterized in that, the reaction temperature of the transition silicon nitride film be 400~
600℃。
6. according to the method described in claim 4, it is characterized in that, tensile stress suffered by the transition silicon nitride film is less than
Tensile stress suffered by the stress memory silicon nitride layer.
7. the method according to claim 1, wherein in the step 02, used radio-frequency power is 90~
120W。
8. the method according to claim 1, wherein the step 02 specifically includes: alternating is passed through dichlorosilane
And ammonia, recycle reaction in-situ repeatedly to generate transition silicon nitride film on a semiconductor substrate.
9. the method according to claim 1, wherein in the step 02, in the semiconductor substrate surface
It is formed before one layer of transition silicon nitride film, further includes: form layer of silicon dioxide in the patterned semiconductor substrate surface
Transition zone.
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| CN107564800B (en) * | 2017-08-31 | 2020-02-18 | 长江存储科技有限责任公司 | Preparation method of silicon nitride layer |
| KR20190062695A (en) * | 2017-11-29 | 2019-06-07 | 엘지디스플레이 주식회사 | Thin film trnasistor, method for manufacturing the same and display device comprising the same |
| JP2019204864A (en) * | 2018-05-23 | 2019-11-28 | 東芝メモリ株式会社 | Semiconductor storage device |
| CN110911284A (en) * | 2019-11-25 | 2020-03-24 | 上海华力集成电路制造有限公司 | Device NBTI lifetime improvement method and structure |
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| CN102437119A (en) * | 2011-08-15 | 2012-05-02 | 上海华力微电子有限公司 | Method for improving effect of stress memory technology |
| CN102446918A (en) * | 2011-08-17 | 2012-05-09 | 上海华力微电子有限公司 | Structure for preventing etch stop layer from cracking and method for forming structure |
| CN104637992A (en) * | 2013-11-13 | 2015-05-20 | 上海和辉光电有限公司 | Gate insulation layer with improved etching angle and formation method of gate insulation layer with improved etching angle |
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