CN102479755B - CMOS (Complementary Metal Oxide Semiconductor) device and manufacturing method thereof - Google Patents
CMOS (Complementary Metal Oxide Semiconductor) device and manufacturing method thereof Download PDFInfo
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- CN102479755B CN102479755B CN201010567602.7A CN201010567602A CN102479755B CN 102479755 B CN102479755 B CN 102479755B CN 201010567602 A CN201010567602 A CN 201010567602A CN 102479755 B CN102479755 B CN 102479755B
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Abstract
The invention provides a CMOS (Complementary Metal Oxide Semiconductor) device and a manufacturing method thereof. The CMOS device comprises an NMOS (N-channel Metal Oxide Semiconductor) transistor and a PMOS (P-channel Metal Oxide Semiconductor) transistor, and stress side walls are formed at two sides of gates of the NMOS transistor and the PMOS transistor; and the stress side wall of the NMOS transistor is provided with tensile stress, and the stress side wall of the PMOS transistor is provided with compressive stress. When the CMOS device is manufactured, stress is remembered in a channel region of the NMOS transistor by using a stress memory technique, and meanwhile, the stress side walls are formed on the gates of the NMOS transistor and the PMOS transistor, thus, a favorable stress effect is provided, and the structure of the device is simplified.
Description
Technical field
The present invention relates to technical field of semiconductors, more specifically, the present invention relates to a kind of cmos device and preparation method thereof that have employed strain memory technique.
Background technology
In semiconductor device especially MOS device, a kind of main method improving the switching frequency of field-effect transistor improves drive current, and the main path improving drive current improves carrier mobility.Existing a kind of technology improving field-effect transistor carrier mobility is strain memory technique (StressMemorization Technique, be called for short SMT), form stable stress by the channel region of scene effect transistor, improve the carrier mobility in raceway groove.Usual tensile stress can make the molecules align in channel region more loose, thus improves the mobility of electronics, is applicable to nmos pass transistor; And compression stress makes the molecular arrangement in channel region more tight, contribute to the mobility improving hole, be applicable to PMOS transistor.
Described strain memory technique SMT specifically comprises employing S/D annealing process, make stress cap layer (Activation Capping Layer, be called for short ACL) bottom polysilicon gate recrystallization, make the stress that stress cap layer brings out, remember in MOS device, cause the electrical property of MOS device to improve 6 ~ 10%.And for PMOS transistor and nmos pass transistor to the requirement of different stress, optionally local train can also be carried out in MOS device, reach the object of the electrical property improving MOS device.
See the paper " Stress Memorization Technique (SMT) by Selectively Strained-Nitride Capping for Sub-65nm High-performanceStrained-Si Device Application " (coming from 2004 " Symposium on VLSI TechnologyDigest of Technical Papers ") that the people such as Chien-Hao Chen deliver, describe a kind of manufacturing process of cmos device of typical strain memory effect, generalized section as shown in Figures 1 to 8.
As shown in Figure 1, first provide semiconductor base 10, semiconductor base 10 is formed the nmos pass transistor N1 by shallow trench 11 insulation isolation and PMOS transistor N2, and the grid of described nmos pass transistor N1 and PMOS transistor N2 has gate lateral wall.
As shown in Figure 2, the first stressor layers 101 is formed on the surface of described nmos pass transistor N1 and PMOS transistor N2, the material of described first stressor layers 101 can be SiN, can be formed by thermal drivers chemical vapour deposition (CVD) (TDCVD) or plasma reinforced chemical vapour deposition (PECVD).By changing parameter (the such as reacting gas H of described chemical vapour deposition (CVD)
2content), stress types and the stress intensity of described first stressor layers 101 can be regulated.When the stress types supposing described first stressor layers 101 is tensile stress, above-mentioned tensile stress acts on the channel region of nmos pass transistor N1, and pair nmos transistor N1 is produced beneficial effect.
As shown in Figure 3, adopt photoetching process to carry out selective etch, remove the part that the first stressor layers 101 is positioned at PMOS transistor N2 surface, and retain the part being positioned at nmos pass transistor N1 surface.
As shown in Figure 4, spike annealing (Spike anneal) is carried out to the semiconductor structure of above-mentioned formation.In described spike anneal process, because the first stressor layers 101 is only positioned at the surface of nmos pass transistor N1, therefore the tensile stress of described first stressor layers 101 will be remembered in the channel region of nmos pass transistor N1, thus improves the carrier mobility of nmos pass transistor N1 channel region.
As shown in Figure 5, wet etching is adopted to remove the first stressor layers 101, then the second stressor layers 102 is formed on the surface of described nmos pass transistor N1 and PMOS transistor N2, the material of described second stressor layers 102 also can be SiN, can be formed by thermal drivers chemical vapour deposition (CVD) (TDCVD) or plasma reinforced chemical vapour deposition (PECVD).Regulate stress types and the stress intensity of described second stressor layers 102, make described second stressor layers 102 be compression stress.Above-mentioned compression stress acts on the channel region of PMOS transistor N2, and pair pmos transistor N2 is produced beneficial effect.
As shown in Figure 6, adopt photoetching process to carry out selective etch, remove the part that the second stressor layers 102 is positioned at nmos pass transistor N1 surface, and retain the part being positioned at PMOS transistor N2 surface.
Because annealing process can make the compression stress of stressor layers diminish, therefore usually can't carry out spike annealing, the stressor layers of PMOS transistor surf zone will be retained, and can not remember in the channel region of PMOS transistor.
As shown in Figure 7, the semicon-ductor structure surface formed in above-mentioned steps forms etching barrier layer 103.The material of described etching barrier layer 103 can be also SiN, SiON etc., can be formed by chemical vapour deposition (CVD).
As shown in Figure 8, before-metal medium layer 104 is formed on the surface of described etching barrier layer 103.And contact hole is formed in before-metal medium layer 104, make the interconnection line of drawing source-drain electrode or grid.
There are the following problems for the manufacturing process of the cmos device of existing strain memory effect: although spike annealing can by the stress memory of strained layer in bottom transistor channel region, stress intensity is less than the stress produced in channel region when retaining strained layer usually.And if retain the making that thicker strained layer easily affects subsequent technique such as contact hole.
Summary of the invention
The problem that the present invention solves is to provide a kind of cmos device and preparation method thereof, improves the understrressing problem of existing strain memory technique.
The manufacture method of a kind of cmos device provided by the invention, comprising:
There is provided semiconductor structure, described semiconductor structure comprises nmos pass transistor and PMOS transistor;
First medium layer and the first stressor layers is formed successively at described semicon-ductor structure surface;
Remove the part that described first stressor layers is positioned at PMOS transistor region;
Spike annealing is carried out to the semiconductor structure of above-mentioned formation;
Etch described first stressor layers, form the first stress sidewall in the grid both sides of nmos pass transistor;
Second dielectric layer and the second stressor layers is formed successively at the semicon-ductor structure surface of above-mentioned formation;
Remove the part that described second stressor layers is positioned at nmos transistor region;
Etch described second stressor layers, the grid of PMOS transistor is formed the second stress sidewall.
Optionally, the material of described first medium layer is silica, and adopt chemical vapour deposition (CVD) to be formed, thickness is
Optionally, the stress types of described first stressor layers is tensile stress.The material of described first stressor layers is silicon nitride, and adopt chemical vapour deposition (CVD) to be formed, thickness is
the stress intensity of described first stressor layers is 0.6GPa ~ 1.5GPa.The parameter of described spike annealing is: annealing temperature 950 DEG C ~ 1100 DEG C, annealing time 1s-2.5s.The width of described first stress sidewall is
optionally, the material of described second dielectric layer is silica, and adopt chemical vapour deposition (CVD) to be formed, thickness is
Optionally, the stress types of described second stressor layers is compression stress.The material of described second stressor layers is silicon nitride, and adopt chemical vapour deposition (CVD) to be formed, thickness is
the stress intensity of described second stressor layers is-2.5GPa ~-3.5GPa.The width of described second stress sidewall is
Cmos device of the present invention, comprises nmos pass transistor and PMOS transistor, and grid both sides are formed with stress sidewall; The stress sidewall of described nmos pass transistor has tensile stress, and the stress sidewall of PMOS transistor has compression stress.
Compared with prior art, the present invention has the following advantages: employing strain memory technique by stress memory while nmos pass transistor channel region, the grid of nmos pass transistor and PMOS transistor forms stress sidewall, provides good stress effect, and simplify device architecture.
Accompanying drawing explanation
By the more specifically explanation of the preferred embodiments of the present invention shown in accompanying drawing, above-mentioned and other object of the present invention, Characteristics and advantages will be more clear.Parts same as the prior art in accompanying drawing employ identical Reference numeral.Accompanying drawing not drawn on scale, focus on purport of the present invention is shown.In the accompanying drawings for clarity sake, the size in layer and region is exaggerated.
Fig. 1 to Fig. 8 is the process for fabrication of semiconductor device schematic diagram of existing strain memory effect;
Fig. 9 is the method, semi-conductor device manufacturing method flow chart of strain memory effect of the present invention;
Figure 10 to Figure 20 is the generalized section of embodiment of the present invention method, semi-conductor device manufacturing method.
Embodiment
For enabling above-mentioned purpose of the present invention, feature and advantage become apparent more, are described in detail the specific embodiment of the present invention below in conjunction with accompanying drawing.
Set forth a lot of detail in the following description so that fully understand the present invention, but the present invention can also adopt other to be different from alternate manner described here to implement, therefore the present invention is not by the restriction of following public specific embodiment.
Just as described in the background section, the stressor layers on existing strain memory technique meeting removal devices surface, its stress effect is limited.
For the problems referred to above, the present inventor provides a kind of manufacture method of semiconductor device, utilizes sidewall etching technics to etch described stressor layers, transistor gate is formed stress sidewall, effectively can improve the stress effect of device, and simplify device architecture.
With reference to figure 9, show the manufacture method flow process of the semiconductor device of strain memory effect of the present invention, basic step comprises:
Perform step S101, provide semiconductor structure, described semiconductor structure comprises nmos pass transistor and PMOS transistor;
Concrete, described semiconductor structure comprises nmos pass transistor and PMOS transistor.Owing to completing the making of source-drain area; for protecting the insulative sidewall of grid to remove in advance in plasma doping technique in above-mentioned nmos pass transistor or PMOS transistor; to avoid in manufacture method of the present invention, affect the pattern of stress sidewall and the integral thickness of sidewall.
Perform step S102, form first medium layer and the first stressor layers successively at described semicon-ductor structure surface; Described first medium layer can improve the adhesiveness between the first stressor layers and the structure such as base semiconductor substrate, grid, strengthens stress effect.The stress types of described first stressor layers should be tensile stress.
Perform step S103, remove the part that described first stressor layers is positioned at PMOS transistor region; Spike annealing is carried out to the semiconductor structure of above-mentioned formation;
Concrete, can photoetching process be adopted, utilize photoresist to stop nmos transistor region, then remove by selective etch the part that the first stressor layers is positioned at PMOS transistor region.Again by spike annealing, by the stress memory of the first stressor layers in the channel region of nmos pass transistor.
Perform step S104, etch described first stressor layers, the grid of nmos pass transistor is formed the first stress sidewall;
Concrete, can sidewall forming processes be adopted, plasma etching is carried out to the first stressor layers.While formation first stress sidewall, remove the remainder of the first stressor layers.
Perform step S105, form second dielectric layer and the second stressor layers successively at the semicon-ductor structure surface of above-mentioned formation; Second stressor layers and the first stress sidewall spacers can be opened by described second dielectric layer, and protect described first stress sidewall not by the impact of follow-up selective etch.The stress types of described second stressor layers should be compression stress.
Perform step S106, remove the part that described second stressor layers is positioned at nmos transistor region;
Concrete, can photoetching process be adopted, utilize photoresist to stop PMOS transistor region, then remove by selective etch the part that the second stressor layers is positioned at nmos transistor region.
Perform step S107, etch described second stressor layers, the grid of PMOS transistor is formed the second stress sidewall.
Equally, adopt sidewall forming processes, plasma etching is carried out to the second stressor layers, while formation second stress sidewall, removes the remainder of the second stressor layers.
After above-mentioned steps, just form semiconductor device of the present invention.In described semiconductor device, the grid of nmos pass transistor and PMOS transistor all defines the side wall construction of compound.Wherein the compound side wall construction of nmos pass transistor comprises first medium layer, the first stress sidewall and second dielectric layer successively from grid; And the compound side wall construction of PMOS transistor comprises first medium layer, second dielectric layer and the second stress sidewall successively from grid.Above-mentioned stress sidewall has good stress effect to corresponding transistor area.Compared with the semiconductor device remaining with stressor layers, stressor layers is integrated in gate lateral wall, thus further simplify device architecture.
Figure 10 to Figure 20 shows each production phase generalized section of a specific embodiment of manufacturing method of semiconductor device of the present invention.
As shown in Figure 10, provide semiconductor structure, described semiconductor structure is cmos device.Described cmos device comprises and is formed at Semiconductor substrate 200, and by the mutually isolated nmos pass transistor M1 of shallow trench and PMOS transistor M2.Wherein the grid 201 of nmos pass transistor M1 and the grid 202 of PMOS transistor M2 are exposed to the surface of Semiconductor substrate 200, and make stress sidewall for the ease of subsequent technique, can remove for the protection of the insulative sidewall of grid when carrying out source-drain electrode doping.
As shown in figure 11, first medium layer 301 and the first stressor layers 401 is deposited successively on the surface of above-mentioned cmos device.
The material of described first medium layer 301 can be silica, and the material of the first stressor layers 401 can be silicon nitride, all can be formed by chemical vapor deposition method.Because the first medium layer 301 of described silica material is for the adhesiveness between the grid of the first stressor layers 401 and polysilicon material of improving silicon nitride material and single-crystal semiconductor substrate, make its stress effect preferably can act on the cmos device of bottom.
In the present embodiment, the thickness of described first medium layer 301 is
the thickness of the first stressor layers 401 is
stress types is tensile stress, and stress intensity is 0.6GPa ~ 1.5GPa (supposing that tensile stress is direct stress).
As shown in figure 12, by coating photoresist, and carry out exposure imaging, nmos transistor region is formed the first photoresist mask 501, and exposes PMOS transistor region.Then on PMOS transistor region, carry out selective etch, remove the first stressor layers 401 in this region.In the present embodiment, hot phosphoric acid can be adopted to carry out wet etching, remove the first stressor layers 401 of silicon nitride material.Described PMOS transistor, owing to being subject to the protection of the first medium layer 301 of silica material, can't be subject to the impact of wet etching.
As shown in figure 13, adopt cineration technics to remove the first photoresist mask 501 be covered on nmos transistor region, then spike annealing is carried out to above-mentioned semiconductor structure, by the stress memory of the first stressor layers 401 in the nmos pass transistor channel region of bottom.In the present embodiment, the parameter of described spike annealing can be: annealing temperature 950 DEG C ~ 1100 DEG C, annealing time 1s-2.5s.
As shown in figure 14, after spike annealing terminates, again by coating photoresist, and carry out exposure imaging, PMOS transistor region is formed the second photoresist mask 502, and exposes nmos transistor region.
As shown in figure 15, etch the first stressor layers 401 in described nmos transistor region, the grid 201 of nmos pass transistor M1 is formed the first stress sidewall 601.
In the present embodiment, conventional sidewall forming processes can be adopted, plasma etching is carried out to the first stressor layers 401.When after formation first stress sidewall 601, the first stressor layers 401 being positioned at grid 201 top and semiconductor substrate also etches removal thereupon.The width of described first stress sidewall 601 depends on the former thickness of the first stressor layers 401 and the time of plasma etching, and scope can be
As shown in figure 16, cineration technics is adopted to remove the second photoresist mask 502 be covered on PMOS transistor region.Second dielectric layer 302 and the second stressor layers 402 is formed successively on the surface of above-mentioned semiconductor structure.
The material of described second dielectric layer 302 can be silica, and the material of the second stressor layers 402 can be silicon nitride, all can be formed by chemical vapor deposition method.In the present embodiment, the thickness of described second dielectric layer 302 is
the thickness of the second stressor layers 402 is
stress types is compression stress, and stress intensity is-2.5GPa ~-3.5GPa.Because described second dielectric layer 302 is overlying on the surface of first medium layer 301 and the first stress sidewall 601, therefore can material is identical but the second stressor layers 402 that stress types is contrary and the first stress sidewall 601 spaced apart.
As shown in figure 17, by coating photoresist, and carry out exposure imaging, PMOS transistor region forms the 3rd photoresist mask 503, and exposes nmos transistor region.Then on nmos transistor region, carry out selective etch, remove the second stressor layers 402 in this region.In the present embodiment, hot phosphoric acid can be adopted to carry out wet etching, remove the second stressor layers 402 of silicon nitride material.Described first stress sidewall 601, owing to being subject to the protection of second dielectric layer 402, can't be subject to the impact of above-mentioned wet etching.
It is pointed out that the second stressor layers 402 of PMOS transistor region surface, do not need to carry out spike annealing.This is the compression stress size easily weakened due to annealing process in the second stressor layers 402, therefore carries out the strain memory technique in PMOS transistor region, relative to acquired stress effect, loses more than gain.
As shown in figure 18, cineration technics is adopted to remove the 3rd photoresist mask 503 be covered on PMOS transistor region.Again by coating photoresist, and carry out exposure imaging, nmos transistor region forms the 4th photoresist mask 504, and exposes PMOS transistor region.
As shown in figure 19, etch the second stressor layers 402 in described PMOS transistor region, the grid 202 of PMOS transistor M2 is formed the second stress sidewall 602.
In the present embodiment, conventional sidewall forming processes can be adopted, plasma etching is carried out to the second stressor layers 402.When after formation second stress sidewall 602, the second stressor layers 402 being positioned at grid 202 top and semiconductor substrate surface also etches removal thereupon.The width of described second stress sidewall 602 depends on the former thickness of the second stressor layers 402 and the time of plasma etching, and scope can be
As shown in figure 20, cineration technics is adopted to remove described 4th photoresist mask 504.So far cmos device of the present invention is just defined.
In above-mentioned cmos device, the compound sidewall of nmos pass transistor grid 201 comprises first medium layer 301, first stress sidewall 601 and second dielectric layer 302 successively from grid, define oxide-nitride-oxide (ONO) compound side wall construction, wherein silicon nitride layer has tensile stress.And the compound sidewall on PMOS transistor grid 202 comprises first medium layer 301, second dielectric layer 302 and the second stress sidewall 602 successively from grid, because first medium layer 301 and second dielectric layer 302 are in fact materials of the same race, therefore form silicon oxide-silicon nitride (O-N) compound side wall construction, wherein silicon nitride layer has compression stress.Although the structure of the grid compound sidewall in territory, above-mentioned different crystal area under control is different, gross thickness is still consistent.
In addition, because PMOS transistor region does not adopt strain memory technique, and the second stress sidewall 602 is spaced two layer medium layer with the channel region of PMOS transistor.Therefore usual, the stress intensity of the second stress sidewall 602 can be made to be greater than the first stress sidewall 601, corresponding stress effect could be obtained.
To sum up described in embodiment, stressor layers is integrated in gate lateral wall by the present invention, thus obtaining good stress effect simultaneously, not affecting the size of device, simplifying device architecture.Foregoing invention thought can be widely used in the manufacture craft of various cmos device.Such as in other embodiments, the stress sidewall production order of conversion nmos pass transistor and PMOS transistor is also feasible.
Although the present invention discloses as above with preferred embodiment, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (15)
1. a manufacture method for cmos device, is characterized in that, comprising:
There is provided semiconductor structure, described semiconductor structure comprises nmos pass transistor and PMOS transistor;
The first medium layer and the first stressor layers that cover described nmos pass transistor and PMOS transistor is formed successively at described semicon-ductor structure surface;
Remove the part that described first stressor layers is positioned at PMOS transistor region;
After removal part first stressor layers, spike annealing is carried out to the semiconductor structure of above-mentioned formation;
Etch described first stressor layers, remove the first stressor layers be positioned in nmos pass transistor top portions of gates and Semiconductor substrate, form the first stress sidewall in the grid both sides of nmos pass transistor, and retain the first medium layer being positioned at described nmos transistor region and PMOS transistor region;
The second dielectric layer and the second stressor layers that cover described nmos pass transistor and PMOS transistor is formed successively on the surface of described first stress sidewall and first medium layer;
Remove the part that described second stressor layers is positioned at nmos transistor region;
Etch described second stressor layers, remove the second stressor layers be positioned in PMOS transistor top portions of gates and Semiconductor substrate, form the second stress sidewall in the grid both sides of PMOS transistor, and retain the second dielectric layer being positioned at described nmos transistor region and PMOS transistor region;
At nmos transistor region, be positioned at the first medium layer on gate lateral wall, the first stress sidewall and described second dielectric layer successively and form compound side wall construction; In described PMOS transistor region, be positioned at the first medium layer on gate lateral wall, second dielectric layer and the second stress sidewall successively and form compound side wall construction;
Wherein, the stress intensity of described second stress sidewall is greater than the stress intensity of described first stress sidewall, and the stress intensity of described first stressor layers is 0.6GPa ~ 1.5GPa, and the stress intensity of described second stressor layers is-2.5GPa ~-3.5GPa.
2. manufacture method as claimed in claim 1, it is characterized in that, the material of described first medium layer is silica, and adopt chemical vapour deposition (CVD) to be formed, thickness is
3. manufacture method as claimed in claim 1, it is characterized in that, the stress types of described first stressor layers is tensile stress.
4. manufacture method as claimed in claim 3, it is characterized in that, the material of described first stressor layers is silicon nitride, and adopt chemical vapour deposition (CVD) to be formed, thickness is
5. manufacture method as claimed in claim 1, it is characterized in that, the parameter of described spike annealing is: annealing temperature 950 DEG C ~ 1100 DEG C, annealing time 1s-2.5s.
6. manufacture method as claimed in claim 5, it is characterized in that, the width of described first stress sidewall is
7. manufacture method as claimed in claim 1, it is characterized in that, the material of described second dielectric layer is silica, and adopt chemical vapour deposition (CVD) to be formed, thickness is
8. manufacture method as claimed in claim 1, it is characterized in that, the stress types of described second stressor layers is compression stress.
9. manufacture method as claimed in claim 8, it is characterized in that, the material of described second stressor layers is silicon nitride, and adopt chemical vapour deposition (CVD) to be formed, thickness is
10. manufacture method as claimed in claim 9, it is characterized in that, the width of described second stress sidewall is
The cmos device that 11. 1 kinds of manufacture methods as arbitrary in claim 1 ~ 10 are formed, comprise nmos pass transistor and PMOS transistor, it is characterized in that, grid both sides are formed with stress sidewall; The stress sidewall of described nmos pass transistor has tensile stress, and the stress sidewall of PMOS transistor has compression stress; The stress sidewall of described nmos pass transistor comprises the first compound sidewall be positioned on described nmos pass transistor grid, and described first compound sidewall comprises first medium layer, the first stress sidewall and second dielectric layer successively from grid; The stress sidewall of PMOS transistor comprises the second compound sidewall be positioned on described PMOS transistor grid, and described second compound sidewall comprises first medium layer, second dielectric layer and the second stress sidewall successively from grid.
12. cmos devices as claimed in claim 11, is characterized in that, the material of described first stress sidewall is silicon nitride, and thickness is
stress intensity is 0.6GPa ~ 1.5GPa.
13. cmos devices as claimed in claim 11, is characterized in that, the material of described second stress sidewall is silicon nitride, and thickness is
stress intensity is-2.5GPa ~-3.5GPa.
14. cmos devices as claimed in claim 11, is characterized in that, the material of described first medium layer is silica, and thickness is
15. cmos devices as claimed in claim 11, is characterized in that, the material of described second dielectric layer is silica, and thickness is
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| CN101087001A (en) * | 2006-06-05 | 2007-12-12 | 台湾积体电路制造股份有限公司 | MOS element and semiconductor structure |
| CN101257022A (en) * | 2007-02-26 | 2008-09-03 | 联华电子股份有限公司 | Semiconductor component and its manufacturing method as well as method for enhancing film layer stress |
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| CN101740620B (en) * | 2008-11-24 | 2012-05-16 | 中芯国际集成电路制造(北京)有限公司 | Semiconductor device with grid side wall layer and forming method thereof |
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| CN101257022A (en) * | 2007-02-26 | 2008-09-03 | 联华电子股份有限公司 | Semiconductor component and its manufacturing method as well as method for enhancing film layer stress |
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Effective date of registration: 20121101 Address after: 201203 Shanghai City, Pudong New Area Zhangjiang Road No. 18 Applicant after: Semiconductor Manufacturing International (Shanghai) Corporation Applicant after: Semiconductor Manufacturing International (Beijing) Corporation Address before: 201203 Shanghai City, Pudong New Area Zhangjiang Road No. 18 Applicant before: Semiconductor Manufacturing International (Shanghai) Corporation |
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