JP2000036593A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent dopants from being mutually diffused via a metal silicide layer, and to prevent the characteristics of a transistor from being deteriorated by inserting a compound thin film being formed of a metal thin film and a foundation, lower-layer electrode layer between the gate electrode layer of a barrier metal layer and a lower-layer gate electrode layer of a side near a semiconductor substrate. SOLUTION: A gate electrode and a side wall 12 are used as a mask in addition to a resist film for covering an n-channel MOSFET, and As is injected to the n channel MOSFET. Boron is injected to a p-channel MOSFET, and a source region 13S and a drain region 13D with a high concentration of impurity in LDD structure in the n-channel MOSFET are formed. A source region 14S with a high concentration of impurity in LDD structure in the p-channel MOSFET and a drain region 14D with a high concentration of impurity in LDD structure are formed. A Ti thin film of the compound of metal with a high melt point and a four-group element on polysilicon gate electrodes 6 and 7 in the n and p-channel MOSFETs turns to a Ti silicide thin film 15.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device capable of operating at a very high speed by employing a structure capable of reducing the resistance of an electrode.

2. Description of the Related Art In semiconductor devices, high integration has been achieved even now.
Because of the trend toward higher densities, efforts are being made to further reduce the size of the device, but when the size of the device is reduced, the problem always arises is the increase in the resistance of the electrodes. If this is not solved, the operating speed of the semiconductor device will decrease, so the present invention discloses one means for solving this problem.

[0003]

2. Description of the Related Art Generally, a MOSFET (metal oxide) is used.
xide semiconductor field
The polymetal electrode in the effect transistor has a configuration of polysilicon / barrier metal / pure metal.

In this configuration, the sheet resistance is kept low by the pure metal layer on the outermost surface, and TiN or WN
The barrier metal layer made of such as prevents the polysilicon layer and the pure metal layer from reacting.

If the polysilicon layer and the pure metal layer react with each other to form silicide, not only the resistance value increases, but also the gate dopant moves through the silicide layer in a later heat treatment step. The transistor characteristics deteriorate.

FIG. 9 shows a CMOS (complementary) model which is a model for explaining the movement of a gate dopant.
metal oxide semiconductor
2A is a cutaway side view of a main part showing r), FIG. 2A is a cutaway side view of a main part along a channel length direction, and FIG. .

In the figure, 1 is a p-type silicon substrate, 2 is a p-type well, 3 is an n-type well, 4 is an STI (shall)
An element isolation insulating film formed by ow trench isolation, 5 is a gate insulating film, 6 is an n-type polysilicon gate electrode layer in an n-channel MOSFET, 7 is a p-type polysilicon gate electrode in a p-channel MOSFET. The gate electrode layer, 8 is a tungsten silicide (WSi ₂ ) gate electrode layer, and 9S is an n-channel MOSF
Low impurity concentration source region of LDD structure in ET, 9
D is a low impurity concentration drain region having an LDD structure in an n-channel MOSFET, and 11S is a p-channel MOSFET.
Low impurity concentration source region of LDD structure at T, 11
D is a low impurity concentration drain region having an LDD structure in a p-channel MOSFET, 12 is a side wall, 13
S is a high impurity concentration source region having an LDD structure in an n-channel MOSFET, and 13D is an n-channel MOSFET.
High impurity concentration drain region of LDD structure in
S is a high impurity concentration source region having an LDD structure in a p-channel MOSFET, and 14D is a p-channel MOSFET.
2 shows a high impurity concentration drain region having an LDD structure in FIG.

The gate electrode GN in the n-channel MOSFET is constituted by the polysilicon gate electrode layer 6 and the tungsten silicide gate electrode layer 8 in the n-channel MOSFET.
The p-channel MO with the polysilicon gate electrode layer 7 and the tungsten silicide gate electrode layer 8 at T
A gate electrode GP in the SFET is formed.

As is generally known, when a pure metal layer is directly grown on a polysilicon layer, the two react in a heat treatment step to form a metal silicide layer.

The tungsten silicide gate electrode layer 8 shown in FIG. 9 is formed by a reaction between the polysilicon layers constituting the polysilicon gate electrode layers 6 and 7 and the tungsten layer. As is known, a tungsten silicide film is directly formed by a CVD method or a sputtering method.

In general, as dopants move easily through the tungsten silicide at elevated temperatures, as shown, the dopant source, ie, the polysilicon gate in an n-channel MOSFET, is shown. When the electrode layer 6 and the polysilicon gate electrode layer 7 in the p-channel MOSFET are close to each other, the respective dopants easily move through the tungsten silicide gate electrode layer 8.

FIG. 10 is an enlarged cutaway side view of the essential part of FIG. 9B, and the same symbols as those used in FIG. 9 represent the same parts or have the same meanings. Do

In the manufacturing process of the semiconductor device, it is unavoidable that there is a step that requires heating after forming the gate. At this time, an n-type polysilicon gate electrode layer in the n-channel MOSFET is required. The phosphorus (P) contained in 6 easily moves to the p-type polysilicon gate electrode layer 7 in the p-channel MOSFET via the tungsten silicide gate electrode layer 8, and conversely, to the p-channel MOSFET. The boron (B) contained in the polysilicon gate electrode layer 7 easily moves through the tungsten silicide gate electrode layer 8 to the polysilicon gate electrode layer 6 in the n-channel MOSFET. Therefore, the characteristics of the CMOS deteriorate.

In order to solve such a problem, in the prior art, a barrier metal layer such as TiN is interposed between the polysilicon layer and the pure metal layer to suppress the generation of metal silicide. is there.

However, in such a configuration, the contact resistance between the polysilicon layer and the barrier metal layer increases, so that the high-speed operation of the MOSFET is hindered.

[0016]

SUMMARY OF THE INVENTION According to the present invention, the contact resistance between the lower gate electrode layer and the barrier metal layer constituting the gate electrode is kept sufficiently low by making a simple modification to the structure of the gate electrode. In order to prevent the deterioration of the heat resistance, the interdiffusion of the dopant through the metal silicide layer forming the gate electrode is suppressed so that the transistor characteristics do not deteriorate.

[0017]

According to the present invention, there is provided a metal thin film and an underlying lower layer between a gate electrode layer acting as a barrier metal layer or a barrier metal layer and a lower gate electrode layer on the side closer to the semiconductor substrate. Basically, a compound thin film generated by the gate electrode layer is interposed.

FIGS. 1A and 1B are cutaway side views of a main part showing a semiconductor device for explaining the principle of the present invention. FIG. 1A is a cutaway side view of a main part along a channel length direction, and FIG. A cutaway side of the main part along the channel width direction substantially at the center of the channel. The same symbols as those used in FIGS. 9 and 10 represent the same parts or have the same meanings.

FIGS. 9 and 1 show the semiconductor device shown in FIG.
The main difference from the semiconductor device shown in FIG. 2 is that the lower gate electrode layer on the side closer to the p-type silicon substrate 1, that is, the polysilicon gate electrode layer 6 in the n-channel MOSFET and the polysilicon in the p-channel MOSFET. silicon·
Ti silicide film 15 was produced by the reaction between the polysilicon gate electrode layer 6 or 7 is Ti thin film and the underlying ultrathin between the TiN gate electrode layer 8 ₁ is a gate electrode layer 7 and the upper gate electrode layer Is inserted.

In the semiconductor device shown in FIG. 1, the upper gate electrode layer forming the gate electrode is made of TiN used as a material for the barrier metal layer, and the upper layer is made of SiN.
It is covered with a cap insulating layer 16 made of, but Wakashi, if you want to reduce the wiring resistance, the gate electrode layer made of pure metal on the TiN gate electrode layer 8 ₁ may be laminated as a matter of course.

The lower gate electrode layer is made of polysilicon, which is made of germanium or
The use of a silicon-containing compound, a germanium-containing compound, or a silicon- and germanium-containing compound is completely the same.

FIG. 2 is a diagram showing the relationship between the contact resistance of TiN / TiSi ₂ and polysilicon and the Ti film thickness. The horizontal axis represents the Ti film thickness [nm], and the vertical axis represents the contact resistance. Each value [Ωμm ² ] is taken.

According to the drawing, when a Ti thin film is interposed between the TiN layer and the polysilicon layer, the TiSi ₂
It can be seen that the contact resistance between the TiN layer and the polysilicon layer is low when a thin film is interposed.

Although not shown, according to experiments, Ti
When the thickness of the thin film was 0, that is, when the Ti thin film was not interposed, the contact resistance became extremely large, and no ohmic contact could be produced.

FIG. 3 is a graph showing the relationship between the phosphorus concentration and the Ti film thickness at the interface between TiN / TiSi ₂ and polysilicon, with the horizontal axis representing the Ti film thickness [nm] and the vertical axis representing the Ti film thickness [nm]. Indicates the phosphorus concentration [cm ^-3 ].

[0026] Figure 3 is the relationship of FIG. 2, i.e., a diagram for better Ti film is thin will be described the reason for that the contact resistance is small, the film thickness of the Ti film is increased when the TiN / TiSi ₂
It can be seen that the phosphorus concentration at the interface between silicon and polysilicon decreases. The phosphorus concentration shown here is SIMS (s
secondary ion mass spectro
(scopy) analysis.

In general, it is known that the contact resistance between silicon and a metal is greatly affected by the dopant concentration at the interface, and the higher the dopant concentration, the lower the contact resistance.

In the case of the present invention, for example, a TiN / Ti / polysilicon structure is formed, and thereafter, a temperature of 1000 [° C.]
RTA (rapid) in N ₂ as time 10 [seconds]
Since thermal annealing is performed, Ti and polysilicon react by this heat, and Ti
Si ₂ and the phosphorus in the polysilicon is TiSi ₂
Although the concentration of phosphorus at the interface is reduced due to the absorption of Ti, the degree of the decrease is small because the TiSi ₂ is thin, so that the contact resistance does not increase.

When a metal such as Al for normal wiring is brought into contact with a source region, a drain region, a gate and the like, a structure of Ti / TiN / Al is used. Is 450 [℃] -5
Since the temperature is as low as 00 [° C.] or less, the dopant does not move, and the contact resistance does not decrease.

According to the data shown in FIGS. 2 and 3, in the semiconductor device according to the present invention, the thickness of the Ti film, which is a refractory metal film interposed in the gate electrode, is 10 [n].
m] It will be understood that the following is preferable. Note that T
When an i film is used, the TiSi ₂ film is about 2.2 times the Ti film.

FIG. 4 is a diagram for explaining the characteristic fluctuation of the n-channel MOSFET due to the opposite conductivity type dopant.
The horizontal axis represents the distance [μm] from the opposite conductivity type diffusion source, and the vertical axis represents the threshold shift [mV].

The data shown is obtained by examining the lateral diffusion of the gate dopant using a sample having the pattern shown in the attached drawings. In the figure, S is a source region, D is a drain region, and G is The gate, P _R is a phosphorus implantation region, B _R is a boron implantation region, L is a distance (parameter) from the opposite conductivity type diffusion source, Lg is a gate length, and Wg is a gate width. In this case, since the purpose is to check the state of diffusion of the gate / dopant, the smaller the gate width Wg is, the easier it is to check the state of diffusion. It is preferable to suppress the fluctuation of the threshold value due to the above.

[0033] As seen in the figure, are adjacent phosphorus implanted region P _R in the region were injected boron is opposite conductivity type dopant B _R, varying the distance therebetween L, temperature of 1000 [℃],
By performing a heat treatment by RTA in N _{2 for a} time of 10 [seconds], it is observed that the dopant in the gate moves and the threshold voltage of the FET changes.

As a result, as in the case of the normal structure in which the gate electrode is made of only polysilicon, the boron implanted region B
_It can be seen that the threshold voltage does not fluctuate even when the distance from _R approaches 0.4 [μm]. Therefore, there is no problem in putting the semiconductor device according to the present invention to practical use.

When the experiment described with reference to FIG. 4 is performed using a gate electrode having a structure in which a tungsten silicide layer is stacked on a polysilicon layer, it has been confirmed that the threshold voltage greatly varies.

FIG. 5 shows data for the p-channel MOSFET, while FIG. 4 shows the data for the n-channel MOSFET.
This is data on T. Similar results were obtained except that the dopant of the reverse conductivity type diffusion source was changed from boron to phosphorus. Even in the case of a p-channel MOSFET, there was a problem with the lateral movement of the dopant. 4 and FIG. 5 show that there is no good CMOS
It can be appreciated that

The effect shown in FIGS. 4 and 5 is obtained because the metal silicide layer, which is considered to be easy for the dopant to move, is an extremely thin film in the present invention as described above. This is because it is difficult for the movement to occur.

As described above, in the semiconductor device according to the present invention, (1) a silicon layer (for example, polysilicon gate electrode layers 6 and 7 and the like) and a semiconductor substrate (for example, p-type silicon substrate 1) side It is necessary to provide a gate electrode in which a compound thin film of a refractory metal and a Group 4 element (for example, a Ti silicide layer 15) and a metal layer that does not react with silicon (for example, a gate electrode layer 8 _{1 made of} TiN) are sequentially stacked. Features, or

(2) A gate electrode comprising a germanium layer, a compound thin film of a refractory metal and a Group 4 element, and a metal layer which does not react with germanium are sequentially stacked from the semiconductor substrate side. Or

(3) A semiconductor device comprising a gate electrode in which a silicon-containing compound layer, a compound thin film of a refractory metal and a Group 4 element, and a metal layer that does not react with the silicon-containing compound layer are sequentially stacked. Features, or

(4) A gate electrode comprising a germanium-containing compound layer, a compound thin film of a refractory metal and a Group 4 element, and a metal layer which does not react with the germanium-containing compound layer are sequentially provided from the semiconductor substrate side. Features, or

(5) From the semiconductor substrate side, a compound layer containing silicon and germanium, a compound thin film of a refractory metal and a Group 4 element, and a metal layer not reacting with the compound layer containing silicon and germanium are sequentially laminated. Characterized by comprising a gate electrode comprising:

[0043] (6) the (1) to (5) In any one of, or a metal layer is characterized by comprising a nitrogen compound of a metal (e.g., a gate electrode layer 8 ₁ consisting of TiN),
Or

(7) In any one of the above (1) to (6), the thickness of the compound thin film of the refractory metal and the Group 4 element is not more than 20 [nm]. Or

(8) The method according to any one of (1) to (7), further comprising a pure metal layer further formed on the metal layer.

By adopting the above means, the contact resistance between the lower gate electrode layer, which is a material which easily reacts with the upper gate electrode material, and the barrier metal layer for suppressing the reaction can be kept sufficiently low. In addition, since the heat resistance does not deteriorate and the transistor characteristics do not deteriorate due to the interdiffusion of the dopant, an integrated circuit device including a transistor which operates at a very high speed can be realized.

[0047]

FIG. 6 to FIG. 8 and FIG. 1 are main part explanatory views showing a semiconductor device in a process step for explaining a process of manufacturing a semiconductor device of the present invention. Is a cut-away side of the main part along the channel length direction, and (B)
Is a cutaway side of the main part along the channel width direction at the substantially center of the channel, and the same symbols as those used in FIGS. 1, 9 and 10 represent the same parts or have the same meanings. .

6 (A) 6- (1) By applying a normal technique, the surface index is (100)
A p-type well 2 and an n-type well 3 are formed on a p-type silicon substrate 1 as shown in FIG. Here, for example, boron was used as the p-type impurity, and phosphorus was used as the n-type impurity.

6- (2) An element isolation insulating region 4 made of SiO ₂ is formed by applying the STI method.

6- (3) By applying the thermal oxidation method, S
A gate insulating film 5 made of iO ₂ is formed.

6- (4) CVD (Chemical Vapor Deposition)
The thickness is 100 [n] by applying the method.
m] of the polysilicon layer.

6- (5) Resist process in lithography technology, and
By applying the ion implantation method, phosphorus is implanted into the n-channel MOSFET portion and boron is implanted into the p-channel MOSFET portion of the polysilicon layer.

6- (6) The thickness is 5 [n] by applying the sputtering method.
m] is formed.

6- (7) The thickness of 65 is obtained by applying the sputtering method.
A [nm] TiN layer is formed.

6- (8) A silicon nitride layer having a thickness of 40 [nm] is formed by applying the CVD method.

7- (1) Resist process in lithography technology and
The etching gas is CHF ₃ + CF ₄ + Ar (SiN
BCl ₃ + Cl ₂ (for TiN and Ti), HB
By applying a dry etching method of r + O ₂ + Cl ₂ (for polysilicon), the polysilicon layer, Ti thin film, Ti thin film formed in steps 6- (4) to 6- (8)
The N layer and the SiN layer are etched into a gate pattern, and n
Formation in the channel MOSFET polysilicon gate electrode layer 6, p in the channel MOSFET polysilicon gate electrode layer 7, a gate pattern of Ti film, the formation of the gate electrode layer 8 ₁ consisting of TiN, from SiN The cap insulating layer 16 is formed.

8- (1) After removing the resist film used in step 7- (1), n
In addition to the resist film covering the channel MOSFET or the resist film covering the p-channel MOSFET, using the gate electrode as a mask, As is implanted into the n-channel MOSFET, and boron is implanted into the p-channel MOSFET. , A low impurity concentration source region 9S having an LDD structure in an n-channel MOSFET, a low impurity concentration drain region 9D having an LDD structure in an n-channel MOSFET, and a low impurity concentration source region 11S, p having an LDD structure in a p-channel MOSFET. Channel MOS
A low impurity concentration drain region 11D having an LDD structure in the FET is formed.

8- (2) A silicon nitride layer having a thickness of 40 [nm] is formed by applying the CVD method.

8- (3) By applying a dry etching method in which the etching gas is CHF ₃ + CF ₄ + Ar, the step 8-
The side wall 12 is formed by performing anisotropic etching of the silicon nitride layer formed in (2).

FIG. 1 1- (1) Resist film covering n-channel MOSFET
In addition to the resist film covering the channel MOSFET, using the gate electrode and the side wall 12 as a mask, As is implanted into the n-channel MOSFET, and boron is implanted into the p-channel MOSFET. High impurity concentration source region 13S having an LDD structure, and L in an n-channel MOSFET.
High impurity concentration drain region 13D having a DD structure, high impurity concentration source region 14S having an LDD structure in a p-channel MOSFET, LDD having a p-channel MOSFET
A high impurity concentration drain region 14D having a structure is formed.

1- (2) By applying the RTA method, the temperature is set to 1000
Heat treatment for activating the dopant is performed at [° C.] for a time of 10 [seconds]. At this time, on the polysilicon gate electrode 6 in the n-channel MOSFET and on the p-channel M
The Ti thin film on the polysilicon gate electrode 7 in the OSFET changes to a Ti silicide thin film 15.

In the present invention, the present invention is not limited to the above-described embodiment, and many other modifications can be realized.

In the above-described embodiment, TiN is used as the upper metal layer material in the gate electrode. However, this may be, for example, a nitrogen compound of tungsten, a nitrogen compound of molybdenum,
It can be replaced with a nitrogen compound of cobalt, a nitrogen compound of tantalum, a nitrogen compound of nickel, or the like. When it is desired to further reduce the resistance value of the wiring, an appropriate pure layer is formed on the metal layer made of the metal nitrogen compound. A metal layer may be stacked.

In the above embodiment, titanium is used as the material of the refractory metal thin film in the compound thin film of the refractory metal and the Group 4 element. For example, titanium having a thickness of 10 nm or less is used. Containing metal, tungsten having a thickness of 10 [nm] or less or metal containing tungsten, having a thickness of 10 [n]
m] or less molybdenum or a metal containing molybdenum, cobalt or a metal containing cobalt having a thickness of 10 nm or less, tantalum or a metal containing tantalum having a thickness of 10 nm or less, nickel having a thickness of 10 nm or less Alternatively, it can be replaced with a metal containing nickel or the like.

In the above embodiment, polysilicon is used as a material of the lower layer in the gate electrode. However, this is replaced with, for example, a polysilicon-containing compound, germanium, a germanium-containing compound, polysilicon and a germanium-containing compound. Energy band, especially when germanium is mixed into the surface of the polysilicon layer.
Since the gap is narrowed, it is effective to reduce the contact resistance.

[0066]

In the semiconductor device according to the present invention, a silicon layer, a silicon-containing compound layer, a germanium layer, a germanium-containing compound layer, a silicon and germanium-containing compound layer, a compound thin film of a refractory metal and a Group 4 element , A gate electrode in which metal layers that do not react with silicon, a silicon-containing compound, germanium, or a germanium-containing compound are sequentially stacked.

By adopting the above configuration, the contact resistance between the lower gate electrode layer, which is a material that easily reacts with the upper gate electrode material, and the barrier metal layer for suppressing the reaction can be kept sufficiently low. In addition, since the heat resistance does not deteriorate and the transistor characteristics do not deteriorate due to the interdiffusion of the dopant, an integrated circuit device including a transistor which operates at a very high speed can be realized.

[Brief description of the drawings]

FIG. 1 is a fragmentary side view showing a semiconductor device for explaining the principle of the present invention.

FIG. 2 is a diagram showing a relationship between a contact resistance between TiN / TiSi ₂ and polysilicon and a Ti film thickness.

FIG. 3 is a diagram showing a relationship between a phosphorus concentration and a Ti film thickness at an interface between TiN / TiSi ₂ and polysilicon.

FIG. 4 shows an n-channel MOSF using an opposite conductivity type dopant.
FIG. 3 is a diagram for explaining a characteristic change of ET.

FIG. 5 is a diagram showing a p-channel MOSF using an opposite conductivity type dopant.
FIG. 3 is a diagram for explaining a characteristic change of ET.

FIG. 6 is an explanatory view of a main part of the semiconductor device in a key step for explaining a step of manufacturing the semiconductor device of the present invention.

FIG. 7 is an explanatory view of a main part of the semiconductor device in a key step for explaining a step of manufacturing the semiconductor device of the present invention.

FIG. 8 is an essential part explanatory view showing the semiconductor device in a process essential point for explaining a process of manufacturing the semiconductor device of the present invention;

FIG. 9 is a fragmentary side view showing a CMOS which is a model for explaining movement of a gate dopant.

10 is an enlarged cross-sectional side view of a main part of FIG. 9 (B).

[Explanation of symbols]

Reference Signs List 1 p-type silicon substrate 2 p-type well 3 n-type well 4 element isolation insulating film 5 gate insulating film 6 polysilicon gate electrode layer in n-channel MOSFET 7 polysilicon gate electrode layer in p-channel MOSFET 8 Tungsten silicide gate electrode layer Low impurity concentration source region of LDD structure in 9S n channel MOSFET Low impurity concentration drain region of LDD structure in 9D n channel MOSFET Low impurity concentration of LDD structure in 11S p channel MOSFET Source region 11D Low impurity concentration drain region in LDD structure in p-channel MOSFET 12 Side wall 13S High impurity concentration source region in LDD structure in n-channel MOSFET 13D LDD structure in n-channel MOSFET High impurity concentration drain region 15 Ti silicide films 16 a cap insulation layer of a high impurity concentration drain region 14S p in the LDD structure in the high impurity concentration source region 14D p-channel MOSFET in the LDD structure on the channel MOSFET

 ──────────────────────────────────────────────────続 き Continued on the front page F-term (reference)

Claims (8)

[Claims] 1. A semiconductor device comprising: a gate electrode formed by sequentially stacking a silicon layer, a compound thin film of a refractory metal and a Group 4 element, and a metal layer that does not react with silicon from the semiconductor substrate side. 2. A semiconductor device comprising: a gate electrode formed by sequentially stacking a germanium layer, a compound thin film of a refractory metal and a Group 4 element, and a metal layer that does not react with germanium from the semiconductor substrate side. 3. A gate electrode comprising a silicon-containing compound layer, a compound thin film of a refractory metal and a Group 4 element, and a metal layer which does not react with the silicon-containing compound layer, which are sequentially stacked from the semiconductor substrate side. Semiconductor device. 4. A gate electrode comprising a germanium-containing compound layer, a compound thin film of a high-melting-point metal and a Group 4 element, and a metal layer that does not react with the germanium-containing compound layer, which are sequentially stacked from the semiconductor substrate side. Semiconductor device. 5. A compound layer containing silicon and germanium, a compound thin film of a refractory metal and a Group 4 element, and a metal layer not reacting with a compound layer containing silicon and germanium are sequentially laminated from the semiconductor substrate side. A semiconductor device comprising a gate electrode. 6. The semiconductor device according to claim 1, wherein the metal layer is made of a metal nitrogen compound. 7. The method according to claim 1, wherein the thickness of the thin film of the compound of the refractory metal and the group 4 element is 20 nm or less.
7. The semiconductor device according to claim 1. 8. The semiconductor device according to claim 1, further comprising a pure metal layer further formed on the metal layer.
13. The semiconductor device according to claim 1.