KR100953335B1 - method of manufacturing a semiconductor device - Google Patents

method of manufacturing a semiconductor device Download PDF

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KR100953335B1
KR100953335B1 KR1020070132137A KR20070132137A KR100953335B1 KR 100953335 B1 KR100953335 B1 KR 100953335B1 KR 1020070132137 A KR1020070132137 A KR 1020070132137A KR 20070132137 A KR20070132137 A KR 20070132137A KR 100953335 B1 KR100953335 B1 KR 100953335B1
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forming
semiconductor substrate
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gate
semiconductor
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KR20090064801A (en
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김양환
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주식회사 동부하이텍
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28114—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor characterised by the sectional shape, e.g. T, inverted-T
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's

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Abstract

본 발명은 반도체 소자 제조 방법에 관한 것이다. 본 발명은 반도체 기판내에 소자분리막을 형성하고 반도체 기판상에 게이트 절연막을 형성하는 단계, 상기 게이트 절연막상에 TEOS(tetraethoxy silane)층을 형성하고, 상기 TEOS층을 패턴닝하여 게이트 형성 영역을 형성하는 단계, 상기 패터닝한 영역에 티(T)자형 게이트를 형성하는 단계, 상기 반도체 기판상에 TEOS층을 제거하는 단계 및 상기 반도체 기판 내에 저농도 제 1 도전형 불순물 이온 영역을 형성하고, 소스 및 드레인 영역을 형성하는 단계를 포함하는 반도체 소자 제조 방법을 포함한다.The present invention relates to a semiconductor device manufacturing method. The present invention provides a method of forming a device isolation film in a semiconductor substrate, forming a gate insulating film on the semiconductor substrate, forming a tetraethoxy silane (TEOS) layer on the gate insulating film, and patterning the TEOS layer to form a gate formation region. Forming a T-shaped gate in the patterned region, removing a TEOS layer on the semiconductor substrate, and forming a low concentration first conductivity type impurity ion region in the semiconductor substrate, and forming a source and drain region. It includes a method of manufacturing a semiconductor device comprising the step of forming a.

반도체, MOS, 스페이서, 공정, T, 게이트 Semiconductor, MOS, Spacer, Process, T, Gate

Description

반도체 소자 제조 방법{method of manufacturing a semiconductor device}Method of manufacturing a semiconductor device

본 발명은 반도체 소자 제조 방법에 관한 것이다. The present invention relates to a semiconductor device manufacturing method.

반도체 소자 중 CMOS(complementary metal oxide semiconductor)는 반도체 성질을 가진 기판상에 산화막을 형성하고 그 위에 도선을 입힌 것으로서, 낮은 전력 소모 등에 이점이 있어 널리 사용된다. Complementary metal oxide semiconductor (CMOS) among semiconductor devices is formed by forming an oxide film on a substrate having semiconductor properties and coating a conductive wire thereon, and is widely used due to its advantages such as low power consumption.

일반적인 CMOS를 제조하는 예는, 폴리 실리콘 증착(deposition) 과정, 폴리 실리콘을 패턴닝(patterning)과정을 거쳐 LDD(lightly doped drain) 영역 형성을 위한 이온 주입 후 스페이서(spacer)를 형성한다. 그 후에 소스/드레인 형성을 위해 각각 소스 영역과 드레인 영역에 이온을 주입하여 CMOS 반도체를 제작한다.In the example of manufacturing a general CMOS, a spacer is formed after ion implantation for forming a lightly doped drain (LDD) region through a polysilicon deposition process and a polysilicon patterning process. Thereafter, ions are implanted into the source region and the drain region, respectively, to form a source / drain, thereby manufacturing a CMOS semiconductor.

위의 순서에 따른 공정 과정 중 스페이서 형성 과정은 반도체의 특성에 큰 영향을 줄 수 있다. 스페이서 공정은 기판상에 일반적으로 SiN4를 증착함으로써 스페이서를 형성하는데, 퍼낸스(furnace)에서 약 700도 내지 800정도의 고온에서 진행할될 수 있다. 그런데 동시에 많은 반도체가 함께 생산될 경우 반도체 소자의 위치에 따라 열을 받는 정도가 달라 스페이서 형성 과정에 의해 생성되는 반도체 소자의 모양이 변형될 수 있다. 따라서, 동시에 다수의 반도체 소자를 형성할 경우 반도체 소자에 틀어짐 현상이 발생할 수 있고 반도체 소자의 특성이 달라질 수 있다. The spacer formation process during the process according to the above sequence can greatly affect the characteristics of the semiconductor. The spacer process generally forms a spacer by depositing SiN 4 on a substrate, which can be carried out at a high temperature of about 700 to 800 degrees in the furnace. At the same time, when a large number of semiconductors are produced together, the degree of heat is different depending on the position of the semiconductor device, and thus the shape of the semiconductor device generated by the spacer forming process may be modified. Therefore, when a plurality of semiconductor devices are formed at the same time, distortion may occur in the semiconductor devices and characteristics of the semiconductor devices may vary.

본 발명이 해결하고자 하는 과제는 반도체 제조 공정을 간소화시킬 수 있고 제조 원가를 줄이면서 반도체 특성을 개선할 수 있는 반도체 제조 방법을 제공하는 것이다.The problem to be solved by the present invention is to provide a semiconductor manufacturing method that can simplify the semiconductor manufacturing process and improve the semiconductor characteristics while reducing the manufacturing cost.

본 발명이 해결하고자 하는 과제는 스페이서 형성 공정이 없이 티(T)자 형 MOS 소자를 제조할 수 있는 반도체 제조 방법을 제공하는 것이다. The problem to be solved by the present invention is to provide a semiconductor manufacturing method capable of manufacturing a tee (T) type MOS device without a spacer forming process.

상기 과제를 해결하고자 하는 본 발명은 반도체 기판내에 소자분리막을 형성하고 반도체 기판상에 게이트 절연막을 형성하는 단계, 상기 게이트 절연막상에 TEOS(tetraethoxy silane)층을 형성하고, 상기 TEOS층을 패턴닝하여 게이트 형성 영역을 형성하는 단계, 상기 패터팅한 영역에 티(T)자형 게이트를 형성하는 단계, 상기 반도체 기판상에 TEOS층을 제거하는 단계 및 상기 반도체 기판 내에 저농도 제 1 도전형 불순물 이온 영역을 형성하고, 소스 및 드레인 영역을 형성하는 단계를 포함하는 반도체 소자 제조 방법을 포함한다.According to an aspect of the present invention, a device isolation film is formed in a semiconductor substrate, a gate insulating film is formed on the semiconductor substrate, a tetraethoxy silane (TEOS) layer is formed on the gate insulating film, and the TEOS layer is patterned. Forming a gate formation region, forming a T-shaped gate in the patterned region, removing a TEOS layer on the semiconductor substrate, and forming a low concentration first conductivity type impurity ion region in the semiconductor substrate. And forming a source and a drain region.

상기 티(T)자형 게이트는 폴리 실리콘(poly silicon)을 증착한 폴리 게이트(poly gate)일 수 있다.The T-shaped gate may be a poly gate on which poly silicon is deposited.

상기 소자분리막은 쉘로우 트랜치 아이솔레이션(shallow trench isolation) 방법에 따라 형성될 수 있다. The device isolation layer may be formed according to a shallow trench isolation method.

상기 티(T)자형 게이트를 형성하는 단계는, 상기 패턴닝한 TEOS층에 폴리 실 리콘을 증착하는 단계, 및 상기 증착한 폴리 실리콘을 포토리소그래피 공정과 에칭 공정으로 티(T)자형으로 게이트를 패턴닝하는 단계를 포함할 수 있다. 상기 TEOS층을 제거하는 단계는 습식 식각(wet etch) 방법으로 상기 TEOS층을 제거할 수 있다. The forming of the tee (T) gate may include depositing polysilicon on the patterned TEOS layer, and depositing the gate of the deposited poly silicon into a tee (T) shape by a photolithography process and an etching process. Patterning may include. Removing the TEOS layer may remove the TEOS layer by a wet etch method.

과제 해결 수단에 따르면 반도체 제조 공정을 간소화시킬 수 있고 제조 원가를 줄이면서 반도체 특성을 개선할 수 있는 반도체 제조 방법을 제공하는 것이다.The problem solving means is to provide a semiconductor manufacturing method that can simplify the semiconductor manufacturing process and improve the semiconductor characteristics while reducing the manufacturing cost.

본 발명이 해결하고자 하는 과제는 스페이서 공정이 없이 티(T)자 형 MOS 소자를 제조할 수 있는 반도체 제조 방법을 제공하는 것이다. The problem to be solved by the present invention is to provide a semiconductor manufacturing method capable of manufacturing a tee (T) type MOS device without a spacer process.

이하 구체적인 실시예를 첨부한 도면을 참조하여 설명한다. 도면을 참조하여 반도체소자 제조 방법의 실시예를 설명하면 다음과 같다.Hereinafter, exemplary embodiments will be described with reference to the accompanying drawings. An embodiment of a semiconductor device manufacturing method will be described below with reference to the accompanying drawings.

도 1 내지 도 7은 반도체 제조 방법의 실시예를 순차적으로 나타낸 도면이다. 도 1 내지 도 7을 참조하여 본 발명에 따른 반도체 제조 방법의 실시예를 기술하면 다음과 같다. 1 to 7 are views sequentially showing an embodiment of a semiconductor manufacturing method. An embodiment of a semiconductor manufacturing method according to the present invention will be described with reference to FIGS. 1 to 7.

도 1에서 나타낸 공정은 반도체 기판(110)에 액티브 영역의 전기적인 절연을 위해 소자 분리막(120)을 형성한다. 소자 분리막은 예를 들어 쉘로우 트랜치 아이솔레이션(shallow trench isolation) 공정으로 형성될 수 있다. 즉, 쉘로우 트랜치 아이솔레이션(shallow trench isolation) 공정이 사용될 경우 반도체 기판(110)에 트랜치(120) 영역을 형성하고, 트랜치에 유전체를 채울 수 있다. The process shown in FIG. 1 forms the device isolation layer 120 for electrically insulating the active region on the semiconductor substrate 110. The device isolation layer may be formed by, for example, a shallow trench isolation process. That is, when a shallow trench isolation process is used, a trench 120 region may be formed in the semiconductor substrate 110, and a dielectric may be filled in the trench.

반도체 기판(110)상에 게이트 절연막(130)을 반도체 기판(110)상에 성장시킨 다. 게이트 절연막(130)은 열산화 공정이나 저압 화학기상증착 공정을 이용하여 생성시킬 수 있느데, 예를 들어 게이트 절연막(130)으로서, 산화막(oxide)을 반도체 기판(110) 표면에 형성시킬 수 있다. 게이트 절연막(130) 액티브 영역과 게이트가 고립되도록 하는 역할을 한다. The gate insulating layer 130 is grown on the semiconductor substrate 110 on the semiconductor substrate 110. The gate insulating layer 130 may be formed using a thermal oxidation process or a low pressure chemical vapor deposition process. For example, as the gate insulating layer 130, an oxide layer may be formed on the surface of the semiconductor substrate 110. The gate insulating layer 130 serves to isolate the active region from the gate.

도 2에 예시한 공정에서, TEOS(tetraethoxy silane)층(140)을 게이트 절연막(130) 상에 증착하고, 게이트를 형성하기 위해 TEOS층(140)을 패턴닝한다. TEOS층(140)을 포토리소그래피 공정 및 에치 공정을 통해 패턴닝할 수 있다. 패턴닝하면 게이트 절연막(130)의 일부를 노출시킬 수 있다.In the process illustrated in FIG. 2, a tetraethoxy silane (TEOS) layer 140 is deposited on the gate insulating film 130, and the TEOS layer 140 is patterned to form a gate. The TEOS layer 140 may be patterned through a photolithography process and an etch process. Patterning may expose a portion of the gate insulating layer 130.

도 3에 예시한 공정에서 TEOS층(140)을 패턴닝하여 노출된 게이트 절연막(130)상에 티(T)자형의 게이트(150) 패턴을 형성한다. 예를 들어 게이트(150) 패턴은 패턴닝한 TEOS층에 폴리 실리콘을 증착한 후 증착한 폴리 실리콘에 포토리소그래피 공정과 에칭 공정을 수행하여 티(T)자형으로 게이트로 패턴닝하여 폴리 게이트(poly-gate)를 형성할 수 있다.In the process illustrated in FIG. 3, the TEOS layer 140 is patterned to form a T-shaped gate 150 pattern on the exposed gate insulating layer 130. For example, the gate 150 pattern is formed by depositing polysilicon on the patterned TEOS layer and then performing photolithography and etching processes on the deposited polysilicon to pattern the gate in a tee shape to form a poly gate (poly). -gate).

도 4의 공정에서 반도체 기판(110)상에 적층된 TEOS층(140)을 식각 공정을 이용하여 제거한다. 예를 들어 용액성 화학 물질을 이용하여 TEOS층(140)을 습식 식각하고, 게이트 절연막(130) 상에 티(T)자형 게이트(150)가 형성되도록 한다.In the process of FIG. 4, the TEOS layer 140 stacked on the semiconductor substrate 110 is removed using an etching process. For example, the TEOS layer 140 is wet-etched using a solution chemical, and a T-shaped gate 150 is formed on the gate insulating layer 130.

도 5 및 도 6의 공정에서 예시한 바와 같이 게이트 영역을 중심으로 게이트 영역의 하위의 양쪽에 저농도의 제 1 도전형 불순물 이온을 반도체 기판(110)에 각각 주입한다. 따라서, 저농도의 제 1 도전형 불순물 이온을 반도체 기판(110)에 각각 주입하면 반도체 기판(110)내에 LDD(lightly doped drain) 영역(160)이 형성된다. 도 5 및 도 6은 LDD 영역(160)은 도핑(doping)이 낮은 물질을 반도체 기판(110)에 도 5 및 도 6에서 예시한 바와 같이 경사진 방향으로 주입(implantation)하는 예를 개시한다. LDD 영역(160)은 반도체 기판(110)내에 주입된 이온 농도의 프로파일을 형성하여 반도체 소자 구동시 반도체 소자 동작시 반도체 소자의 동작 전압을 낮출 수 있는 역할을 할 수 있다.As illustrated in the processes of FIGS. 5 and 6, the first conductivity type impurity ions having low concentration are implanted into the semiconductor substrate 110 at both sides of the gate region, respectively, around the gate region. Therefore, when the low concentration of the first conductivity type impurity ions are implanted into the semiconductor substrate 110, lightly doped drain (LDD) regions 160 are formed in the semiconductor substrate 110. 5 and 6 illustrate an example in which the LDD region 160 is implanted with a low doping material into the semiconductor substrate 110 in an inclined direction as illustrated in FIGS. 5 and 6. The LDD region 160 may form a profile of ion concentration implanted in the semiconductor substrate 110 to lower the operating voltage of the semiconductor device when the semiconductor device is driven when the semiconductor device is driven.

도 7에서 예시한 바와 같이 드레인(drain)(170) 영역과 소스(source)(180)영역을 생성한다. 반도체 기판(110)내에 게이트(160)를 중심으로 각각 고농도의 제 2 도전성 이온 물질을 드레인(drain)(170) 영역과 소스(source)(180)영역에 주입한다. 드레인 영역(170)과 소스 영역(180)은 게이트(160) 영역과 LDD 영역을 사이에 두고 위치하도록 각각 도핑 물질을 주입한다. As illustrated in FIG. 7, a drain 170 region and a source 180 region are generated. In the semiconductor substrate 110, a second concentration of the second conductive ionic material is injected into the drain 170 and the source 180 regions, respectively, around the gate 160. The doping material is injected into the drain region 170 and the source region 180 so as to be positioned with the gate 160 region and the LDD region interposed therebetween.

위의 실시예에 따르면 스페이서의 구조를 별도로 생성하는 공정을 수행하지 않고 티(T) 자형 반도체 소자를 형성할 수 있다. 위와 같이 티(T) 자 형태의 게이트를 형성하여 인위적으로 LDD 영역을 블럭킹하는 스페이서를 형성하지 않아도 LDD 영역과 소스/드레인 영역을 별도로 형성시킬 수 있다. 따라서 스페이서를 형성하는 공정을 없애 공정을 간단하게 할 수 있고, 스페이서를 형성하는 공정시 열 예 산(thermal budget)을 줄일 수 있다. 그리고, 많은 반도체 소자에 스페이서를 동시에 형성하는 공정을 수행할 경우 각 반도체 소자가 위치에 따른 온도의 차이 발생하는 반도체 소자의 틀어짐 현상을 방지할 수 있다. 따라서, 동일한 특성을 가지는 반도체 소자를 동시에 생산할 수 있다. According to the above embodiment, the T-shaped semiconductor device may be formed without performing a process of separately generating the structure of the spacer. As described above, the LDD region and the source / drain region may be formed separately without forming a spacer having a T-shaped gate to artificially block the LDD region. Therefore, the process of forming the spacer can be eliminated, thereby simplifying the process, and the thermal budget in the process of forming the spacer can be reduced. In addition, when a process of forming spacers on a plurality of semiconductor devices is performed at the same time, it is possible to prevent the semiconductor device from being distorted due to a difference in temperature depending on the location of each semiconductor device. Therefore, semiconductor devices having the same characteristics can be produced at the same time.

도 1은 반도체 기판상에 소자분리막과 게이트막을 생성하는 공정을 예시한 도면1 illustrates a process of forming an isolation layer and a gate film on a semiconductor substrate.

도 2는 TEOS층을 형성하는 공정을 예시한 도면2 illustrates a process of forming a TEOS layer;

도 3은 폴리 게이트를 형성하는 공정을 예시한 도면3 illustrates a process of forming a poly gate.

도 4는 TEOS층을 제거하는 공정을 예시한 도면4 illustrates a process of removing a TEOS layer.

도 5 및 도 6은 LDD(lightly doped drain) 영역을 형성하는 공정을 예시하는 도면5 and 6 illustrate a process of forming a lightly doped drain (LDD) region.

도 7은 소스와 드레인 영역을 형성하는 공정을 예시한 도면7 illustrates a process of forming source and drain regions;

Claims (5)

반도체 기판내에 소자분리막을 형성하고 반도체 기판상에 게이트 절연막을 형성하는 단계; Forming an isolation layer in the semiconductor substrate and forming a gate insulating film on the semiconductor substrate; 상기 게이트 절연막 상에 TEOS(tetraethoxy silane)층을 형성하고, 상기 게이트 절연막의 일부를 노출하도록 TEOS층을 패턴닝하여 게이트 형성 영역을 형성하는 단계;Forming a tetraethoxy silane (TEOS) layer on the gate insulating film, and patterning the TEOS layer to expose a portion of the gate insulating film to form a gate formation region; 패턴닝한 TEOS층에 폴리 실리콘을 증착한 후 포토리소그래피 공정과 에칭 공정을 수행하여 증착한 폴리 실리콘을 티(T)자형 게이트로 패터닝하는 단계;Depositing polysilicon on the patterned TEOS layer and then performing photolithography and etching to pattern the deposited polysilicon into a T-shaped gate; 상기 반도체 기판 상에 형성된 TEOS층을 제거하는 단계;Removing the TEOS layer formed on the semiconductor substrate; TEOS층이 제거된 반도체 기판 내에 제1 도전형 불순물 이온을 주입하여 LDD(lightly doped drain) 영역을 형성하는 단계; 및Implanting first conductivity type impurity ions into the semiconductor substrate from which the TEOS layer has been removed to form a lightly doped drain (LDD) region; And 상기 LDD 영역이 형성된 반도체 기판 내에 소스 및 드레인 영역을 형성하는 단계를 포함하는 반도체 소자 제조 방법.Forming a source and a drain region in the semiconductor substrate on which the LDD region is formed. 제 1항에 있어서, 상기 LDD 영역을 형성하는 단계는,The method of claim 1, wherein the forming of the LDD region comprises: 상기 제1 도전형 불순물 이온을 경사 주입하여 상기 LDD 영역을 형성하는 것을 특징으로 하는 반도체 소자 제조 방법.And injecting the first conductivity type impurity ions to form the LDD region. 제 1항에 있어서,The method of claim 1, 상기 소스 및 드레인 영역은 상기 게이트 형성 영역과 상기 LDD 영역을 사이에 두고 위치하도록 형성하는 것을 특징으로 하는 반도체 소자 제조 방법.The source and drain regions may be formed to be positioned with the gate formation region and the LDD region therebetween. 삭제delete 제 1항에 있어서,The method of claim 1, 상기 TEOS층을 제거하는 단계는 습식 식각 방법을 이용하여 제거하는 반도체 소자 제조 방법.The step of removing the TEOS layer is a semiconductor device manufacturing method using a wet etching method.
KR1020070132137A 2007-12-17 2007-12-17 method of manufacturing a semiconductor device KR100953335B1 (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR0141951B1 (en) * 1994-12-20 1998-06-01 문정환 Manufacturing method of semiconductor device
KR20000031962A (en) * 1998-11-11 2000-06-05 정선종 Electric power device having trench gate structure and production method thereof
KR20040060489A (en) * 2002-12-30 2004-07-06 동부전자 주식회사 Method for forming transistor
KR20050069522A (en) * 2003-12-31 2005-07-05 동부아남반도체 주식회사 Method for making gate structure in the semiconductor device manufacture processing

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR0141951B1 (en) * 1994-12-20 1998-06-01 문정환 Manufacturing method of semiconductor device
KR20000031962A (en) * 1998-11-11 2000-06-05 정선종 Electric power device having trench gate structure and production method thereof
KR20040060489A (en) * 2002-12-30 2004-07-06 동부전자 주식회사 Method for forming transistor
KR20050069522A (en) * 2003-12-31 2005-07-05 동부아남반도체 주식회사 Method for making gate structure in the semiconductor device manufacture processing

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