CN103426826B - Flash cell and forming method thereof - Google Patents
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Abstract
A kind of flash cell and forming method thereof, the forming method of described flash cell includes: providing Semiconductor substrate, semiconductor substrate surface is formed with the floating gate material layer on first medium layer and surface thereof；Formed and cover first medium layer and the second dielectric layer on floating gate material layer surface and the control gate material layer on surface thereof；The hard mask layer with opening is formed in control gate material surface；The first side wall is formed in opening；With the first side wall and hard mask layer as mask, etching controls gate material layer, forms the first groove；In the first groove, formed and be positioned at the second side wall controlled on gate material layer sidewall；Along the first recess etch second dielectric layer, floating gate material layer and first medium layer, form the second groove and floating boom；Tunnel oxide is formed on the second groove inner wall surface；Formed on tunnel oxide surface and fill full first groove, the wordline of the second groove.Said method can improve and control in flash memory to delete the coupling efficiency to floating boom, thus improves the wiping/writing performance of flash memory.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly to a kind of flash cell and forming method thereof.
Background technology
In current semiconductor industry, IC products can be divided mainly into three major types type: logic, storage
Device and analog circuit, wherein memory device account for sizable ratio in IC products, such as RAM
(random access memory), DRAM(dynamic RAM), ROM (read only memory), EPROM (can
Erasable programmable read-only memory (EPROM)), FLASH (flash memory) and FRAM(ferroelectric memory) etc..
In memorizer, the development of flash memory is the rapidest.It is mainly characterized by the case of not powered can grow
Phase keeps the information of storage, has integrated level height, faster access speed and is prone to the multiple advantages such as erasing,
Thus be widely used in the multinomial field such as microcomputer, Automated condtrol.Flash memory structure generally comprises
Floating boom and be positioned at the control gate above described floating boom.
Refer to Fig. 1, for the structural representation of the flash cell that prior art is formed.
Described flash cell specifically includes that Semiconductor substrate 10, is positioned at the coupling oxygen on Semiconductor substrate 10 surface
Change layer 21, be positioned at the floating boom 22 on described coupling oxide layer surface, be positioned at the isolating oxide layer on floating boom 22 surface
31, be positioned at the control gate 32 on isolating oxide layer surface, and be positioned at control gate 32, isolating oxide layer 31,
Floating boom 22, the wordline 40 of coupling oxide layer 21 side, it is positioned at described wordline 40 and floating boom 22, coupling oxidation
Tunnel oxide 33 between layer 21, Semiconductor substrate 10.
The control gate of existing flash memory is relatively low to the coupling efficiency of floating boom, and flash memory wiping/writing efficiency is on the low side, need into
The raising of one step.
Summary of the invention
The problem that the present invention solves is to provide a kind of flash cell and forming method thereof, improves in flash memory and controls
Delete the coupling efficiency to floating boom, improve the wiping/writing performance of flash memory.
For solving the problems referred to above, the present invention provides the forming method of a kind of flash cell, including: provide half
Conductor substrate, described semiconductor substrate surface is formed with the first medium of covering part semiconductor substrate surface
Layer and the floating gate material layer being positioned at first medium layer surface；Formed cover described semiconductor substrate surface, the
One dielectric layer and floating gate material layer sidewall and the second dielectric layer of floating gate material layer top surface, Yi Jiwei
Control gate material layer in described second dielectric layer surface；Formed in described control gate material surface and have
The hard mask layer of opening, described opening is positioned at directly over floating gate material layer, and the width of described opening is more than
The width of floating gate material layer；The first side wall covering hard mask layer sidewall is formed in described opening；With institute
State the first side wall and hard mask layer is mask, with described second dielectric layer as stop-layer, etch described control
Gate material layer, forms the first groove；In described first groove, formed and be positioned at described control gate material layer
The second side wall on sidewall；With described Semiconductor substrate as stop-layer, along described first recess etch second
Dielectric layer, floating gate material layer and first medium layer, form the second groove and be positioned at the floating of the second groove both sides
Grid；Tunnel oxide is formed on described second groove inner wall surface；Formed on described tunnel oxide surface
Fill full described first groove, the wordline of the second groove；Remove described hard mask layer and being positioned at described firmly to cover
Part under film layer controls gate material layer and part second dielectric layer, forms control gate, and described control gate covers
Lid is positioned at the top surface of floating boom and the second dielectric layer of the side sidewall surfaces away from wordline.
Optionally, also include: before forming described second side wall, at described control gate material layer sidewall table
Face forms silicon oxide layer.
Optionally, the width of described first medium layer and floating gate material layer is 0.2 micron～0.4 micron, described
The thickness of floating gate material layer is 200 angstroms～600 angstroms.
Optionally, the width of described opening is 0.3 micron～0.5 micron.
Optionally, also include: carry out ion is lightly doped in the Semiconductor substrate of described first side wall both sides
Inject, formed and district is lightly doped；Described semiconductor substrate surface formed cover described control gate dielectric layer,
Control gate and the 3rd side wall of the first side wall sidewall；Enter in the Semiconductor substrate of described 3rd side wall both sides
Row ion implanting, forms source line and bit line, part source line and part bit line are positioned at semiconductor substrate surface
Below control gate.
Optionally, the dopant ion that ion implanting and ion implanting employing are lightly doped described in is N-type ion.
For solving the problems referred to above, technical scheme additionally provides and a kind of uses said method to be formed
Flash cell, including: Semiconductor substrate；It is positioned at the floating gate dielectric layer of semiconductor substrate surface and is positioned at institute
State the floating boom on floating gate dielectric layer surface；It is positioned at described floating boom surface and covers described floating boom end face and sidewall
Control gate dielectric layer and be positioned at the control gate of described control gate dielectric layer surface；Run through described control gate,
The groove of control gate dielectric layer, floating boom and floating gate dielectric layer；It is positioned on the control gate sidewall of described groove
The second side wall；It is positioned at the first side wall of described control gate top surface；Be positioned at described first side wall surface,
Second side wall surface and the tunnel oxide on groove inner wall surface；It is positioned at described tunnel oxide surface, fills out
It is full of described groove, and the wordline that surface flushes with the first side wall surface；Be positioned at described first side wall,
Control gate, the 3rd side wall of control gate dielectric layer sidewall surfaces；It is positioned at partly leading of described 3rd side wall both sides
Source line in body substrate and bit line.
Optionally, between the control gate sidewall in described groove and the second side wall, there is silicon oxide layer.
Optionally, the dopant ion in described source line and wordline is N-type ion.
Optionally, part source line and part bit line are positioned at below the control gate of semiconductor substrate surface.
Compared with prior art, technical scheme has the advantage that
Technical scheme, described semiconductor substrate surface forms covering part semiconductor substrate surface
First medium layer and be positioned at the floating gate material layer on first medium layer surface, then at described floating gate material layer
Surface is formed and covers the second dielectric layer on described floating gate material layer surface and sidewall and be positioned at described second medium
The control gate material layer on layer surface.Floating gate material layer described in subsequent etching forms floating boom, etches described second
Dielectric layer and control the control gate dielectric layer that formed respectively of gate material layer and control gate, described control gate medium
Layer covers top surface and the side sidewall of floating boom, and control gate is positioned at described control gate dielectric layer surface,
So described control gate, the end face face that overlapping area is described floating boom between control gate dielectric layer and floating boom
Amass and side sidewall area sum, compared with prior art, improve described control gate, control gate medium
Overlapping area between layer and floating boom, makes the electric capacity between described control gate and floating boom improve, and then improves
The control gate the formed coupling efficiency to floating boom, improves the wiping/writing performance of flash cell.
Further, before forming source line and bit line, first described Semiconductor substrate is lightly doped ion
Inject so that the source line ultimately formed and bit line portion are positioned at below the control gate of semiconductor substrate surface,
It is positioned at the parasitic channel below described control gate such that it is able to eliminate.
Accompanying drawing explanation
Fig. 1 is the structural representation of the flash cell of the prior art of the present invention；
Fig. 2 to Figure 17 is the schematic diagram of the flash cell forming process of the embodiment of the present invention.
Detailed description of the invention
As described in the background art, in the flash memory that prior art is formed, control gate is to the coupling efficiency of floating boom not
High.Research finds, this low coupling efficiency can make floating boom couple the low voltage obtained from control gate,
When causing that flash memory is programmed or wipes operation, needs bring up to the highest voltage, the erasable effect of flash memory
Rate reduces, and power consumption becomes big, and the requirement of reliability of material also can be improved by higher voltage.
The control gate of flash memory is that the electric capacity between control gate and floating boom accounts for around floating boom to floating boom coupling efficiency
The ratio of total capacitance, the control gate of the flash memory of prior art is positioned at above floating boom top surface, described control
Electric capacity between grid with floating boom depends on the size of the control gate topside area overlapping with floating boom.
Technical scheme provides a kind of flash cell and forming method thereof, improves the control gate of flash memory
And the overlapping area between floating boom, increases the electric capacity between control gate and floating boom, thus improves the coupling of flash memory
Close efficiency, thus improve the wiping/writing performance of flash memory.
Understandable, below in conjunction with the accompanying drawings for enabling the above-mentioned purpose of the present invention, feature and advantage to become apparent from
The specific embodiment of the present invention is described in detail.
Refer to Fig. 2, it is provided that Semiconductor substrate 100, form first on described Semiconductor substrate 100 surface
Layer of dielectric material 201 and floating gate material layer 202.
The material of described Semiconductor substrate 100 includes the semi-conducting materials such as silicon, germanium, SiGe, GaAs,
Described Semiconductor substrate 100 can be body material can also be composite construction such as silicon-on-insulator.This area
Technical staff can according in Semiconductor substrate 100 formed semiconductor device select described quasiconductor lining
The type at the end 100, the type of the most described Semiconductor substrate should not limit the scope of the invention.This
In embodiment, described Semiconductor substrate 100 is silicon chip.
The material of described first medium layer 201 is silicon oxide, and described first medium layer 201 is subsequently used for shape
Become floating gate dielectric layer, as the tunnel oxide between floating boom and substrate.Described first medium layer 201
Forming method is thermal oxide or chemical gaseous phase deposition.The thickness range of described first medium layer 201 is 80 angstroms
～100 angstroms.
The material of floating gate material layer 202 can be polysilicon, and described floating gate material layer 202 is subsequently used for shape
Becoming floating boom, described floating gate material layer 202 forming method is chemical gaseous phase deposition.Described floating gate material layer 202
Thickness range be 200 angstroms～600 angstroms.
Refer to Fig. 3, etch described floating gate material layer 202 and first medium layer 201(refer to Fig. 2),
Form floating gate material layer 204 and the first medium layer 203 on covering part Semiconductor substrate 100 surface.
The method forming described floating gate material layer 204 and first medium layer 203 includes: at described floating boom material
Bed of material 202(refer to Fig. 2) surface forms patterned photoresist layer, and described graphical photoresist layer limits
Determine floating gate material layer 204 and first medium layer 203 positions and dimensions being subsequently formed, state figure with described
Shape photoresist layer is mask, etches described floating gate material layer 202 and first medium layer 201(refer to figure
2) surface of part semiconductor substrate, is exposed.
Concrete, in the present embodiment, after using dry etch process to etch described floating gate material layer 202,
Wet-etching technology is used to etch described first medium layer 201, it is possible to reduce etching process is to Semiconductor substrate
The damage on 100 surfaces.
In other embodiments of the invention, it would however also be possible to employ dry etch process etches described floating gate material
Layer and first medium layer.
Described floating gate material layer 204 and the surface of first medium layer 203 covering part Semiconductor substrate 100.
The width range of described floating gate material layer 204 and first medium layer 203 is 0.2 micron～0.4 micron.
Refer to Fig. 4, formed and cover described Semiconductor substrate 100 surface, floating gate material layer 204 and first
The second dielectric layer 301 on dielectric layer 203 surface, and it is positioned at the control on described second dielectric layer 301 surface
Gate material layer 302.
The material of described second dielectric layer 301 is ONO(oxide-nitride-oxide) structure, institute
State second dielectric layer 301 to be subsequently used for forming control gate dielectric layer, as controlling to delete the coupling between floating boom
Close oxide layer.The forming method of described second dielectric layer 301 is thermal oxide or chemical gaseous phase deposition.Described
The thickness range of second dielectric layer 301 is 100 angstroms～200 angstroms.In other embodiments of the present invention, second
The material of dielectric layer can also is that mono-layer oxidized silicon.
Described second dielectric layer 301 cover floating gate material layer 204 and the sidewall of first medium layer 203 and
The top surface of lid floating gate material layer 204.
Described control gate material layer 302 material can be polysilicon, and described control gate material layer 302 is follow-up
For forming control gate, described control gate material layer 302 forming method is chemical gaseous phase deposition.Described control
The thickness range of gate material layer 302 processed is 500 angstroms～1000 angstroms.Described control gate material layer 302 and floating boom
Isolated by second dielectric layer 301 between surface and the sidewall of material layer 204.
Refer to Fig. 5, form hard mask layer 400 on described control gate material layer 302 surface.
Described hard mask layer 400 material is silicon nitride, and chemical vapor deposition method can be used to be formed.
Refer to Fig. 6, etch described hard mask layer 400(and refer to Fig. 5), form graphical hard mask layer
401。
The method forming described graphical hard mask layer 401 includes: refer at described hard mask layer 400(
Fig. 5) surface forms patterned photoresist layer, and described graphical photoresist layer defines the figure being subsequently formed
The positions and dimensions of shape hard mask layer 401, states graphical photoresist layer as mask with described, etches institute
Stating hard mask layer 400, form opening 402, described opening 402 exposes part and controls gate material layer 302
Surface.
Described opening 402 is positioned at the surface controlling gate material layer 302, and the width of described opening 402 is big
Width in floating gate material layer 204.The width range of described opening 402 is 0.3 micron～0.5 micron.
Refer to Fig. 7, in described opening 402, form the first side wall 403 covering described opening sidewalls.
The material of described first side wall 403 differs with the material of described graphical hard mask layer 401, this
In embodiment, the material of described first side wall 403 is silicon oxide.
Formed described first side wall 403 method include: formed and cover described opening 402 inwall and institute
State the first spacer material layer on graphical hard mask layer 401 surface, use without mask etching technique, etching
Described first spacer material layer, removes and is positioned at table bottom graphical hard mask layer 401 surface and opening 402
First spacer material in face, forms the first side wall 403 covering opening 402 sidewall.Described sidewall section position
Above floating gate material layer 204.
Described first side wall 403 controls the mask of gate material layer as subsequent etching.
Refer to Fig. 8, with described first side wall 403 and graphical hard mask layer 401 as mask, along described
Opening 402 etches described control gate material layer 302, exposes the surface of part second dielectric layer 301.
Concrete, with described second dielectric layer 301 as etching stop layer, dry etch process can be used
Etch described control gate material layer 302, form the first groove 303.
Refer to Fig. 9, at described graphical hard mask layer the 401, first side wall 403 and the first groove 303
The silicon oxide layer 404 of inner wall surface.
Described silicon oxide layer 404 thickness be 50 angstroms～100 angstroms, use chemical vapor deposition method formed
Described silicon oxide layer 404.Described silicon oxide layer can be avoided follow-up directly at the first groove 303 sidewall table
During face forms the second side wall, between described second side wall and control gate material layer 302, there is lattice
Mismatch and produce defect.
In other embodiments of the invention, it is also possible to use thermal oxidation technology, directly described first recessed
Control gate material layer 302 sidewall surfaces of groove 303 sidewall forms silicon oxide layer.
In other embodiments of the invention, it is also possible to be formed without described silicon oxide layer 404.
Refer to Figure 10, form the second side on silicon oxide layer 404 surface of described first groove 303 sidewall
Wall 405.
The material of described second side wall 405 is silicon nitride.Due to the thinner thickness of described silicon oxide layer 405,
Be insufficient as the follow-up wordline formed in the first groove 303 and control between gate material layer 302 every
From structure, so forming the second side wall 405, as the isolation junction between wordline and control gate material layer 302
Structure.Form described second side wall 405 on described silicon oxide layer 405 surface and can improve described second side wall
The quality of 405, improves isolation effect.
Concrete, the method forming described second side wall 405 includes: in described silicon oxide 404 surface shape
Become the second spacer material layer, use without mask etching technique, etch described second spacer material layer, remove
Table bottom graphical hard mask layer 401 surface, part the first side wall 403 surface and the first groove 303
Part the second spacer material layer in face, forms the second side wall 405 covering the first groove 303 sidewall surfaces.
Refer to Figure 11, along described first groove 303 etching oxidation silicon layer 404, second dielectric layer 301,
Floating gate material layer 204 and first medium layer 203(refer to Figure 10), with described Semiconductor substrate 100 be
Etching stop layer, forms the second groove 304, and is positioned at the floating boom 206 of described first groove both sides, floating
Gate dielectric layer 205.
Concrete, with described graphical hard mask layer the 401, first side wall the 403, second side wall 405 for covering
Film layer, etches described silicon oxide layer 404, second dielectric layer 301, floating gate material layer along the first groove 303
204 and first medium layer 203 to Semiconductor substrate 100, form the second groove 304.
Use dry etch process, eliminate the partial oxidation silicon layer 404 of exposure simultaneously.Described floating gate material
Layer 204 and first medium layer 205(refer to Figure 10) be etched after, respectively as the floating boom 206 of flash memory
With floating gate dielectric layer 205.
Refer to Figure 12, formed and cover described second groove the 304, first groove 303 inwall, the first side
Wall 403 surface and the tunnel oxide 501 on graphical hard mask layer 401 surface.
The material of described tunnel oxide 501 is silicon oxide, and the thickness of described tunnel oxide 501 is 100
Angstrom～150 angstroms, can use chemical gaseous phase deposition or atom layer deposition process form described tunnel oxide
501。
Refer to Figure 13, formed on described tunnel oxide 501 surface fill full described opening 402, the
One groove 303 and the second groove 304(refer to Figure 12) wordline 502.
The material of described wordline 502 is polysilicon, uses chemical vapor deposition method to form described wordline 502.
Concrete, the method forming described wordline 502 includes: in described tunnel oxide 501 surface shape
Become to fill full described opening the 402, first groove 303 and the second groove 304(and refer to Figure 12), and
Cover the described wordline material layer higher than described graphical hard mask layer 401 surface；With described first figure
Changing hard mask layer 401 is stop-layer, and described wordline material layer is carried out chemical machinery mask process, removes
It is positioned at part tunnel oxide 501 and the wordline material layer on the described first graphical hard mask layer 401 surface,
Forming wordline 502, the surface of described wordline 502 flushes with the surface of graphical hard mask layer 401.
Refer to Figure 14, after described wordline 502 surface forms cap 503, remove described first figure
Shape hard mask layer 401 controls gate material layer 302 with the part being positioned at below described graphical hard mask layer
Figure 13 is refer to part second dielectric layer 301(), form control gate 306 and control gate dielectric layer 305.
The material of described cap 503 is silicon oxide, and thermal oxidation technology can be used in described wordline 502
Surface forms described cap 503.Described cap 503 is for protecting described word in subsequent etching processes
Line 502 is injury-free.Depositing operation can also be used in other embodiments of the invention to form described lid
Cap layers 503.
In the present embodiment, use wet-etching technology to remove described Patterned masking layer 401(and refer to figure
13), described wet etching solution can be phosphoric acid；Then dry etch process is used, with described first side
Wall 305 and cap 503 are mask, remove the part control gate below described Patterned masking layer 401
Material layer 302 and part second dielectric layer 301(refer to Figure 13), form control gate 306 and below
Control gate dielectric layer 305.
Opening 402(in described Patterned masking layer 401 refer to Figure 12) width more than floating boom material
The width of the bed of material, so the control gate dielectric layer 305 formed after removing described Patterned masking layer covers floating
The top surface of grid 206 and described floating boom 206 are away from the sidewall surfaces of wordline 502 side, described control
Electric capacity, described control gate 306 and floating boom is formed between grid 306, control gate dielectric layer 305 and floating boom 206
Overlapping area between 206 includes not only including the weight that control gate 306 is positioned at floating boom 206 top surface portion
Folded area, also includes the area of the side sidewall of described floating boom 206, compared with prior art, improves
Overlapping area between described control gate 306 and floating boom 206, improves described control gate 306 and floating boom
Electric capacity between 206.
Total capacitance around described floating boom 206 is the electric capacity between control gate 306 and floating boom 206, floating boom
The electric capacity sum between electric capacity and floating boom 206 and wordline 502 between 206 and substrate 100.Due to
Compared with prior art, between floating boom 206 and Semiconductor substrate 100 and floating boom 206 and wordline 502
Structure do not change, the therefore electric capacity between floating boom 206 and substrate 100 and floating boom 206
And the electric capacity between wordline 502 is constant.
Owing to flash memory control grid is that the electric capacity between control gate and floating boom accounts for floating boom week to the coupling efficiency of floating boom
The ratio of the total capacitance enclosed, electric capacity between floating boom 206 and substrate 100 and floating boom 206 and word
In the case of electric capacity between line 502 is constant, the electric capacity between described control gate 306 and floating boom 206 carries
High so that the ratio in total capacitance of the electric capacity between control gate 306 and floating boom 206 improves, thus dodges
The coupling efficiency deposited improves, and can improve the magnitude of voltage that flash memory is coupled on floating boom 206 in the course of the work,
Thus improve the work efficiency of flash reading and writing or erasing, improve the performance of flash memory.
Refer to Figure 15, be lightly doped in the Semiconductor substrate 100 of described first side wall 403 both sides
Ion implanting, is formed and district 101 is lightly doped.
The described ion that ion implanting is lightly doped is N-type ion, including the one in phosphorus, gallium or arsenic or several
Kind of ion, described in the ion dose of ion implanting is lightly doped is 1 × 1013atom/cm3～5 × 1013atom/cm3,
Energy is 20keV～30keV.
The described ion being lightly doped in district 101 spreads during subsequent anneal, and part is lightly doped district and is positioned at
Below control gate 306, the parasitic channel being positioned at below control gate 306 can be eliminated.
Refer to Figure 16, formed on described Semiconductor substrate 100 surface and cover described control gate dielectric layer
305, control gate 306 and the 3rd side wall 102 of the first side wall 403 sidewall.
The material of described 3rd side wall 102 is silicon nitride.Described 3rd side wall 102 is due at subsequent technique
The described flash cell of middle protection.And described 3rd side wall 102 may be used for adjusting the source line being subsequently formed
Position with bit line.
Refer to Figure 17, in the Semiconductor substrate 100 of described 3rd side wall 102 both sides, carry out ion note
Enter, form source line 103 and bit line 104.
In the Semiconductor substrate 100 of described first side wall 403 both sides, carry out ion implanting, form source line
103 and bit line 104.The ion of described ion implanting is N-type ion, including the one in phosphorus, gallium or arsenic
Or several ion, the ion dose of described ion implanting is 1 × 1015atom/cm3～8 × 1015atom/cm3,
Energy is 10keV～50keV.
Embodiments of the invention additionally provide a kind of flash memory unit structure using said method to be formed.
Refer to Figure 17, described flash cell includes: Semiconductor substrate 100；It is positioned at Semiconductor substrate 100
The floating gate dielectric layer 205 on surface and the floating boom 206 being positioned at described floating gate dielectric layer 205 surface；It is positioned at described
Floating boom 206 surface and cover the control gate dielectric layer 305 of described floating gate side walls and be positioned at described control gate
The control gate 306 on dielectric layer 305 surface；Run through described control gate 306, control gate dielectric layer 305, float
Grid 206 and the groove of floating gate dielectric layer 206；It is positioned at control gate 306 sidewall surfaces of described groove
Second side wall 405, is positioned at the first side wall 403 of described control gate 306 top surface；It is positioned at described first
Side wall 403 surface, the second side wall 405 surface and the tunnel oxide 501 on groove inner wall surface；It is positioned at institute
State tunnel oxide 501 surface, fill full described groove, and surface is neat with the first side wall 403 surface
Flat wordline 502；It is positioned at the cap 503 on described wordline 502 surface；Be positioned at described first side wall 403,
Control gate 306, the 3rd side wall 102 of control gate dielectric layer 305 sidewall surfaces；It is positioned at described 3rd side wall
Source line 103 in the Semiconductor substrate 100 of 102 both sides and bit line 104.
The material of described floating gate dielectric layer 205 is silicon oxide, and thickness is 80 angstroms-100 angstroms.
The material of described floating boom 206 is polysilicon, and thickness is 200 angstroms～600 angstroms.
The material of described control gate dielectric layer 305 is ONO(oxide-nitride-oxide) stacking knot
Structure, thickness is 100 angstroms～200 angstroms.
The material of described control gate 306 is polysilicon, and the thickness of described control gate 306 is 500 angstroms～1000
Angstrom.
The material of described first side wall the 403, second side wall 405 and the 3rd side wall 102 is silicon nitride.
The material of described wordline 502 is polysilicon.
The material of described cap 503 is silicon oxide, and thickness is 200 angstroms～500 angstroms.
The material of described tunnel oxide 501 is silicon oxide, and the thickness of described tunnel oxide 501 is 100
Angstrom～150 angstroms.
In the present embodiment, between described control gate 306 and the second side wall 405, also there is silicon oxide layer 404,
The thickness of described silicon oxide layer is 50 angstroms～100 angstroms, and described silicon oxide layer 404 can reduce the second side wall
Lattice mismatch between 404 and control gate 306, improves the isolation effect of described second side wall 405.
Described flash memory also includes the source line being positioned at the Semiconductor substrate 100 of described 3rd side wall 102 both sides
103 and bit line 104, described source line 103 and bit line 104 part be positioned at below control gate 306, can disappear
Except the parasitic channel below described control gate.
The control gate 306 of described flash cell and control gate dielectric layer 305 cover the top of floating boom 306
Surface and described floating boom 306 are away from the sidewall surfaces of wordline 502 side.Compared with prior art, improve
Described control gate 306 and the overlapping area of floating boom 206, improve described control gate 306 and floating boom 206
Between electric capacity, thus improve the control gate coupling efficiency to floating boom in flash cell, and then can carry
The wiping/writing performance of high flash memory.
Although present disclosure is as above, but the present invention is not limited to this.Any those skilled in the art,
Without departing from the spirit and scope of the present invention, all can make various changes or modifications, therefore the guarantor of the present invention
The scope of protecting should be as the criterion with claim limited range.
Claims (6)
1. the forming method of a flash cell, it is characterised in that including:
Thering is provided Semiconductor substrate, described semiconductor substrate surface is formed with covering part semiconductor substrate surface
First medium layer and be positioned at the floating gate material layer on first medium layer surface；
Formed and cover described semiconductor substrate surface, first medium layer and floating gate material layer sidewall and floating boom
The second dielectric layer of material layer top surface, and it is positioned at the control gate material on described second dielectric layer surface
Layer；
Form the hard mask layer with opening in described control gate material surface, described opening is positioned at floating boom
Directly over material layer, and the width of described opening is more than the width of floating gate material layer；
The first side wall covering hard mask layer sidewall is formed in described opening；
With described first side wall and hard mask layer as mask, with described second dielectric layer as stop-layer, etching
Described control gate material layer, forms the first groove；
In described first groove, formed and be positioned at the second side wall on described control gate material layer sidewall；
With described Semiconductor substrate as stop-layer, along described first recess etch second dielectric layer, floating boom material
The bed of material and first medium layer, form the second groove and be positioned at the floating boom of the second groove both sides；
Tunnel oxide is formed on described second groove inner wall surface；
Formed on described tunnel oxide surface and fill full described first groove, the wordline of the second groove；
Remove described hard mask layer and the part that is positioned under described hard mask layer controls gate material layer and part the
Second medium layer, forms control gate, and described control gate covers and is positioned at the top surface of floating boom and away from wordline
The second dielectric layer of side sidewall surfaces.
The forming method of flash cell the most according to claim 1, it is characterised in that also include: formed
Before described second side wall, form silicon oxide layer in described control gate material layer sidewall surfaces.
The forming method of flash cell the most according to claim 1, it is characterised in that described first medium
The width of layer and floating gate material layer is 0.2 micron～0.4 micron, and the thickness of described floating gate material layer is 200
Angstrom～600 angstroms.
The forming method of flash cell the most according to claim 3, it is characterised in that the width of described opening
Degree is 0.3 micron～0.5 micron.
The forming method of flash cell the most according to claim 1, it is characterised in that also include: in institute
Carry out being lightly doped ion implanting in stating the Semiconductor substrate of the first side wall both sides, formed and district is lightly doped；?
Described semiconductor substrate surface is formed and covers described control gate dielectric layer, control gate and the first side wall sidewall
The 3rd side wall；In the Semiconductor substrate of described 3rd side wall both sides, carry out ion implanting, form source
Line and bit line, part source line and part bit line are positioned at below the control gate of semiconductor substrate surface.
The forming method of flash cell the most according to claim 5, it is characterised in that described in be lightly doped from
The dopant ion that son injects and ion implanting uses is N-type ion.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310371237.6A CN103426826B (en) | 2013-08-22 | 2013-08-22 | Flash cell and forming method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310371237.6A CN103426826B (en) | 2013-08-22 | 2013-08-22 | Flash cell and forming method thereof |
Publications (2)
| Publication Number | Publication Date |
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| CN103426826A CN103426826A (en) | 2013-12-04 |
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| CN104091802B (en) * | 2014-07-23 | 2016-08-24 | 上海华虹宏力半导体制造有限公司 | Memory cell and forming method thereof and read method |
| CN104157616B (en) * | 2014-08-26 | 2017-02-22 | 上海华虹宏力半导体制造有限公司 | Flash memory unit and formation method thereof |
| CN104916562B (en) * | 2015-04-17 | 2018-01-26 | 上海华虹宏力半导体制造有限公司 | Flash cell coupling ratio monitoring method |
| CN105070690A (en) * | 2015-08-11 | 2015-11-18 | 上海华虹宏力半导体制造有限公司 | Flash memory device formation method |
| CN105261594B (en) * | 2015-09-02 | 2021-01-29 | 董业民 | Method for forming self-aligned split gate flash memory |
| CN105336705B (en) * | 2015-12-04 | 2018-06-26 | 上海华虹宏力半导体制造有限公司 | The manufacturing method of flash memory structure |
| CN106298793B (en) * | 2016-09-30 | 2019-02-05 | 上海华虹宏力半导体制造有限公司 | Autoregistration grid flash memory device and its manufacturing method |
| CN108565249B (en) * | 2018-06-08 | 2020-07-31 | 上海华虹宏力半导体制造有限公司 | Method for forming flash memory side wall |
| CN110164865B (en) * | 2019-05-23 | 2021-06-18 | 上海华虹宏力半导体制造有限公司 | Method for manufacturing embedded flash memory |
| CN111799266B (en) * | 2020-08-26 | 2024-01-26 | 上海华虹宏力半导体制造有限公司 | Embedded flash memory, manufacturing method thereof and embedded semiconductor device |
| CN111834245B (en) * | 2020-08-26 | 2022-09-23 | 上海华虹宏力半导体制造有限公司 | Semiconductor PCM structure and detection method thereof |
| CN111987105B (en) * | 2020-09-29 | 2023-09-08 | 上海华虹宏力半导体制造有限公司 | Manufacturing method of split gate type memory |
| CN112164655B (en) * | 2020-09-29 | 2024-03-15 | 上海华虹宏力半导体制造有限公司 | Method for manufacturing flash memory device |
| CN112397391B (en) * | 2020-11-17 | 2022-10-28 | 华虹半导体(无锡)有限公司 | Semiconductor device structure and manufacturing method of flash memory device |
| CN113394222B (en) * | 2021-06-18 | 2024-05-24 | 上海华虹宏力半导体制造有限公司 | Flash memory preparation method |
| CN113675205B (en) * | 2021-08-20 | 2024-04-19 | 上海华虹宏力半导体制造有限公司 | Method for manufacturing semiconductor device |
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| CN102637645A (en) * | 2011-02-10 | 2012-08-15 | 上海宏力半导体制造有限公司 | Preparation method of memory |
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