CN105070690A - Flash memory device formation method - Google Patents
Flash memory device formation method Download PDFInfo
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- CN105070690A CN105070690A CN201510490480.9A CN201510490480A CN105070690A CN 105070690 A CN105070690 A CN 105070690A CN 201510490480 A CN201510490480 A CN 201510490480A CN 105070690 A CN105070690 A CN 105070690A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
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Abstract
The invention provides a flash memory device formation method which is characterized by, after forming a thinner side wall, forming a sixth medium layer on the side wall; and then, etching the sixth medium layer, a second medium layer and a floating gate layer in sequence, and keeping a part of the sixth medium layer arranged on the surface of the side wall, wherein the etching no longer adopts phosphoric acid soaking, thereby preventing the device problem due to phosphoric acid soaking.
Description
Technical field
The present invention relates to field of semiconductor manufacture, particularly relate to a kind of formation method of flush memory device.
Background technology
The advantages such as flash memory is convenient with it, storage density is high, good reliability become the focus studied in non-volatility memorizer.Since coming out from first flash memory products 1980s, along with the development of technology and each electronic product are to the demand stored, flash memory is widely used in mobile phone, notebook, in the mobile and communication apparatus such as palmtop PC and u dish, flash memory is a kind of nonvolatile memory, its operation principles is that the critical voltage by changing transistor or memory cell controls the switch of gate pole passage to reach the object storing data, storage data in memory can not be disappeared because of power interruptions, and flash memory is electric erasable and a kind of special construction of programmable read-only memory.Nowadays flash memory has occupied most of market share of non-volatile semiconductor memory, becomes non-volatile semiconductor memory with fastest developing speed.
Please refer to Fig. 1 to Fig. 6, Fig. 1 to Fig. 6 is the part-structure schematic diagram in prior art in flash memory forming process, and concrete, flash memory forming step comprises:
Substrate 10 is provided, described substrate 10 is formed with successively first medium layer 21, floating gate layer 31, second dielectric layer 22, control grid layer 32 and the 3rd dielectric layer 23, wherein, described 3rd dielectric layer 23 is provided with groove, described groove exposes the surface of described control grid layer 32, the sidewall surfaces of described groove is formed with the 4th dielectric layer 24, as shown in Figure 1;
Etch described control grid layer 32, expose described second dielectric layer 22, as shown in Figure 2;
Form oxide layer (scheming non-label) then on the surface of control grid layer 32 sidewall, form side wall 25 on the surface of described 4th dielectric layer 24 and oxide layer, as shown in Figure 3;
Etch described second dielectric layer 22 and floating gate layer 31, expose described first medium layer 21, as shown in Figure 4;
Use phosphoric acid etching to remove part side wall 25, expose the second dielectric layer 22 on the surface at described floating gate layer 31 turning, as shown in Figure 5;
Pre-embossed etching off, except the second dielectric layer 22 be positioned on the surface at floating gate layer 31 turning and the first medium layer 21 exposed, is convenient to the follow-up dielectric layer that regrows, and is grown wordline.
But, when using phosphoric acid to carry out back etching to side wall 25, can whole wafer be placed in the container of phosphoric acid, certain infringement can be caused to device, cause the generation of defect.
Summary of the invention
The object of the present invention is to provide a kind of formation method of flush memory device, can avoid using phosphoric acid dip, guarantee the performance of flush memory device.
To achieve these goals, the present invention proposes a kind of formation method of flush memory device, comprise step:
Substrate is provided, described substrate is formed with successively first medium layer, floating gate layer, second dielectric layer, control grid layer and the 3rd dielectric layer, described 3rd dielectric layer is provided with groove, and described groove exposes the surface of described control grid layer, and the sidewall surfaces of described groove is formed with the 4th dielectric layer;
Etch described control grid layer, expose described second dielectric layer;
Form oxide layer and side wall successively on the surface of control grid layer sidewall, described side wall is close to the sidewall surfaces of described 4th dielectric layer;
The 6th dielectric layer is formed on the surface of described side wall;
Etch described 6th dielectric layer, second dielectric layer and floating gate layer successively, expose described first medium layer, and reserve part the 6th dielectric layer is positioned at the surface of described side wall;
Etching off is except the 6th dielectric layer retained, the second dielectric layer being positioned at floating gate layer corner and the first medium layer exposed in the same time, exposes the surface of described substrate.
Further, in the formation method of described flush memory device, after etching removes the 6th dielectric layer and the second dielectric layer being positioned at floating gate layer corner and first medium layer retained, to regrow the 7th dielectric layer at described side wall and floating gate layer sidewall and substrate surface.
Further, in the formation method of described flush memory device, fill in described groove and form wordline.
Further, in the formation method of described flush memory device, described first medium layer is silica; Second dielectric layer is silicon oxide/silicon nitride/silicon oxide composite bed; 3rd dielectric layer is silicon nitride; The material of the 4th dielectric layer is silica.
Further, in the formation method of described flush memory device, the material of described floating gate layer and control grid layer is polysilicon.
Further, in the formation method of described flush memory device, described side wall material is silicon nitride.
Further, in the formation method of described flush memory device, described 6th dielectric layer is silica.
Further, in the formation method of described flush memory device, described 6th dielectric layer of disposable etching, second dielectric layer and floating gate layer in same equipment board.
Further, in the formation method of described flush memory device, in different platform, etch described 6th dielectric layer, second dielectric layer and floating gate layer respectively.
Compared with prior art, beneficial effect of the present invention is mainly reflected in: after forming thinner side wall, then on side wall, the 6th dielectric layer is formed, then the 6th dielectric layer, second dielectric layer and floating gate layer is etched successively, reserve part the 6th dielectric layer is positioned at the surface of side wall, now etch and do not re-use phosphoric acid dip, avoid the component problem that phosphoric acid dip causes.
Accompanying drawing explanation
Fig. 1 to Fig. 6 is the part-structure schematic diagram in prior art in flash memory forming process;
Fig. 7 is the flow chart of the formation method of flush memory device in one embodiment of the invention;
Fig. 8 to Figure 14 is the structural representation in one embodiment of the invention in flash memory forming process.
Embodiment
Be described in more detail below in conjunction with the formation method of schematic diagram to flush memory device of the present invention, which show the preferred embodiments of the present invention, should be appreciated that those skilled in the art can revise the present invention described here, and still realize advantageous effects of the present invention.Therefore, following description is appreciated that extensively knowing for those skilled in the art, and not as limitation of the present invention.
In order to clear, whole features of practical embodiments are not described.They in the following description, are not described in detail known function and structure, because can make the present invention chaotic due to unnecessary details.Will be understood that in the exploitation of any practical embodiments, a large amount of implementation detail must be made to realize the specific objective of developer, such as, according to regarding system or the restriction about business, change into another embodiment by an embodiment.In addition, will be understood that this development may be complicated and time-consuming, but be only routine work to those skilled in the art.
In the following passage, more specifically the present invention is described by way of example with reference to accompanying drawing.According to the following describes and claims, advantages and features of the invention will be clearer.It should be noted that, accompanying drawing all adopts the form that simplifies very much and all uses non-ratio accurately, only in order to object that is convenient, the aid illustration embodiment of the present invention lucidly.
Please refer to Fig. 7, in the present embodiment, propose a kind of formation method of flush memory device, comprise step:
S100: substrate is provided, described substrate is formed with successively first medium layer, floating gate layer, second dielectric layer, control grid layer and the 3rd dielectric layer, described 3rd dielectric layer is provided with groove, described groove exposes the surface of described control grid layer, and the sidewall surfaces of described groove is formed with the 4th dielectric layer;
S200: etch described control grid layer, exposes described second dielectric layer;
S300: form oxide layer and side wall successively on the surface of control grid layer sidewall, described side wall is close to the sidewall surfaces of described 4th dielectric layer;
S400: form the 6th dielectric layer on the surface of described side wall;
S500: etch described 6th dielectric layer, second dielectric layer and floating gate layer successively, expose described first medium layer, and reserve part the 6th dielectric layer is positioned at the surface of described side wall;
S600: etching off is except the 6th dielectric layer retained, the second dielectric layer being positioned at floating gate layer corner and the first medium layer exposed in the same time, exposes the surface of described substrate.
Concrete, please refer to Fig. 8, in the present embodiment, described substrate 10 is formed with successively first medium layer 210, floating gate layer 310, second dielectric layer 220, control grid layer 320 and the 3rd dielectric layer 230, wherein, the 3rd dielectric layer 230 is provided with groove, described groove exposes the surface of described control grid layer 320, the sidewall surfaces of described groove is formed with the 4th dielectric layer 240, and wherein, described first medium layer 210 is silica; Second dielectric layer 220 can be silicon oxide/silicon nitride/silicon oxide composite bed (ONO), also can be single-layer medium layer; 3rd dielectric layer 230 is silicon nitride; The material of the 4th dielectric layer 240 is silica.The material of described floating gate layer 310 and control grid layer 320 is polysilicon.
Please refer to Fig. 9, etch described control grid layer 320, expose described second dielectric layer 220, wherein, because second dielectric layer 220 can be the dielectric layer of ONO combination, therefore after the described control grid layer 320 of etching, also can carry out certain process to second dielectric layer 220, remove silica and the silicon nitride of second dielectric layer 220 upper surface, expose the silica of the bottom, thus be conducive to the carrying out of subsequent technique, in addition, can also when etching control grid layer 320, etching two-layer before second dielectric layer 220 is removed by disposable etching, only retain last one deck silica.
Please refer to Figure 10; oxide layer (figure is label) and side wall 250 is formed successively on the surface of control grid layer 320 sidewall; described side wall 250 is also close to the sidewall surfaces of described 4th dielectric layer 240; wherein; oxide layer adopts high-temperature thermal oxidation method to be formed; for the protection of the sidewall of control grid layer 320, the material of described side wall 250 is generally silicon nitride, and it can also be used for follow-up etching stop layer.
Please refer to Figure 11, form the 6th dielectric layer 260 on the surface of described side wall 250, wherein, the 6th dielectric layer 260 can be formed in the surface of described side wall 250, the 3rd dielectric layer 230, the 4th dielectric layer 240 and second dielectric layer 220.
Then, please refer to Figure 12, etch described 6th dielectric layer 260, second dielectric layer 220 and floating gate layer 310 simultaneously, expose described first medium layer 210, and reserve part the 6th dielectric layer 260 is positioned at the surface of described side wall 250; This etching can use common gas or acid solution to etch, and does not re-use the side wall 250 of phosphoric acid to silicon nitride and carries out back etching, wafer so just can be avoided to be immersed in the infringement brought in phosphoric acid.In addition, the etching of the 6th dielectric layer 260, second dielectric layer 220 and floating gate layer 310 can use the disposable etching of acid solution, to save processing step in same equipment.
Please refer to Figure 13; etching removes the 6th dielectric layer 260 retained, the second dielectric layer 220 being positioned at floating gate layer 310 corner and the first medium layer 210 exposed successively; expose the surface of described substrate 100 and the turning of floating gate layer 310; because etching can cause damage to first medium layer 210 etc.; comparatively good device can be formed in order to follow-up; usually the first medium layer 210 etc. removed and suffer damage can first be etched, and then the good dielectric layer that regrows, be convenient to form good device.
Please refer to Figure 14, after etching removes the 6th dielectric layer 260 retained and the second dielectric layer 220 being positioned at floating gate layer 310 corner, to regrow the 7th dielectric layer 270 at described side wall 250 and floating gate layer 310 surface, then, fill in described groove and form wordline 400.The material of described wordline 400 is polysilicon, and the material of described 7th dielectric layer 270 is silica.Wherein, the step forming wordline 400 comprises, and polysilicon can be formed in the surface of described 3rd dielectric layer 230 and the 4th dielectric layer 240, adopts chemical mechanical milling tech etching to remove unnecessary polysilicon, thus forms wordline 400.
To sum up, in the formation method of the flush memory device provided in the embodiment of the present invention, after forming thinner side wall, then on side wall, the 6th dielectric layer is formed, then the 6th dielectric layer, second dielectric layer and floating gate layer is etched successively, reserve part the 6th dielectric layer is positioned at the surface of side wall, now etches and does not re-use phosphoric acid dip, avoid the component problem that phosphoric acid dip causes.
Above are only the preferred embodiments of the present invention, any restriction is not played to the present invention.Any person of ordinary skill in the field; in the scope not departing from technical scheme of the present invention; the technical scheme disclose the present invention and technology contents make the variations such as any type of equivalent replacement or amendment; all belong to the content not departing from technical scheme of the present invention, still belong within protection scope of the present invention.
Claims (9)
1. a formation method for flush memory device, is characterized in that, comprise step:
Substrate is provided, described substrate is formed with successively first medium layer, floating gate layer, second dielectric layer, control grid layer and the 3rd dielectric layer, described 3rd dielectric layer is provided with groove, and described groove exposes the surface of described control grid layer, and the sidewall surfaces of described groove is formed with the 4th dielectric layer;
Etch described control grid layer, expose described second dielectric layer;
Form oxide layer and side wall successively on the surface of control grid layer sidewall, described side wall is close to the sidewall surfaces of described 4th dielectric layer;
The 6th dielectric layer is formed on the surface of described side wall;
Etch described 6th dielectric layer, second dielectric layer and floating gate layer successively, expose described first medium layer, and reserve part the 6th dielectric layer is positioned at the surface of described side wall;
Etching off is except the 6th dielectric layer retained, the second dielectric layer being positioned at floating gate layer corner and the first medium layer exposed in the same time, exposes the surface of described substrate.
2. the formation method of flush memory device as claimed in claim 1, it is characterized in that, after etching removes the 6th dielectric layer retained and the second dielectric layer being positioned at floating gate layer corner, to regrow the 7th dielectric layer at described side wall, floating gate layer sidewall and substrate surface.
3. the formation method of flush memory device as claimed in claim 2, is characterized in that, fills and form wordline in described groove.
4. the formation method of flush memory device as claimed in claim 1, it is characterized in that, described first medium layer is silica; Second dielectric layer is the composite bed of silicon oxide/silicon nitride/silicon oxide; 3rd dielectric layer is silicon nitride; The material of the 4th dielectric layer is silica.
5. the formation method of flush memory device as claimed in claim 1, it is characterized in that, the material of described floating gate layer and control grid layer is polysilicon.
6. the formation method of flush memory device as claimed in claim 1, it is characterized in that, described side wall material is silicon nitride.
7. the formation method of flush memory device as claimed in claim 1, it is characterized in that, described 6th dielectric layer is silica.
8. the formation method of flush memory device as claimed in claim 1, is characterized in that, described 6th dielectric layer of disposable etching, second dielectric layer and floating gate layer in same equipment board.
9. the formation method of flush memory device as claimed in claim 1, is characterized in that, etch described 6th dielectric layer, second dielectric layer and floating gate layer in different platform respectively.
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| CN201510490480.9A CN105070690A (en) | 2015-08-11 | 2015-08-11 | Flash memory device formation method |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110459478A (en) * | 2019-08-23 | 2019-11-15 | 上海华虹宏力半导体制造有限公司 | Split-gate flash memory and forming method thereof |
| CN111613618A (en) * | 2020-05-26 | 2020-09-01 | 上海华虹宏力半导体制造有限公司 | Semiconductor device and method for manufacturing the same |
| CN113675205A (en) * | 2021-08-20 | 2021-11-19 | 上海华虹宏力半导体制造有限公司 | Method for manufacturing semiconductor device |
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| CN102593062A (en) * | 2012-03-09 | 2012-07-18 | 上海宏力半导体制造有限公司 | Split-gate type flash memory structure and manufacturing method thereof |
| CN103426826A (en) * | 2013-08-22 | 2013-12-04 | 上海宏力半导体制造有限公司 | Flash memory unit and formation method thereof |
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Patent Citations (3)
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| US20080026528A1 (en) * | 2000-09-22 | 2008-01-31 | Yuan Jack H | Non-volatile Memory Cell Array Having Discontinuous Source and Drain Diffusions Contacted by Continuous Bit Line Conductors and Methods of Forming |
| CN102593062A (en) * | 2012-03-09 | 2012-07-18 | 上海宏力半导体制造有限公司 | Split-gate type flash memory structure and manufacturing method thereof |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110459478A (en) * | 2019-08-23 | 2019-11-15 | 上海华虹宏力半导体制造有限公司 | Split-gate flash memory and forming method thereof |
| CN111613618A (en) * | 2020-05-26 | 2020-09-01 | 上海华虹宏力半导体制造有限公司 | Semiconductor device and method for manufacturing the same |
| CN113675205A (en) * | 2021-08-20 | 2021-11-19 | 上海华虹宏力半导体制造有限公司 | Method for manufacturing semiconductor device |
| CN113675205B (en) * | 2021-08-20 | 2024-04-19 | 上海华虹宏力半导体制造有限公司 | Method for manufacturing semiconductor device |
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