CN103066025B - Method for coupling of top source line of separating grid flash memory - Google Patents
Method for coupling of top source line of separating grid flash memory Download PDFInfo
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- CN103066025B CN103066025B CN201210576912.4A CN201210576912A CN103066025B CN 103066025 B CN103066025 B CN 103066025B CN 201210576912 A CN201210576912 A CN 201210576912A CN 103066025 B CN103066025 B CN 103066025B
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Abstract
A method for coupling of a top source line of separating grid flash memory comprises that S1, a tunneling oxidation layer is formed on a semiconductor substrate; S2, a floating grid polycrystalline silicon layer and a silicon nitride layer are formed on one side of the tunneling oxidation layer; S3, etching for the floating grid polycrystalline silicon layer is carried out; S4, a self-aligned oxide side wall is formed, and local etching for the floating grid polycrystalline silicon layer is carried out; S5, back etching for the self-aligned oxide side wall is carried out, S6, a high-temperature oxide layer is deposited; S7, a polycrystalline silicon layer is deposited; S8, a polycrystalline silicon layer side wall is formed; S9, a high-temperature oxide layer on a second upper surface of the semiconductor substrate is removed; and S10, the polycrystalline silicon layer is deposited, and mechanical grinding is carried out. According to the method for the coupling of the top source line of the separating grid flash memory, existing technological processes are simplified, process windows of the coupling of the top source line of the separating grid flash memory are increased, and stability of devices is improved.
Description
Technical field
The present invention relates to technical field of semiconductors, the method for the top source line coupling of more particularly, to a kind of separate gate flash memory.
Background technology
With the development of semiconductor technology, flash memory has obtained widely should as a kind of non-volatility memorizer
With.Compared with SRAM and the such volatile storage of dynamic RAM, non-volatility memorizer is to work as
When power supply temporarily interrupts or device is indefinitely in off-position, remain to keep a kind of element of data storage, and the former is then
The information of storage can be lost.
Preferably non-volatility memorizer should be able to provide every minimum cost, high density, quick access rate, low work(
Consumption, and big operating temperature range etc..Meanwhile, with scientific and technological progress, the reliability that people store to device, data preserve
The avoiding of the inefficacy mechanism such as characteristic and resistance to crosstalk characteristic it is also proposed higher requirement.
Normally, non-volatility memorizer is all using a FGS floating gate structure, electric charge via silicon substrate or drain electrode end, across
One layer insulating be injected among floating boom and store with floating boom in, this process becomes programming；Electric charge is removed from floating-gate device,
Referred to as wipe.Because electric charge increases on floating boom, according to floating gate charge coupling model, floating boom threshold voltage can raise, and makes
Device is changed to high-voltage state.Through floating gate charge erasing, device can be changed to low-voltage state.
But, the method for the top source line coupling of traditional separate gate flash memory, preparation process is loaded down with trivial details, and process window is little, produces
Product stability is not high.
Therefore it is directed to the problem that prior art exists, this case designer, by being engaged in the industry experience for many years, actively studies
Improvement, then has the method that a kind of top source line of separate gate flash memory of the present invention couples.
Content of the invention
The present invention be directed in prior art, the method for the traditional top source line coupling of separate gate flash memory, preparation process
Loaded down with trivial details, process window is little, the method that the not high defect of product stability provides a kind of top source line coupling of separate gate flash memory.
In order to solve the above problems, the method that the present invention provides a kind of top source line coupling of separate gate flash memory, described side
Method includes：
Execution step S1：Semiconductor substrate is provided, and forms tunneling oxide layer on the semiconductor substrate；
Execution step S2：Sequentially form floating boom polycrystalline in the side differing from described Semiconductor substrate of described tunneling oxide layer
Silicon layer and silicon nitride layer, and photoetching, etching are carried out to described silicon nitride layer；
Execution step S3：With described silicon nitride layer as mask, described floating gate polysilicon layer is performed etching；
Execution step S4：Surface deposition oxide on the side wall and described floating gate polysilicon layer of described silicon nitride layer
Layer, and described oxide skin(coating) is etched by etching technics, autoregistration oxide side walls are formed with the side wall in described silicon nitride layer,
And local etching is located at the described floating gate polysilicon layer between described autoregistration oxide side walls, until exposing local tunnel oxidation
First upper surface of layer；
Execution step S5：Described autoregistration oxide side walls are carried out back carve using buffered oxide etch agent, expose position
Part floating gate polysilicon layer below described autoregistration oxide side walls, and the local tunneling oxide layer exposing is etched, directly
To the second upper surface exposing described Semiconductor substrate；
Execution step S6：Expose in described silicon nitride layer, described autoregistration oxide side walls, and described being etched
Second upper surface of Semiconductor substrate deposits described high-temperature oxydation nitride layer；
Execution step S7：Upper surface depositing polysilicon layer in described high-temperature oxydation nitride layer；
Execution step S8：Etch described polysilicon layer, described polycrystalline is formed with the surface inside described high temperature oxide layer
Sidewall silicon；
Execution step S9：Remove the high-temperature oxydation nitride layer of the second upper surface of Semiconductor substrate being formed at described exposure；
Execution step S10：Outside described high temperature oxide layer, described polysilicon sidewall, and the Semiconductor substrate exposing
Source polysilicon described in surface deposition, and carry out cmp.
Alternatively, described tunneling oxide layer adopts high temperature furnace pipe membrane formation process to prepare.
In sum, the method for the top source line coupling of separate gate flash memory of the present invention, simplifies existing process stream
Journey, increased the process window of the top source line coupling of separate gate flash memory, improves the stability of device.
Brief description
The flow chart that Fig. 1 show the method for top source line coupling of separate gate flash memory of the present invention；
Fig. 2 show the structural representation after floating gate polysilicon layer etching；
Fig. 3 show the structural representation of autoregistration oxide side walls；
Fig. 4 show autoregistration oxide side walls and returns structural representation after quarter；
Fig. 5 show the structural representation of high-temperature oxydation nitride layer；
Fig. 6 show the structural representation of polysilicon layer；
Fig. 7 show the structural representation of polysilicon sidewall；
Fig. 8 show the structural representation of the high-temperature oxydation nitride layer removing Semiconductor substrate；
Fig. 9 show the structural representation after source polysilicon deposit cmp.
Specific embodiment
For describing technology contents, structural feature, institute's reached purpose and effect of the invention in detail, below in conjunction with reality
Apply example and coordinate accompanying drawing to be described in detail.
Refer to Fig. 1, the flow chart that Fig. 1 show the method for top source line coupling of separate gate flash memory of the present invention.Described
The method of the top source line coupling of separate gate flash memory, including：
Execution step S1：Semiconductor substrate is provided, and forms tunneling oxide layer on the semiconductor substrate；
Execution step S2：Sequentially form floating boom polycrystalline in the side differing from described Semiconductor substrate of described tunneling oxide layer
Silicon layer and silicon nitride layer, and photoetching, etching are carried out to described silicon nitride layer；
Execution step S3：With described silicon nitride layer as mask, described floating gate polysilicon layer is performed etching；
Execution step S4：Surface deposition oxide on the side wall and described floating gate polysilicon layer of described silicon nitride layer
Layer, and described oxide skin(coating) is etched by etching technics, autoregistration oxide side walls are formed with the side wall in described silicon nitride layer,
And local etching is located at the described floating gate polysilicon layer between described autoregistration oxide side walls, until exposing local tunnel oxidation
First upper surface of layer；
Execution step S5：Described autoregistration oxide side walls are carried out back carve using buffered oxide etch agent, expose position
Part floating gate polysilicon layer below described autoregistration oxide side walls, and the local tunneling oxide layer exposing is etched, directly
To the second upper surface exposing described Semiconductor substrate；
Execution step S6：Expose in described silicon nitride layer, described autoregistration oxide side walls, and described being etched
Second upper surface of Semiconductor substrate deposits described high-temperature oxydation nitride layer；
Execution step S7：Upper surface depositing polysilicon layer in described high-temperature oxydation nitride layer；
Execution step S8：Etch described polysilicon layer, described polycrystalline is formed with the surface inside described high temperature oxide layer
Sidewall silicon；
Execution step S9：Remove the high-temperature oxydation nitride layer of the second upper surface of Semiconductor substrate being formed at described exposure；
Execution step S10：Outside described high temperature oxide layer, described polysilicon sidewall, and the Semiconductor substrate exposing
Source polysilicon described in surface deposition, and carry out cmp.
The method of the top source line coupling of separate gate flash memory of the present invention simplifies existing process flow process, increased and separates
The process window of the top source line coupling of flash memory in grating, improves the stability of device.
Method for describing the top source line coupling of separate gate flash memory of the present invention in detail, please continue to refer to Fig. 1, and combines ginseng
Read Fig. 2～Fig. 9.Fig. 2 show the structural representation after floating gate polysilicon layer etching.Fig. 3 show autoregistration oxide side walls
Structural representation.Fig. 4 show autoregistration oxide side walls and returns structural representation after quarter.Fig. 5 show high-temperature oxydation nitride layer
Structural representation.Fig. 6 show the structural representation of polysilicon layer.Fig. 7 show the structural representation of polysilicon sidewall.Figure
8 structural representations showing the high-temperature oxydation nitride layer removing Semiconductor substrate.Fig. 9 show source polysilicon and deposits and change
Learn the structural representation after mechanical lapping.
The method of the top source line coupling of described separate gate flash memory, including：
Execution step S1：Semiconductor substrate 11 is provided, and tunneling oxide layer 12 is formed on described Semiconductor substrate 11；
Wherein, described tunneling oxide layer 12 is the required dielectric oxide film of programming, preserves because its quality is related to data
Characteristic, so in the present invention, it is preferred to, using the high temperature furnace pipe membrane formation process preparation of high-quality, to reduce described tunnel oxidation
Layer 12 issuable defect.
Execution step S2：Sequentially form floating boom in the side differing from described Semiconductor substrate 11 of described tunneling oxide layer 12
Polysilicon layer 13 and silicon nitride layer 14, and photoetching, etching are carried out to described silicon nitride layer 14；
Execution step S3：With described silicon nitride layer 14 as mask, described floating gate polysilicon layer 13 is performed etching；
Execution step S4：Surface deposition oxidation on the side wall and described floating gate polysilicon layer 13 of described silicon nitride layer 14
Nitride layer, and described oxide skin(coating) is etched by etching technics, autoregistration oxide is formed with the side wall in described silicon nitride layer 14
Side wall 15, and local etching is located at the described floating gate polysilicon layer 13 between described autoregistration oxide side walls 15, until exposing
First upper surface 121 of local tunneling oxide layer 12；
Execution step S5：Described autoregistration oxide side walls 15 are carried out back carve using buffered oxide etch agent, expose
Positioned at the part floating gate polysilicon layer 13 of described autoregistration oxide side walls 15 lower section, and the local tunneling oxide layer 12 that will expose
The first upper surface 121 etch, until expose described Semiconductor substrate 11 the second upper surface 111；
Execution step S6：Sudden and violent in described silicon nitride layer 14, described autoregistration oxide side walls 15, and described being etched
Second upper surface 111 of the Semiconductor substrate 11 of dew deposits described high-temperature oxydation nitride layer 16；
Execution step S7：Upper surface depositing polysilicon layer 17 in described high-temperature oxydation nitride layer 16；
Execution step S8：Etch described polysilicon layer 17, and formed on the surface of described high temperature oxide layer 16 inner side described
Polysilicon sidewall 18；
Execution step S9：Remove the high-temperature oxydation of the second upper surface 111 of Semiconductor substrate 11 being formed at described exposure
Nitride layer 16；
Execution step S10：In described high temperature oxide layer 16, described polysilicon sidewall 18, and the Semiconductor substrate exposing
Source polysilicon 19 described in surface deposition outside 11, and carry out cmp.
It is apparent that the method for the top source line coupling of separate gate flash memory of the present invention simplifies existing process flow process, increase
Add the process window of the top source line coupling of separate gate flash memory, improve the stability of device.
In sum, the method for the top source line coupling of separate gate flash memory of the present invention, simplifies existing process stream
Journey, increased the process window of the top source line coupling of separate gate flash memory, improves the stability of device.
Those skilled in the art all it will be appreciated that without departing from the spirit or scope of the present invention, can be to this
Bright carry out various modifications and variations.Thus, if any modification or modification fall into the protection of appended claims and equivalent
In the range of when it is believed that the present invention cover these modification and modification.
Claims (2)
1. a kind of method of the top source line coupling of separate gate flash memory is it is characterised in that methods described includes：
Execution step S1：Semiconductor substrate is provided, and forms tunneling oxide layer on the semiconductor substrate；
Execution step S2：Sequentially form floating gate polysilicon layer in the side differing from described Semiconductor substrate of described tunneling oxide layer
And silicon nitride layer, and photoetching, etching are carried out to described silicon nitride layer；
Execution step S3：With described silicon nitride layer as mask, described floating gate polysilicon layer is performed etching；
Execution step S4：Surface deposition oxide skin(coating) on the side wall and described floating gate polysilicon layer of described silicon nitride layer, and
Described oxide skin(coating) is etched by etching technics, autoregistration oxide side walls are formed with the side wall in described silicon nitride layer, and office
Portion's etching is located at the described floating gate polysilicon layer between described autoregistration oxide side walls, until expose local tunneling oxide layer it
First upper surface；
Execution step S5：Described autoregistration oxide side walls are carried out back carve using buffered oxide etch agent, expose and be located at institute
State the part floating gate polysilicon layer below autoregistration oxide side walls, and by the local exposing tunneling oxide layer etching, until sudden and violent
Reveal the second upper surface of described Semiconductor substrate；
Execution step S6：In partly leading of exposing of described silicon nitride layer, described autoregistration oxide side walls, and described being etched
Second upper surface deposit high-temperature oxydation nitride layer of body substrate；
Execution step S7：Upper surface depositing polysilicon layer in described high-temperature oxydation nitride layer；
Execution step S8：Etch described polysilicon layer, described polysilicon side is formed with the surface inside described high temperature oxide layer
Wall；
Execution step S9：Remove the high-temperature oxydation nitride layer of the second upper surface of Semiconductor substrate being formed at described exposure；
Execution step S10：In described high temperature oxide layer, described polysilicon sidewall, and the outer surface of the Semiconductor substrate exposing
Deposit source polysilicon, and carry out cmp.
2. the method for the top source line coupling of separate gate flash memory as claimed in claim 1 is it is characterised in that described tunnel aoxidizes
Layer is using the preparation of high temperature furnace pipe membrane formation process.
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| CN103839796A (en) * | 2014-03-17 | 2014-06-04 | 上海华虹宏力半导体制造有限公司 | Method for forming source electrode polycrystalline silicon |
| CN110112132B (en) * | 2019-04-28 | 2021-05-07 | 上海华虹宏力半导体制造有限公司 | Split-gate memory and manufacturing method thereof |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5972752A (en) * | 1997-12-29 | 1999-10-26 | United Semiconductor Corp. | Method of manufacturing a flash memory cell having a tunnel oxide with a long narrow top profile |
| CN1378242A (en) * | 2001-03-30 | 2002-11-06 | 华邦电子股份有限公司 | Method for producing floating grid in flash memory |
| US6849499B2 (en) * | 2000-06-28 | 2005-02-01 | Taiwan Semiconductor Manufacturing Company | Process for flash memory cell |
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2012
- 2012-12-26 CN CN201210576912.4A patent/CN103066025B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5972752A (en) * | 1997-12-29 | 1999-10-26 | United Semiconductor Corp. | Method of manufacturing a flash memory cell having a tunnel oxide with a long narrow top profile |
| US6849499B2 (en) * | 2000-06-28 | 2005-02-01 | Taiwan Semiconductor Manufacturing Company | Process for flash memory cell |
| CN1378242A (en) * | 2001-03-30 | 2002-11-06 | 华邦电子股份有限公司 | Method for producing floating grid in flash memory |
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