CN106803509B - Process manufacturing method for solving programming crosstalk failure of split-gate flash memory - Google Patents
Process manufacturing method for solving programming crosstalk failure of split-gate flash memory Download PDFInfo
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- CN106803509B CN106803509B CN201710079379.3A CN201710079379A CN106803509B CN 106803509 B CN106803509 B CN 106803509B CN 201710079379 A CN201710079379 A CN 201710079379A CN 106803509 B CN106803509 B CN 106803509B
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- 230000015654 memory Effects 0.000 title claims abstract description 71
- 238000000034 method Methods 0.000 title claims abstract description 47
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 41
- 230000008569 process Effects 0.000 title claims abstract description 19
- 238000005530 etching Methods 0.000 claims abstract description 24
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims abstract description 18
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 14
- 230000001681 protective effect Effects 0.000 claims abstract description 10
- 238000004380 ashing Methods 0.000 claims abstract description 4
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 claims description 16
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 11
- 229910000147 aluminium phosphate Inorganic materials 0.000 claims description 8
- 239000000203 mixture Substances 0.000 claims description 6
- 239000000377 silicon dioxide Substances 0.000 claims description 6
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 4
- 238000002347 injection Methods 0.000 claims description 3
- 239000007924 injection Substances 0.000 claims description 3
- 235000012239 silicon dioxide Nutrition 0.000 claims description 3
- 230000007547 defect Effects 0.000 abstract description 5
- 238000001039 wet etching Methods 0.000 abstract description 4
- 229910052681 coesite Inorganic materials 0.000 description 3
- 229910052906 cristobalite Inorganic materials 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 229910052682 stishovite Inorganic materials 0.000 description 3
- 229910052905 tridymite Inorganic materials 0.000 description 3
- 238000002955 isolation Methods 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 229910004541 SiN Inorganic materials 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
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Abstract
The invention provides a process manufacturing method for solving the problem of programming crosstalk failure of a split gate flash memory, which comprises the following steps of: the first step is as follows: executing the manufacturing process of the split gate flash memory until the logic gate is etched by using the logic gate light resistance; the second step is as follows: ashing and wet stripping are carried out on the logic gate photoresist, and wet removal of the logic area gate hard mask is not carried out temporarily; thirdly, continuing to execute the manufacturing process of the split-gate flash memory until the word line is etched; the fourth step: removing the logic gate hard mask by a wet method; wherein dilute hydrofluoric acid may be used in the wet stripping treatment in the second step. The invention moves the 'wet method logic hard mask removing' process originally positioned after the logic gate etching to the word line etching, thereby avoiding the influence of the wet etching on the word line protective oxide layer, improving the word line appearance and reducing programming crosstalk failure. Meanwhile, diluted hydrofluoric acid can be used for removing the logic gate photoresist by a wet method, so that the defect problems of photoresist residue and the like are avoided.
Description
Technical Field
The invention relates to the field of semiconductor manufacturing, in particular to the field of split gate flash memory manufacturing; and, more particularly, to a process fabrication method for addressing split gate flash memory program cross talk failures.
Background
Flash memory has become a hot point of research in non-volatile memories due to its advantages of convenience, high storage density, good reliability and the like. Since the first flash memory product appeared in the eighties of the twentieth century, with the development of technology and the storage requirements of various electronic products, flash memory is widely used in mobile and communication devices such as mobile phones, notebooks, palm computers, U disks and the like.
Flash memory is a non-volatile memory, which operates on the principle of storing data by controlling the switching of gate channels by changing the threshold voltage of transistors or memory cells so that the data stored in the memory will not disappear due to power interruption, and is a special structure of electrically erasable and programmable read-only memory. Flash memory now occupies a large portion of the market share of non-volatile semiconductor memory, becoming the fastest growing non-volatile semiconductor memory.
Generally, a flash memory is a split gate structure or a stacked gate structure or a combination of the two structures. Due to the special structure of the split-gate flash memory, the split-gate flash memory shows unique performance advantages when being programmed and erased compared with a stacked gate flash memory, so that the split-gate flash memory has the advantages of high programming efficiency, capability of avoiding over-erasing due to the structure of a word line and the like, and is particularly widely applied.
A split gate flash memory program crosstalk failure (PTC) is common at the wafer edge, and the failed bit is at the edge of the flash memory array. This failure is often due to the word line (word line poly) being too low, causing subsequent ion implantation through the word line into the channel, causing a punch through failure of the word line transistor.
Accordingly, it is desirable to provide a process fabrication method that addresses the cross-talk failure in split gate flash memory programming.
Disclosure of Invention
The technical problem to be solved by the present invention is to provide a manufacturing method capable of solving the problem of programming crosstalk failure of the split gate flash memory, aiming at the above defects in the prior art.
In order to achieve the above technical object, according to the present invention, there is provided a manufacturing method for solving program crosstalk failure of a split gate flash memory, including:
the first step is as follows: executing the manufacturing process of the split gate flash memory until the logic gate is etched by using the logic gate light resistance;
the second step is as follows: ashing and wet stripping are carried out on the logic gate photoresist;
the third step: continuing to execute the manufacturing process of the split-gate flash memory until the word line etching is finished;
the fourth step: and removing the logic gate hard mask by a wet method.
Preferably, in the manufacturing method for solving the split gate flash memory programming crosstalk failure, in the second step, the logic gate hard mask is kept, so that the influence of wet removal of the logic gate hard mask on word line etching of the flash memory area is avoided.
Preferably, in the manufacturing method of the process for solving the program crosstalk failure of the split gate flash memory, in the fourth step, the logic gate hard mask is removed by using dilute hydrofluoric acid.
Preferably, in the manufacturing method for solving the split gate flash memory programming crosstalk failure, in the fourth step, phosphoric acid is used to remove the logic gate hard mask.
Preferably, in the manufacturing method for solving the split gate flash memory programming crosstalk failure, in the fourth step, the logic gate hard mask is removed by using hot phosphoric acid.
Preferably, in the manufacturing method for solving the problem of the split gate flash memory programming crosstalk failure, the composition of the logic gate hard mask is SiN.
Preferably, in the manufacturing method for solving the problem of the cross talk failure in the split gate flash memory programming, the composition of the logic gate hard mask is SiON.
Preferably, in the manufacturing method for solving the problem of the cross talk failure in the split-gate flash memory programming, the component of the logic gate hard mask is silicon dioxide SiO2。
Preferably, in the manufacturing method for solving the problem of the cross talk failure in the split gate flash memory programming, in the third step, the word line etching includes protective oxide layer etching.
Preferably, in the manufacturing method for solving the programming crosstalk failure of the split-gate flash memory, the split-gate flash memory comprises a flash memory area and a logic area.
The invention moves the 'wet method logic hard mask removing' process originally positioned after the logic gate etching to the word line etching, thereby avoiding the influence of the wet etching on the word line protective oxide layer, improving the word line appearance and reducing programming crosstalk failure. Meanwhile, the logic gate photoresist wet removal method can use dilute hydrofluoric acid, so that the defect problems of photoresist residue and the like are avoided.
Drawings
A more complete understanding of the present invention, and the attendant advantages and features thereof, will be more readily understood by reference to the following detailed description when considered in conjunction with the accompanying drawings wherein:
fig. 1 schematically shows the structure of a split-gate flash memory cell after logic gate etching.
Figure 2 schematically shows the structure of a split-gate flash memory cell after flash word line etching.
Fig. 3 schematically shows a flow chart of a process manufacturing method for solving the split gate flash memory programming crosstalk failure according to a preferred embodiment of the present invention.
It is to be noted, however, that the appended drawings illustrate rather than limit the invention. It is noted that the drawings representing structures may not be drawn to scale. Also, in the drawings, the same or similar elements are denoted by the same or similar reference numerals.
Detailed Description
In order that the present disclosure may be more clearly and readily understood, reference will now be made in detail to the present disclosure as illustrated in the accompanying drawings.
Fig. 1 schematically shows the structure of a gate-divided flash memory cell after logic gate etching, and fig. 2 schematically shows the structure of a gate-divided flash memory cell after flash memory word line etching. As shown in fig. 1 and 2, the split gate flash memory includes a flash memory region and a logic region. The importance of a word line protection oxide (word line protection oxide) on the appearance of the etched word line is generally higher as the oxide is thicker, and the channel under the word line cannot be influenced by the heavy doping injection of a subsequent bit line (bit line), so that the programming crosstalk failure is improved. More specifically, the thickness of the wordline protection oxide will affect the wordline polysilicon profile and the wordline recess height. A thicker wordline protection oxide layer has a greater process margin for wordline isolation sidewall etching.
In the manufacturing process of the split-gate flash memory, the thickness of the protective oxide layer on the word line polysilicon is influenced by the wet stripping process step of the logic gate photoresist and the logic gate hard mask removing process step, so that the problem of programming crosstalk failure of the split-gate flash memory can be solved by aiming at the wet stripping process step of the logic gate photoresist and the logic gate hard mask removing process step.
The present invention has been made based on the above analysis. In the method, the 'wet method logic hard mask removal' process originally positioned after the logic gate etching is moved to the position after the word line etching, so that the influence of the wet etching on the word line protective oxide layer is avoided, the word line appearance is improved, and the programming crosstalk failure is reduced. Meanwhile, diluted hydrofluoric acid can be used for removing the logic gate photoresist by a wet method, so that the defect problems of photoresist residue and the like are avoided.
Specific preferred embodiments of the present invention will be described below.
Fig. 3 schematically shows a flowchart of a process manufacturing method for solving the split gate flash memory programming crosstalk failure according to a first preferred embodiment of the present invention.
Specifically, as shown in fig. 3, the manufacturing method of the process for solving the program crosstalk failure of the split-gate flash memory according to the first preferred embodiment of the present invention includes:
first step S1: executing the manufacturing process of the split gate flash memory until the logic gate is etched by using the logic gate light resistance; the manufacturing process of the split-gate flash memory in the first step S1 is a conventional flow process. For example, the relevant well, isolation and active region structures are formed in the substrate 100, and the corresponding processes of forming the gate structure on the substrate 100 are performed.
Second step S2: ashing and wet stripping the logic gate photoresist in the logic region 300; in the second step S2, the logic gate hard mask 10 is temporarily remained, so as to avoid the influence of wet removal of the logic gate hard mask 10 on the word line etching of the flash memory region.
Third step S3: continuing to execute the manufacturing process of the split-gate flash memory until the word line polysilicon 30 of the flash memory area 200 is etched; specifically, in the third step, the word line etching includes etching of the protective oxide layer 20.
Fourth step S4: and removing the logic gate hard mask by a wet method.
Specifically, in specific examplesIn the fourth step, the logic gate hard mask may be removed using dilute hydrofluoric acid (DHF). Alternatively, in another specific example, in the fourth step, phosphoric acid (in particular, hot phosphoric acid, hot H) may be used3PO4) The logic gate hard mask is removed. Of course, alternatively, in another specific example, in the fourth step, dilute hydrofluoric acid (DHF) and phosphoric acid (in particular hot phosphoric acid, hot H) may be used3PO4) The combination of (1) removes the logic gate hard mask.
The hard mask of logic gate may be SiN, SiON or SiO2One kind of (1). For example, in a specific example, the composition of the logic gate hard mask is SiN. For example, alternatively, in another specific example, the composition of the logic gate hard mask is SiON. For example, alternatively, in another specific example, the composition of the logic gate hard mask is silicon dioxide, SiO2。
As described above, the importance of the word line protective oxide layer on the shape of the etched word line is generally the thicker the oxide layer is, the higher the word line is, and the channel under the word line is not affected by the subsequent heavy doping injection of the bit line, so that the programming crosstalk failure is improved.
In the manufacturing method for solving the programming crosstalk failure of the split-gate flash memory according to the preferred embodiment of the invention, the process of removing the logic hard mask by the wet method originally after the logic gate etching is moved to the position after the word line etching, so that the influence of the wet etching on the word line protective oxide layer is avoided, the word line appearance is improved, and the programming crosstalk failure is reduced. Meanwhile, diluted hydrofluoric acid can be used for removing the logic gate photoresist by a wet method, so that the defect problems of photoresist residue and the like are avoided.
In addition, it should be noted that the terms "first", "second", "third", and the like in the specification are used for distinguishing various components, elements, steps, and the like in the specification, and are not used for indicating a logical relationship or a sequential relationship between the various components, elements, steps, and the like, unless otherwise specified or indicated. Moreover, implementation of the method and/or system of embodiments of the present invention may include performing the selected task manually, automatically, or in combination. Moreover, the actual instrumentation and equipment according to embodiments of the method and/or system of the present invention may utilize an operating system to accomplish several selected tasks either in hardware, software, or a combination thereof. The present invention can be realized in hardware, software, or a combination of hardware and software. Any kind of computing system, or device adapted for carrying out the methods described herein, may be adapted to perform the functions described herein.
It is to be understood that while the present invention has been described in conjunction with the preferred embodiments thereof, it is not intended to limit the invention to those embodiments. It will be apparent to those skilled in the art from this disclosure that many changes and modifications can be made, or equivalents modified, in the embodiments of the invention without departing from the scope of the invention. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention are still within the scope of the protection of the technical solution of the present invention, unless the contents of the technical solution of the present invention are departed. Unless defined to the contrary, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Preferred methods, techniques, devices, and materials are described, but any methods, techniques, devices, or materials similar or equivalent to those described herein can be used in the practice or testing of the present invention. Structures described herein are to be understood as also referring to functional equivalents of such structures.
It is to be further understood that the present invention is not limited to the particular methodology, compounds, materials, manufacturing techniques, uses, and applications described herein, as such may, of course, vary. It is also to be understood that the terminology used herein is for the purpose of describing particular embodiments only, and is not intended to limit the scope of the present invention. It must be noted that, as used herein and in the appended claims, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. Thus, for example, reference to "an element" means a reference to one or more elements and includes equivalents thereof known to those skilled in the art. Similarly, as another example, reference to "a step" or "an apparatus" means a reference to one or more steps or apparatuses and may include sub-steps as well as sub-apparatuses. All conjunctions used should be understood in the broadest sense. Thus, the word "or" should be understood to have the definition of a logical "or" rather than the definition of a logical "exclusive or" unless the context clearly dictates otherwise. Structures described herein are to be understood as also referring to functional equivalents of such structures. Language that can be construed as approximate should be understood as such unless the context clearly dictates otherwise.
Claims (8)
1. A process manufacturing method for solving the problem of programming crosstalk failure of a split-gate flash memory is characterized by comprising the following steps:
the first step is as follows: executing the manufacturing process of the split gate flash memory until the logic gate is etched by using the logic gate light resistance;
the second step is as follows: ashing and wet stripping are carried out on the logic gate photoresist;
the third step: continuing to execute the manufacturing process of the split-gate flash memory until the word line etching is finished; in the third step, the word line etching comprises protective oxide layer etching; the thicker the word line protective oxide layer is, the higher the word line is, and the channel under the word line cannot be influenced by subsequent heavy doping injection of the bit line, so that programming crosstalk failure is improved;
the fourth step: removing the logic gate hard mask by a wet method;
in the second step, the logic gate hard mask is reserved, and the influence of wet removal of the logic gate hard mask on word line etching of the flash memory area is avoided.
2. The manufacturing method of solving the cross talk failure in split gate flash memory programming according to claim 1, wherein in the fourth step, the logic gate hard mask is removed by using diluted hydrofluoric acid.
3. The manufacturing method of a process for solving the program crosstalk failure of a split-gate flash memory according to claim 1, wherein in the fourth step, phosphoric acid is used to remove the logic gate hard mask.
4. The manufacturing method of a process for solving the program crosstalk failure of a split-gate flash memory according to claim 1, wherein in the fourth step, a logic gate hard mask is removed by using hot phosphoric acid.
5. The manufacturing method of solving the problem of cross talk failure in split gate flash memory as claimed in claim 1, wherein the hard mask of logic gate is composed of SiN.
6. The manufacturing method of solving the cross talk failure problem in split gate flash memory programming as claimed in claim 1, wherein the composition of the logic gate hard mask is SiON.
7. The manufacturing method of claim 1, wherein the hard mask of logic gate is made of silicon dioxide (SiO)2。
8. The manufacturing method for solving the problem of the programming crosstalk failure of the split-gate flash memory according to claim 1, wherein the split-gate flash memory comprises a flash memory area and a logic area.
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| CN110828463B (en) * | 2019-10-25 | 2022-05-31 | 上海华虹宏力半导体制造有限公司 | Layout and mask of split-gate flash memory and layout manufacturing method |
| CN111293120B (en) * | 2020-04-01 | 2023-05-26 | 上海华虹宏力半导体制造有限公司 | Split gate flash memory and preparation method thereof |
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| CN106158873A (en) * | 2014-12-17 | 2016-11-23 | 台湾积体电路制造股份有限公司 | There is the forming method of the gate-division type flash memory unit component of low-power logic device |
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| US9716097B2 (en) * | 2015-01-14 | 2017-07-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | Techniques to avoid or limit implant punch through in split gate flash memory devices |
| CN105140230B (en) * | 2015-08-11 | 2018-03-06 | 上海华虹宏力半导体制造有限公司 | Solves the manufacture method of Split-gate flash memory programming interference failure |
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| CN106158873A (en) * | 2014-12-17 | 2016-11-23 | 台湾积体电路制造股份有限公司 | There is the forming method of the gate-division type flash memory unit component of low-power logic device |
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