CN108565249B - Method for forming flash memory side wall - Google Patents
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- CN108565249B CN108565249B CN201810590030.0A CN201810590030A CN108565249B CN 108565249 B CN108565249 B CN 108565249B CN 201810590030 A CN201810590030 A CN 201810590030A CN 108565249 B CN108565249 B CN 108565249B
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- 238000000034 method Methods 0.000 title claims abstract description 57
- 238000005530 etching Methods 0.000 claims abstract description 146
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 claims description 34
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 claims description 22
- 239000000758 substrate Substances 0.000 claims description 18
- 125000006850 spacer group Chemical group 0.000 claims description 16
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 6
- 239000000203 mixture Substances 0.000 claims 1
- 239000004065 semiconductor Substances 0.000 abstract description 25
- 238000006243 chemical reaction Methods 0.000 abstract description 11
- 230000002159 abnormal effect Effects 0.000 abstract description 4
- 238000007517 polishing process Methods 0.000 description 6
- 239000000126 substance Substances 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 230000000873 masking effect Effects 0.000 description 4
- 230000004075 alteration Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
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- 238000003475 lamination Methods 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 230000002035 prolonged effect Effects 0.000 description 1
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H01L2924/1434—Memory
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- H01L2924/1438—Flash memory
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Abstract
The invention provides a method for forming a flash memory side wall, which comprises the steps of etching for three times to form a second side wall of a flash memory device; the height of the formed second side wall is smaller than that of the second side wall formed in the prior art. The height of the second side wall is reduced, so that the height difference between the top of the flash memory word line and the second side wall is increased, and the height difference between the top of the flash memory word line and the second side wall reaches the process standard. Meanwhile, compared with the prior art, an etching step is added, so that the time for excessively etching the second dielectric layer in the method is basically consistent with the time for excessively etching the second dielectric layer in the prior art, the problem that the subsequently formed semiconductor structure is abnormal due to the fact that the reaction cavity is polluted by the increase of the excessive etching time is solved, and the performance of the device is improved.
Description
Technical Field
The invention relates to the field of semiconductor manufacturing, in particular to a method for forming a flash memory side wall.
Background
In existing integrated circuits, a memory device has become an important device. Among the current Memory devices, Flash Memory (Flash Memory) is developed particularly rapidly. The main characteristic of flash memory is that it can keep the stored information for a long time without power-up; and has the advantages of high integration level, high access speed, easy erasing and rewriting, and the like, thereby being widely applied to the fields of microcomputer, automatic control, and the like.
Each portion in a flash memory device has a corresponding size requirement. The height difference between the offset sidewall of the flash memory and the top of the word line of the flash memory is an important factor affecting the overall performance of the flash memory device, and the height difference needs to be within a proper range. If the width of a process window in the word line chemical mechanical polishing process is smaller than the standard width, and the distance between the top of the word line and the offset side wall is closer, the height difference between the offset side wall and the top of the flash memory word line is smaller than the standard value of the height difference between the offset side wall and the top of the flash memory word line, so that the offset side wall is exposed in the subsequent device manufacturing process, and finally the step of removing the mask layer of the offset side wall on the floating gate is etched to damage the device structure. If the width of the process window in the word line chemical mechanical polishing process is larger than the standard width, the distance between the top of the word line and the offset side wall is increased, so that the height difference between the offset side wall and the top surface of the flash memory word line is increased, and the height difference between the offset side wall and the top surface of the flash memory word line reaches the standard value, but the process window in the word line chemical mechanical polishing process is increased, and the word line can leave residues on the surface of the mask layer on the floating gate after the chemical mechanical polishing process, so that the subsequent removal of the mask layer on the floating gate is. Therefore, it is not desirable to increase the width of the process window during the word line cmp process to make the height difference between the offset sidewall and the top surface of the flash memory word line meet the process standard.
Disclosure of Invention
The invention aims to provide a method for forming a flash memory side wall, which aims to solve the problem that the height difference between a flash memory offset side wall formed in the existing method and the top of a flash memory word line does not accord with the manufacturing process standard of a semiconductor device.
In order to achieve the above object, the present invention provides a method for forming a flash memory sidewall, comprising the following steps:
providing a substrate, wherein a first gate layer, a dielectric layer, a second gate layer and a mask layer are sequentially formed on the substrate; a first opening is formed in the mask layer, the surface of the second gate layer is exposed out of the first opening, and a first side wall is formed on the side wall of the first opening;
etching the second gate layer and the dielectric layer by taking the first side walls as masks to form second openings;
and sequentially forming a first dielectric layer and a second dielectric layer on the bottom and the side wall of the second opening and the surface of the mask layer.
Etching the second dielectric layer for the first time; the first etching exposes the first dielectric layer on the surface of the mask layer and the first dielectric layer on the bottom surface of the second opening;
performing second etching on the second dielectric layer; the selectivity of the second dielectric layer during the second etching is greater than that of the first dielectric layer during the first etching; and
performing third etching on the second dielectric layer to form a second side wall on the surface of the first dielectric layer; and during the third etching, the selectivity of the second dielectric layer is greater than that of the second dielectric layer during the second etching.
Optionally, the thickness of the first dielectric layer ranges from 94 angstroms to 115 angstroms.
Optionally, the thickness range of the second dielectric layer is 270 to 330 angstroms.
Optionally, during the second etching, the etching selection ratio range of the second dielectric layer to the first dielectric layer is 3-4.
Optionally, during the third etching, the etching selection ratio of the second dielectric layer to the first dielectric layer ranges from 8 to 9.
Optionally, the second etching and the third etching are performed in a manner of stopping etching by reaching time.
Optionally, the time range of the second etching is 25-35 seconds.
Optionally, the time range of the third etching is 20-30 seconds.
Optionally, during the first etching, the etching selection ratio of the second dielectric layer to the first dielectric layer is in a range of 1.5-2.0.
Optionally, the first etching is performed by stopping etching when reaching an end point.
Optionally, the thickness range of the first etching is 270-330 angstroms.
Optionally, the first etching and the second etching use a mixed gas of carbon tetrafluoride gas and trifluoromethane gas.
Optionally, during the first etching, the content ratio of the carbon tetrafluoride gas to the trifluoromethane gas ranges from 2.5 to 3.5.
Optionally, during the second etching, the content ratio of the carbon tetrafluoride gas to the trifluoromethane gas ranges from 0.25 to 0.75.
Optionally, the third etching uses trifluoromethane gas.
Optionally, the first dielectric layer is an oxide layer, the second dielectric layer is a silicon nitride layer, the mask layer is a silicon nitride layer, and the dielectric layer is an ONO layer.
Optionally, after the step of etching the second gate layer and the dielectric layer to form the second opening with the first sidewall as a mask, the dielectric layer is left with a residue.
In summary, in the method for forming the flash memory sidewall spacer provided by the present invention, a substrate is provided, and a first gate layer, a dielectric layer, a second gate layer and a mask layer are sequentially formed on the substrate; a first opening is formed in the mask layer, the surface of the second gate layer is exposed out of the first opening, and a first side wall is formed on the side wall of the first opening; etching the second gate layer and the dielectric layer by taking the first side walls as masks to form second openings; and sequentially forming a first dielectric layer and a second dielectric layer on the bottom and the side wall of the second opening and the surface of the mask layer. And etching the second dielectric layer for three times to finally form a second side wall. And the selectivity of the second dielectric layer during the second etching is greater than that of the first dielectric layer during the first etching, and the selectivity of the second dielectric layer during the third etching is greater than that of the second dielectric layer during the second etching. The method provided by the invention comprises the steps of etching for three times to form a second side wall of the flash memory device; the height of the finally formed second side wall is smaller than that of the second side wall formed in the prior art. The height of the second side wall is reduced, so that the height difference between the top of the flash memory word line and the second side wall is increased, and the height difference between the top of the flash memory word line and the second side wall reaches the process standard. Meanwhile, compared with the prior art, an etching step is added, so that the time for excessively etching the second dielectric layer in the method is basically consistent with the time for excessively etching the second dielectric layer in the prior art, the problem that the formed semiconductor structure is abnormal due to the pollution of a reaction cavity caused by the increase of the excessive etching time is avoided, and the performance of the device is improved.
Drawings
FIG. 1 is a schematic diagram of a front-end structure after forming a floating gate sidewall;
FIG. 2 is a schematic diagram of the front end structure after forming the second sidewall opening;
FIG. 3 is a schematic diagram of a front-end structure after sequentially forming a first dielectric layer and a second dielectric layer;
fig. 4 is a flowchart of a method for forming a flash memory sidewall according to an embodiment of the present invention;
fig. 5 is a schematic view of a semiconductor structure after forming a first sidewall spacer according to an embodiment of the present invention;
FIG. 6 is a schematic view of a semiconductor structure after forming a second opening according to an embodiment of the present invention;
FIG. 7 is a schematic diagram of a semiconductor structure after sequentially forming a first dielectric layer and a second dielectric layer in accordance with an embodiment of the present invention;
FIG. 8 is a schematic view of a semiconductor structure formed after a first etching in accordance with an embodiment of the present invention;
FIG. 9 is a schematic view of a semiconductor structure formed after a second etching in accordance with an embodiment of the present invention;
FIG. 10 is a schematic view of a semiconductor structure formed after a third etching according to an embodiment of the present invention;
the semiconductor device comprises a substrate 10, a first gate layer 11, a dielectric layer 12, a second gate layer 13, a mask layer 14, a floating gate side wall 15, a first side wall opening 16, a second side wall opening 17, a first dielectric layer 18, a second dielectric layer 19, a substrate 20, a first gate layer 21, a dielectric layer 22, a second gate layer 23, a mask layer 24, a first side wall 25, a first opening 26, a second opening 27, a first dielectric layer 28 and a second dielectric layer 29.
Detailed Description
The following describes in more detail embodiments of the present invention with reference to the schematic drawings. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
In the description that follows, it will be understood that when a layer (or film), region, pattern, or structure is referred to as being "on" a substrate, layer (or film), region, and/or pattern, it can be directly on another layer or substrate, and/or intervening layers may also be present. In addition, it will be understood that when a layer is referred to as being "under" another layer, it can be directly under the other layer, and/or one or more intervening layers may also be present. In addition, references to "on" and "under" layers may be made based on the drawings.
As described in the background art, when forming a flash memory device, the height difference between the offset sidewall of the flash memory and the top of the word line of the flash memory is an important factor affecting the overall performance of the flash memory device, and therefore, the height difference between the offset sidewall of the flash memory and the top of the word line of the flash memory needs to be within a proper range.
Because the height difference between the offset side wall and the top surface of the flash memory word line reaches the process standard by increasing the width of the process window in the word line chemical mechanical polishing process, residue is left on the surface of the mask layer on the floating gate after the word line chemical mechanical polishing process, and the subsequent removal of the mask layer on the floating gate is blocked.
Therefore, the inventor finds a method for reducing the height of the offset side wall to enable the height difference between the offset side wall and the top surface of the flash memory word line to reach the process standard and improve the performance of the flash memory device.
Specifically, referring to fig. 1, the structure shown in fig. 1 is a front-end semiconductor structure before forming offset spacers. As shown in fig. 1, the front-end structure includes a substrate 10, a first gate layer 11 on the substrate 10, a dielectric layer 12 on the first gate layer 11, a second gate layer 13 on the dielectric layer 12, and a mask layer 14 on the second gate layer 13. Furthermore, a first sidewall opening 16 is formed in the mask layer 14, a portion of the surface of the second gate layer 13 is exposed at the bottom of the first sidewall opening 16, and a floating gate sidewall 15 is formed on a sidewall of the first sidewall opening 16.
Further, referring to fig. 2, the second gate layer 13 and the dielectric layer 12 are etched using the floating gate spacers 15 as a mask to form second sidewall openings 17. Referring to fig. 3, a first dielectric layer 18 is formed on the bottom and sidewalls of the second sidewall opening 17 and the surface of the mask layer 14, and then a second dielectric layer 19 is formed on the surface of the first dielectric layer 18.
Specifically, in one embodiment, the thickness of the first dielectric layer 18 is in a range of 65 to 79 angstroms, and may be 68 angstroms, 72 angstroms or 74 angstroms; the thickness of the second dielectric layer 19 is 270-330 angstroms, which may be 290 angstroms, 300 angstroms or 310 angstroms.
Furthermore, when the offset side wall is formed, the etching is finished in two steps, wherein the two steps comprise main etching and over etching, and the second dielectric layer and the first dielectric layer adopt high etching selection ratio in the over etching. The inventor increases the etching amount of the first dielectric layer and the second dielectric layer by keeping the main etching step unchanged and increasing the over-etching time, so that the height of the finally formed offset side wall is reduced compared with the previous height, and the height difference between the offset side wall and the top of the word line can reach the process standard subsequently. However, the etching selectivity of the second dielectric layer and the first dielectric layer in the over-etching step is much higher than that of the second dielectric layer and the second dielectric layer in the first etching, and the polymer content in the etchant mainly used in the over-etching is relatively heavy, which easily causes the cavity contamination. Therefore, after the excessive etching time is prolonged, the semiconductor reaction cavity is polluted, the reaction condition in the cavity is influenced, and the subsequently formed semiconductor structure is abnormal and does not reach the process standard; for example, the surface of the floating gate sidewall is rough and the critical dimension of the mask layer is increased. Meanwhile, after the over-etching time is increased, the first gate layer at the bottom of the second sidewall opening may be damaged, so that a blunt end is formed at a contact end of the first gate layer and the offset sidewall, and the formation of the structure may affect the erasing performance of a subsequent floating gate, and finally, the performance of the flash memory device.
Therefore, in order to solve the above problems in manufacturing a semiconductor device, the present invention provides a method for forming a flash sidewall.
Referring to fig. 4, which is a schematic flow chart of a method for forming a flash memory sidewall provided in an embodiment of the present invention, as shown in fig. 4, the method for forming a flash memory sidewall includes the following steps:
step S1: providing a substrate, wherein a first gate layer, a dielectric layer, a second gate layer and a mask layer are sequentially formed on the substrate; a first opening is formed in the mask layer, the surface of the second gate layer is exposed out of the first opening, and a first side wall is formed on the side wall of the first opening;
step S2: etching the second gate layer and the dielectric layer by taking the first side walls as masks to form second openings;
step S3: and sequentially forming a first dielectric layer and a second dielectric layer on the bottom and the side wall of the second opening and the surface of the mask layer.
Step S4: etching the second dielectric layer for the first time; the first etching exposes the first dielectric layer on the surface of the mask layer and the first dielectric layer on the bottom surface of the second opening;
step S5: performing second etching on the second dielectric layer; the selectivity of the second dielectric layer during the second etching is greater than that of the first dielectric layer during the first etching; and
step S6: performing third etching on the second dielectric layer to form a second side wall on the surface of the first dielectric layer; and during the third etching, the selectivity of the second dielectric layer is greater than that of the second dielectric layer during the second etching.
Specifically, referring to fig. 5 to 7, a semiconductor structure is formed before forming the second sidewall. Further, referring to fig. 5, the process of forming the semiconductor structure includes step S1: a substrate 20 is provided, and a first gate layer 21, a dielectric layer 22, a second gate layer 23 and a mask layer 24 are sequentially formed on the substrate 20. A first opening 26 is formed in the mask layer 24, a part of the surface of the second gate layer 23 is exposed at the bottom of the first opening 26, and a first sidewall 25 is formed on a sidewall of the first opening 26, where it should be noted that the first sidewall 25 is a floating gate sidewall.
Further, referring to fig. 6, the process of forming the semiconductor structure further includes step S2; and etching the second gate layer 23 and the dielectric layer 22 by using the first sidewall 25 as a mask, and reserving a part of the dielectric layer 22 to form a second opening 27. Specifically, the dielectric layer 22 is an ONO stack, and the part of the dielectric layer 22 that remains is an oxide layer that remains the bottom of the ONO stack and is used to protect the first gate layer 21.
Still further, referring to fig. 7, the process of forming the semiconductor structure further includes step S3, forming a first dielectric layer 28 and a second dielectric layer 29 on the bottom and the sidewall of the second opening 27 and the surface of the masking layer 24 in sequence.
Specifically, in one embodiment, the thickness of the first dielectric layer 28 is increased, and the thickness of the first dielectric layer 28 ranges from 94 to 115 angstroms, and may be 98 angstroms, 104 angstroms or 110 angstroms; the thickness range of the second dielectric layer 29 is 270-330 angstroms, and can be 290 angstroms, 300 angstroms or 310 angstroms. The first dielectric layer 28 is an oxide layer, the second dielectric layer 29 is a silicon nitride layer, the mask layer 24 is a silicon nitride layer, the second gate layer 23 is a control gate, the dielectric layer 22 is an ONO stack, and the first gate layer 21 is a floating gate. The thickness of the ONO lamination layer ranges from 140 to 160 angstroms, and after the second opening 27 is formed, the thickness of the rest oxide layer ranges from 15 to 30 angstroms. And may be 16 angstroms, 20 angstroms or 25 angstroms.
Further, step S4 to step S6 are performed to finally form a second sidewall, where it should be noted that the second sidewall is an offset sidewall.
First, in step S4, the second dielectric layer 29 is etched for the first time, specifically, the first etching is performed in a manner of stopping etching when reaching the end point. Further, the thickness range of the first etching is 270-330 angstroms, and carbon tetrafluoride (CF) is mainly used4) Gas and trifluoromethane (CHF)3) And etching by using gas. Specifically, the carbon tetrafluoride (CF) is introduced into the reaction cavity separately4) Gas and trifluoromethane (CHF)3) A gas. Wherein, in the reaction chamber, the carbon tetrafluoride (CF)4) Gas and trifluoromethane (CHF)3) The ratio of the content of the gas is higher; specifically, carbon tetrafluoride (CF)4) Gas and trifluoromethane (CHF)3) The ratio of the gas contents is in the range of 2.5 to 3.5. Furthermore, during the first etching, the etching selection ratio of the second dielectric layer 29 to the first dielectric layer 28 is in the range of 1.5-2.0. Referring to fig. 8, after the first etching, the first dielectric layer 28 on the surface of the masking layer 24 and the first dielectric layer 2 on the bottom surface of the second opening 27 are exposed8。
Further, since the thickness of first dielectric layer 28 is increased in this embodiment, after second dielectric layer 29 on the surface of first dielectric layer 28 on masking layer 24 is etched, first dielectric layer 28 protects masking layer 24 from being etched, so that the step of over-etching is not performed urgently. Preferably, step S5 is performed to perform a second etching on the second dielectric layer 29, specifically, the second etching is performed by stopping the etching at the reaching time. Further, the time range of the second etching is 25-35 seconds, and carbon tetrafluoride (CF) is mainly used4) Gas and trifluoromethane (CHF)3) And etching by using gas. Specifically, the carbon tetrafluoride (CF) is introduced into the reaction cavity separately4) Gas and trifluoromethane (CHF)3) A gas. Wherein, in the reaction chamber, the carbon tetrafluoride (CF)4) Gas and trifluoromethane (CHF)3) The content ratio of the gas is low; specifically, carbon tetrafluoride (CF)4) Gas and trifluoromethane (CHF)3) The ratio of the gas contents is in the range of 0.25 to 0.75. Furthermore, during the second etching, the etching selection ratio of the second dielectric layer 29 to the first dielectric layer 28 is in the range of 3-4. Specifically, referring to fig. 9, a schematic view of the semiconductor structure formed after the second etching is shown.
And finally, performing step S6 to perform a third etching on the second dielectric layer 29, specifically, the third etching is performed by stopping the etching at the time of arrival. Further, the third etching time is 20-30 seconds, and trifluoromethane (CHF) is mainly used3) And etching by using gas. Furthermore, during the third etching, the etching selection ratio of the second dielectric layer 29 to the first dielectric layer 28 ranges from 8 to 9. Specifically, referring to fig. 10, the schematic view of the semiconductor structure formed after the third etching is shown, the second dielectric layer 29 is tightly attached to the surface of the first dielectric layer, and the remaining second dielectric layer 29 in fig. 10 is the second sidewall spacer finally formed.
Furthermore, the difference between the time of the third etching and the time of the transitional etching in the prior art is not large, and the height of the formed second side wall is smaller than that of the second side wall formed in the prior art. And after the third etching in the method, the environment of the reaction cavity is not greatly influenced, and the formed semiconductor structure reaches the process standard. Meanwhile, the phenomenon that a blunt end is formed at the contact end of the first gate layer and the offset side wall due to the fact that the first gate layer is etched, the erasing function of a subsequent flash memory is affected is avoided, and the performance of the device is improved.
In summary, in the method for manufacturing a flash memory according to the present invention, a substrate is provided, and a first gate layer, a dielectric layer, a second gate layer and a mask layer are sequentially formed on the substrate; a first opening is formed in the mask layer, the surface of the second gate layer is exposed out of the first opening, and a first side wall is formed on the side wall of the first opening; etching the second gate layer and the dielectric layer by taking the first side walls as masks to form second openings; and sequentially forming a first dielectric layer and a second dielectric layer on the bottom and the side wall of the second opening and the surface of the mask layer. And etching the second dielectric layer for three times to finally form a second side wall. And the selectivity of the second dielectric layer during the second etching is greater than that of the first dielectric layer during the first etching, and the selectivity of the second dielectric layer during the third etching is greater than that of the second dielectric layer during the second etching. The method provided by the invention comprises the steps of etching for three times to form a second side wall of the flash memory device; the height of the finally formed second side wall is smaller than that of the second side wall formed in the prior art. The height of the second side wall is reduced, so that the height difference between the top of the flash memory word line and the second side wall is increased, and the process standard is reached. Meanwhile, compared with the prior art, an etching step is added, so that the over-etching time of the second dielectric layer in the method is basically consistent with the over-etching time of the second dielectric layer in the prior art, and the finally formed semiconductor structure reaches the process standard.
Furthermore, by increasing the thickness of the first dielectric layer, after the second dielectric layer is etched, the surface of the mask layer is protected from being etched by the first dielectric layer, and the etching of the second dielectric layer and the first dielectric layer is not urgent to select a high etching selection ratio. Therefore, the over-etching time is reduced, the over-etching time of the second dielectric layer in the method is basically consistent with the over-etching time of the second dielectric layer in the prior art, the problem that after the over-etching time is increased, a semiconductor reaction cavity is polluted to influence reaction conditions, so that the subsequently formed semiconductor structure is abnormal, and the first gate layer at the bottom of the second side wall opening is lost to form a blunt end at the contact end of the first gate layer and the second side wall is solved, and the performance of a flash memory device is improved.
The above description is only a preferred embodiment of the present invention, and does not limit the present invention in any way. It will be understood by those skilled in the art that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (17)
1. A method for forming a flash memory side wall is characterized by comprising the following steps:
providing a substrate, wherein a first gate layer, a dielectric layer, a second gate layer and a mask layer are sequentially formed on the substrate; a first opening is formed in the mask layer, the surface of the second gate layer is exposed out of the first opening, and a first side wall is formed on the side wall of the first opening;
etching the second gate layer and the dielectric layer by taking the first side walls as masks to form second openings;
sequentially forming a first dielectric layer and a second dielectric layer on the bottom and the side wall of the second opening and the surface of the mask layer;
etching the second dielectric layer for the first time; the first etching exposes the first dielectric layer on the surface of the mask layer and the first dielectric layer on the bottom surface of the second opening;
performing second etching on the second dielectric layer; the second etching is used for thinning the exposed part of the first dielectric layer, and the top height of the second dielectric layer is reduced; during the second etching, the selectivity of the second dielectric layer relative to the first dielectric layer is greater than that during the first etching; and
carrying out third etching on the second dielectric layer; the third etching exposes the surface of the mask layer and part of the surface of the first side wall, the first dielectric layer on the bottom surface of the second opening is further thinned, and the top height of the second dielectric layer is further reduced, so that a second side wall is formed on the surface of the first dielectric layer; and during the third etching, the selectivity of the second dielectric layer relative to the first dielectric layer is greater than that during the second etching.
2. The method for forming the sidewall spacer of the flash memory according to claim 1, wherein the thickness of the first dielectric layer is 94-115 angstroms.
3. The method for forming the flash memory sidewall spacer as claimed in claim 1, wherein the thickness of the second dielectric layer is 270 to 330 angstroms.
4. The method for forming the flash memory sidewall spacer according to claim 1, wherein during the second etching, the etching selection ratio range of the second dielectric layer to the first dielectric layer is 3-4.
5. The method for forming the flash memory sidewall spacer according to claim 1, wherein during the third etching, an etching selection ratio range of the second dielectric layer to the first dielectric layer is 8-9.
6. The method for forming the flash memory sidewall as claimed in claim 1, wherein the second etching and the third etching are performed by stopping the etching at the time of arrival.
7. The method for forming the flash memory sidewall spacer of claim 6, wherein the time of the second etching is in a range of 25 to 35 seconds.
8. The method for forming the flash memory sidewall spacer as claimed in claim 6, wherein the time of the third etching is 20-30 seconds.
9. The method for forming the flash memory sidewall spacer according to claim 1, wherein during the first etching, an etching selection ratio of the second dielectric layer to the first dielectric layer is in a range of 1.5 to 2.0.
10. The method for forming the flash memory sidewall as claimed in claim 1, wherein the first etching is performed by stopping the etching when reaching an end point.
11. The method for forming the flash memory sidewall spacer of claim 10, wherein the thickness of the first etching is 270 to 330 angstroms.
12. The method for forming the flash memory sidewall as claimed in claim 1, wherein the first etching and the second etching use a mixture of carbon tetrafluoride gas and trifluoromethane gas.
13. The method for forming the flash memory sidewall as claimed in claim 12, wherein a ratio of the carbon tetrafluoride gas to the trifluoromethane gas during the first etching is in a range of 2.5 to 3.5.
14. The method for forming the flash memory sidewall as claimed in claim 12, wherein a ratio of the carbon tetrafluoride gas to the trifluoromethane gas during the second etching is in a range of 0.25 to 0.75.
15. The method for forming the flash memory sidewall as claimed in claim 1, wherein the third etching uses trifluoromethane gas.
16. The method for forming the sidewall spacer of the flash memory according to claim 1, wherein the first dielectric layer is an oxide layer, the second dielectric layer is a silicon nitride layer, the mask layer is a silicon nitride layer, and the dielectric layer is an ONO layer.
17. The method for forming the sidewall spacer of the flash memory according to claim 1, wherein the dielectric layer is left after the step of etching the second gate layer and the dielectric layer to form the second opening by using the first sidewall spacer as a mask.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US6635533B1 (en) * | 2003-03-27 | 2003-10-21 | Powerchip Semiconductor Corp. | Method of fabricating flash memory |
| CN103413786A (en) * | 2013-08-22 | 2013-11-27 | 上海宏力半导体制造有限公司 | Storage unit, forming method of storage unit and driving method of storage unit |
| CN103426826A (en) * | 2013-08-22 | 2013-12-04 | 上海宏力半导体制造有限公司 | Flash memory unit and formation method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6635533B1 (en) * | 2003-03-27 | 2003-10-21 | Powerchip Semiconductor Corp. | Method of fabricating flash memory |
| CN103413786A (en) * | 2013-08-22 | 2013-11-27 | 上海宏力半导体制造有限公司 | Storage unit, forming method of storage unit and driving method of storage unit |
| CN103426826A (en) * | 2013-08-22 | 2013-12-04 | 上海宏力半导体制造有限公司 | Flash memory unit and formation method thereof |
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