CN110911346A - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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- CN110911346A CN110911346A CN201911243526.1A CN201911243526A CN110911346A CN 110911346 A CN110911346 A CN 110911346A CN 201911243526 A CN201911243526 A CN 201911243526A CN 110911346 A CN110911346 A CN 110911346A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
- H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
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Abstract
The invention provides a semiconductor structure and a forming method thereof. By forming the mask layer to cover the isolation oxide layer and defining at least part of the pattern of the first semiconductor device, and the mask layer at least comprises the first mask layer with a material different from that of the isolation oxide layer, on the basis of the above, at least when the first mask layer of the mask layer is removed, the etching rate of the etchant to the isolation oxide layer can be ensured to be low, and the problem that the isolation oxide layer is greatly consumed is avoided. Therefore, the isolation performance of the isolation oxide layer can be guaranteed, and the overall performance of the formed semiconductor structure can be improved.
Description
Technical Field
The present invention relates to the field of semiconductor technology, and more particularly, to a semiconductor structure and a method for forming the same.
Background
With the continuous development of semiconductor technology, the integration level of semiconductor devices is also higher and higher, and thus the semiconductor devices are more widely applied to actual life. In order to reduce the influence between devices, isolation between different devices may be generally achieved by using an isolation oxide layer. However, after the isolation oxide layer is formed, and the semiconductor device is continuously manufactured on the outer side of the isolation oxide layer, the isolation oxide layer is often damaged.
Referring specifically to fig. 1 a-1 c, a method of forming a semiconductor structure includes, for example, the following steps.
In a first step, referring to fig. 1a in particular, a substrate 10 is provided, an isolation oxide layer 20 is formed on the substrate 10, and a second semiconductor device 50 may be further formed on the isolation oxide layer 20.
A second step, continuing to refer to fig. 1a, forming a mask layer 30 on the substrate 10, wherein the mask layer 30 covers the isolation oxide layer 20, and a mask pattern (e.g., including a plurality of openings) is further formed in a region of the mask layer 30 outside the isolation oxide layer 20, and copying the mask pattern into the substrate 10 for forming a first semiconductor device on the substrate outside the isolation oxide layer.
It should be noted that, when the mask pattern is copied into the substrate 10, in order to ensure a large etching selection ratio between the mask layer and the substrate 10, the mask layer 30 is usually formed by using an oxide material, which is beneficial to improve the pattern accuracy of the mask pattern copied into the substrate 10. And, in order to avoid the depletion of the mask layer 30 during the pattern transfer, it is generally necessary to make the mask layer 30 have a large thickness (for example, to make the thickness of the mask layer 30 equal to or greater than 6000 angstroms).
A third step, shown in fig. 1b in particular, is to perform an etching process to remove the mask layer 30.
As mentioned above, the material of the mask layer 30 is usually an oxide material, and therefore, when the mask layer 30 is removed, the isolation oxide layer 20 is exposed, and a large loss of the isolation oxide layer 20 is caused. In particular, since the mask layer 30 has a large thickness, in order to avoid the problem of mask material residue, a large Over-etching amount (Over Etch) is required to remove the mask layer 30, which may result in a large consumption of the isolation oxide layer 20.
In addition, as shown in fig. 1b, a second semiconductor device 50 is usually formed on the isolation oxide layer 20, and when an etching process is performed to remove the mask layer 30, a portion of the isolation oxide layer 20 exposed from the second semiconductor device 50 is eroded due to an etching barrier of the second semiconductor device 50, so that a larger step structure is formed at a sidewall position of the second semiconductor device 50.
Referring to fig. 1c, when the conductive layer 40 is formed subsequently to further manufacture the first semiconductor device, due to the presence of the step structure, the conductive material of the conductive layer 40 often remains on the sidewall of the second semiconductor device 50 (specifically, refer to the dashed line box in fig. 1 c), which may adversely affect the performance of the second semiconductor device 50.
Disclosure of Invention
The invention aims to provide a method for forming a semiconductor structure, which aims to solve the problem that the existing forming method is easy to cause that an isolation oxide layer is greatly consumed, so that the isolation performance of the isolation oxide layer is reduced, and the performance of a semiconductor device is further influenced.
To solve the above technical problem, the present invention provides a method for forming a semiconductor structure, including:
providing a substrate, wherein an isolation oxide layer is formed on the substrate, and a second semiconductor device is formed on the isolation oxide layer;
forming a mask layer on the substrate, wherein the mask layer at least comprises a first mask layer with a material different from that of the isolation oxide layer, the mask layer covers the isolation oxide layer and the second semiconductor device, and a mask pattern is further formed in a region, located outside the isolation oxide layer, in the mask layer;
copying the mask pattern into the substrate for forming a first semiconductor device on the substrate outside the isolation oxide layer; and the number of the first and second groups,
and removing the mask layer.
Optionally, before forming the mask layer, forming a liner oxide layer on the top surface of the substrate; and when the mask layer is formed, the mask layer covers the lining oxide layer.
Optionally, the material of the first mask layer includes silicon nitride.
Optionally, an etching process is performed to remove the first mask layer, and an etchant of the etching process includes phosphoric acid.
Optionally, the mask layer is at least two stacked structures, and the first mask layer is a bottom layer of the stacked structures, so that the first mask layer directly covers the isolation oxide layer; and the laminated structure further comprises a second mask layer, wherein the material of the second mask layer is different from that of the first mask layer.
Optionally, the method for removing the mask layer includes:
executing a first etching process to remove the second mask layer and etch and stop on the first mask layer; and the number of the first and second groups,
and executing a second etching process to remove the first mask layer.
Optionally, the material of the second mask layer includes silicon oxide. Further, the thickness of the second mask layer is larger than that of the first mask layer.
Optionally, the mask pattern of the mask layer includes at least one opening; and, copying the mask pattern into the substrate comprises: at least one trench is formed in the substrate.
Optionally, the second semiconductor device is a temperature sensor, and the first semiconductor device is a trench gate field effect transistor.
In addition, the present invention also provides a semiconductor structure prepared by the formation method as described above, the semiconductor structure including:
a substrate;
an isolation oxide layer formed on the substrate;
a second semiconductor device formed on the isolation oxide layer; and the number of the first and second groups,
and the first semiconductor device is formed on the substrate outside the isolation oxide layer.
In the method for forming the semiconductor structure, the isolation oxide layer is formed, the second semiconductor device is formed on the isolation oxide layer, and the first semiconductor device is formed on the outer side of the isolation oxide layer, so that the first semiconductor device and the second semiconductor device can be electrically isolated by using the isolation oxide layer. The method comprises the steps of preparing a first semiconductor device on the outer side of an isolation oxide layer, wherein when the first semiconductor device is prepared on the outer side of the isolation oxide layer, a mask layer can be used for covering the isolation oxide layer and a second semiconductor device, at least part of patterns of the first semiconductor device are defined, and because the mask layer at least comprises a first mask layer with a material different from that of the isolation oxide layer, on the basis, when the first mask layer of the mask layer is removed, an etchant can be ensured to have a low etching rate on the isolation oxide layer, the problem that the isolation oxide layer is consumed in a large amount is avoided, and therefore a large step structure can be correspondingly prevented from being formed on the side wall of the.
Furthermore, because a larger step structure is not formed at the side wall position of the second semiconductor device, for example, when the first conductive layer of the first semiconductor device is continuously formed at this time, the conductive material of the first conductive layer can be effectively prevented from remaining at the side wall position of the second semiconductor device, so that the device performance of the second semiconductor device can be effectively guaranteed.
Drawings
FIGS. 1a to 1c are schematic structural diagrams of a conventional semiconductor structure during a manufacturing process thereof;
FIG. 2 is a flow chart illustrating a method of forming a semiconductor structure according to an embodiment of the present invention;
fig. 3a to fig. 3e are schematic structural diagrams of a semiconductor structure in a manufacturing process according to an embodiment of the invention.
Wherein the reference numbers are as follows:
10-a substrate;
20-isolating oxide layer;
30-a mask layer;
40-a conductive layer;
50-a second semiconductor device;
100-a substrate;
200-an isolation oxide layer;
300-a mask layer;
310 — a first mask layer;
320-a second mask layer;
410-a trench;
420-a gate oxide layer;
430-a first conductive layer;
510-a first liner oxide layer;
520-a second liner oxide layer;
600-a second semiconductor device.
Detailed Description
The method for forming the semiconductor structure according to the present invention is described in further detail with reference to the accompanying drawings and the embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is provided solely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
Fig. 2 is a schematic flow chart of a method for forming a semiconductor structure according to an embodiment of the invention, and fig. 3a to 3e are schematic structural diagrams of the semiconductor structure according to an embodiment of the invention during a manufacturing process thereof. The steps in this embodiment will be described in detail below with reference to the drawings.
In step S100, referring specifically to fig. 3a, a substrate 100 is provided, and an isolation oxide layer 200 is formed on the substrate 100. In particular, the isolation oxide layer 200 may be used to isolate different devices integrated on the same substrate 100 from each other.
The isolation oxide layer 200 may be formed by a local oxidation of Silicon (LOCOS) process, for example.
In a further scheme, a second semiconductor device 600 may be further formed on the isolation oxide layer 200, and at this time, the second semiconductor device 600 may be integrated with other semiconductor devices on the same substrate 100 through the isolation oxide layer 200 without mutual influence.
In this embodiment, the second semiconductor device 600 includes a second conductive layer formed on the isolation oxide layer 200. And the width of the second conductive layer is smaller than the width of the isolation oxide layer 200, so as to ensure that the isolation oxide layer 200 has a better isolation performance for the second conductive layer, and at this time, the isolation oxide layer 200 has a portion exposed from the second conductive layer correspondingly.
The second semiconductor device 600 is, for example, a temperature sensor, and a thermistor can be formed by the second conductive layer. Optionally, the material of the second conductive layer includes, for example, polysilicon.
In step S200, with continued reference to fig. 3a, a mask layer 300 is formed on the substrate 100, the mask layer 300 covers the isolation oxide layer 200, and a mask pattern is further formed in a region of the mask layer 300 outside the isolation oxide layer.
In this embodiment, the mask layer 300 further covers the second semiconductor device 600 (specifically, the mask layer 300 covers the second conductive layer of the second semiconductor device and covers the isolation oxide layer 200 exposed from the second conductive layer), so as to avoid etching damage to the second semiconductor device 600 and the isolation oxide layer 200 when the substrate 100 is etched in the following process.
In an alternative scheme, before forming the mask layer 300, the method further includes: a liner oxide layer is formed on the substrate 100. In this embodiment, the liner oxide layer formed on the top surface of the substrate 100 is the first liner oxide layer 510.
It should be noted that, since the mask layer 300 generally has a large internal stress relative to the substrate 100, if the mask layer 300 is directly covered on the substrate 100, the stress in the mask layer 300 acts on the substrate 100, so that the substrate 100 is easily deformed, and the patterning precision of the substrate 100 is further affected.
Specifically, the liner oxide layer (including the first liner oxide layer 510) may be formed, for example, by a thermal oxidation process, so that the first liner oxide layer 510 can be formed on the top surface of the substrate 100 in a self-aligned manner.
In addition, in this embodiment, the material of the second conductive layer of the second semiconductor device 600 includes polysilicon, and accordingly, when the thermal oxidation process is performed, a liner oxide layer is also formed on the exposed surface of the second conductive layer (as shown in fig. 3a, the liner oxide layer formed on the second conductive layer is the second liner oxide layer 520). Furthermore, when the mask layer 300 is formed subsequently, the mask layer 300 correspondingly covers the second conductive layer by spacing the second liner oxide layer 520, so that the stress applied to the second semiconductor device 600 by the mask layer 300 can also be relieved, and the performance of the second semiconductor device 600 is prevented from being affected.
Wherein the thickness of the liner oxide layer (including the first liner oxide layer 510 and the second liner oxide layer 520) is much smaller than the thickness of the mask layer 300. For example, the liner oxide layer has a thickness of not more than
And the thickness of the liner oxide layer may be further in-between
Based on this, when the liner oxide layer is removed subsequently, the liner oxide layer can be completely removed only by a trace amount of over-etching, and a large amount of loss of the isolation oxide layer 200 is not caused at this time.
With continued reference to fig. 3a, the mask layer 300 includes at least a first mask layer 310 of a material different from the isolation oxide layer 200. Since the material of the first mask layer 310 in the mask layer 300 is different from the material of the isolation oxide layer 200, during the etching process for removing the first mask layer 310, i.e. correspondingly, the first mask layer 310 and the isolation oxide layer 200 have a larger etching selectivity ratio, the problem that the isolation oxide layer 200 is greatly eroded by the etchant is avoided. Specifically, the material of the first mask layer 310 includes, for example, silicon nitride (SiN).
As described above, a mask pattern is also formed in the mask layer 300 in the region outside the isolation oxide layer. It is understood that the mask pattern in the mask layer 300 is, for example, at least a portion of a pattern for defining the first semiconductor device. As shown in fig. 3a, the mask pattern in this embodiment includes at least one opening (two openings are schematically shown in fig. 3 a).
Further, the mask layer 300 further includes a second mask layer 320, and the second mask layer 320 has a larger etching selectivity with respect to the substrate 100. That is, when the substrate 100 is etched using the mask layer 300 as a mask, a patterning process may be implemented mainly using the second mask layer 320 as a mask.
In a specific embodiment, the material of the second mask layer 320 includes silicon oxide, for example. And, the second mask layer 320 may be further formed of silicon oxide based on TEOS precursors in combination with a chemical vapor deposition process.
It should be noted that, in order to ensure that the mask pattern in the mask layer 300 can be accurately copied into the substrate 100, and avoid the second mask layer 320 being consumed when the substrate 100 is etched by using the mask layer 300 as a mask, the second mask layer 320 is generally configured to have a larger thickness dimension. In this embodiment, the thickness of the second mask layer 320 can be larger than the thickness of the first mask layer 310, for example, the thickness of the first mask layer 310 is between
The second mask layer 320 has a thickness dimension between
With continued reference to fig. 3a, in the masking layer 300, a second masking layer 320 is formed on the first masking layer 310. That is, the first mask layer 310 is closer to the isolation oxide layer 200 than the second mask layer 320, so that when the second mask layer 320 with a larger thickness in the mask layer 300 is removed, the first mask layer 310 can be used as an etching stop layer to prevent the etchant from eroding the isolation oxide layer 200 and the second semiconductor device 600 below the first mask layer 310. In this embodiment, the first mask layer 310 directly covers the surface of the isolation oxide layer 200.
It is understood that, in this embodiment, the mask layer 300 is a stacked structure formed by stacking at least two layers, and the first mask layer 310 is the lowest layer of the stacked structure, so that the first mask layer 310 directly covers the isolation oxide layer 200, and therefore, when the mask layer 300 is removed, the first mask layer 310 can be used as an etch stop layer of the upper mask layer.
In step S300, with continued reference to fig. 3a, the mask pattern in the mask layer 300 is copied into the substrate 100 for forming a first semiconductor device in the substrate 100 outside the isolation oxide layer 200. Specifically, the substrate 100 is etched by using the mask layer 300 as a mask, and the isolation oxide layer 200 and the second semiconductor device 600 are prevented from being damaged under the cover of the mask layer 300.
In this embodiment, the mask pattern in the mask layer 300 includes at least one opening, so that when the mask pattern is copied into the substrate 100, at least one trench 410 is correspondingly formed in the substrate 100. And, a trench gate field effect transistor may be further formed on the basis of the trench 410, for example, to further constitute a first semiconductor device.
In step S400, the mask layer 300 is removed, as shown with particular reference to fig. 3 b-3 c. In this embodiment, the mask layer 300 includes a second mask layer 320 and a first mask layer 310, and the second mask layer 320 and the first mask layer 310 are made of different materials, so that the second mask layer 320 and the first mask layer 310 can be sequentially removed by using different etching processes.
Specifically, the method for removing the mask layer 300 may include the following steps.
Step one, specifically referring to fig. 3b, a first etching process is performed to remove the second mask layer 320, and the etching is stopped on the first mask layer 310.
That is, in this embodiment, when the second mask layer 320 is etched, the first mask layer 310 is used as an etch stop layer, and at this time, even if the material of the second mask layer 320 is the same as the material of the isolation oxide layer 200 and a large over-etching amount is required to remove the second mask layer 320 with a large thickness, under the blocking of the first mask layer 310, the etchant of the first etching process can still be prevented from eroding the isolation oxide layer 200.
Step two, specifically referring to fig. 3c, a second etching process is performed to remove the first mask layer 310.
It should be appreciated that, since the material of the first mask layer 310 is different from the material of the isolation oxide layer 200, the etchant of the second etching process has a larger etching selectivity ratio for the first mask layer 310 and the isolation oxide layer 200, and thus, the isolation oxide layer 200 is not greatly eroded, and the isolation oxide layer 200 is prevented from being greatly consumed.
In this embodiment, the material of the first mask layer 310 includes silicon nitride, and the material of the isolation oxide layer 200 includes silicon oxide, based on which the etchant of the second etching process may include phosphoric acid to avoid eroding the isolation oxide layer 200.
With continued reference to fig. 3c, a liner oxide layer (including a first liner oxide layer 510 formed on the top surface of the substrate and a second liner oxide layer 520 formed on the surface of the second conductive layer) is also formed on the substrate 100. Therefore, when the first mask layer 310 is removed, the substrate 100 and the second semiconductor device 600 can be protected from etching damage under the protection of the substrate oxide layer.
In addition, as shown in fig. 3d, after removing the mask layer 300, the method further includes: and executing a third etching process to remove the lining oxide layer. The first etching process, the second etching process and the third etching process may be wet etching processes.
Note that the liner oxide layer is of a small thickness (e.g., in-between)
) Therefore, only a small amount of over-etching is required to ensure that the liner oxide layer is completely removed, and thus, the isolation oxide layer 200 is not greatly damaged.
As described above, in the present embodiment, at least one trench 410 is formed in the substrate 100 at the periphery of the isolation oxide layer 200, and a trench gate field effect transistor may be further formed based on the trench 410 to further form the first semiconductor device.
Referring specifically to fig. 3e, in a further aspect, the method for forming the semiconductor structure may further include: a first conductive layer 430 is formed in the trench 410.
The method for forming the first conductive layer 430 includes: first, a conductive material layer is deposited on the substrate 100, the conductive material layer fills the trench, and the conductive material layer also covers the top surface and sidewalls of the second semiconductor device 600 and the isolation oxide layer 200; then, an etch-back process is performed to remove a portion of the conductive material layer covering the second semiconductor device and the isolation oxide layer, and to retain a portion of the conductive material layer filled in the trench, so as to form the first conductive layer 430.
It should be appreciated that, based on the fact that the mask layer as described above is used in the present embodiment for protecting the second semiconductor device 600 and the isolation oxide layer 200 and defining at least part of the pattern of the first semiconductor device, i.e., the mask layer includes at least the first mask layer with a material different from that of the isolation oxide layer, it is possible to ensure that the etching agent has a smaller etching rate for the isolation oxide layer and avoid the isolation oxide layer from being consumed in a large amount at least when the first mask layer is removed. Therefore, on one hand, the isolation performance of the isolation oxide layer 200 can be ensured; on the other hand, when the first conductive layer of the first semiconductor device is prepared, since a larger step structure is not formed at a position corresponding to the sidewall of the second semiconductor device 600, the problem of the residual conductive material can be effectively avoided when the first conductive layer 430 is formed, and thus the second semiconductor device 600 is prevented from being adversely affected by the residual conductive material.
As described above, the first semiconductor device is, for example, a trench gate field effect transistor, and based on this, the first conductive layer 430 may be used to constitute a gate conductive layer. And, before forming the first conductive layer 430, further comprising: a gate oxide layer 420 is formed on the inner wall of the trench. Specifically, the gate oxide layer 420 may be formed by a thermal oxidation process, for example. In addition, when the gate oxide layer 420 is formed, a shielding oxide layer may be simultaneously formed on the top surface of the substrate 100 and the surface of the second conductive layer.
In addition, the embodiment also provides a semiconductor structure prepared by the method for forming the semiconductor device. Referring specifically to fig. 3e, the semiconductor structure includes: a substrate 100; an isolation oxide layer 200 formed on the substrate 100; a second semiconductor device 600 formed on the isolation oxide layer 200; and a first semiconductor device formed outside the isolation oxide layer 200.
As described above, when the method provided in this embodiment is used to fabricate the semiconductor structure, the problem that the isolation oxide layer 200 exposed from the second semiconductor device 600 is consumed in a large amount can be avoided, and the height difference between the second semiconductor device 600 and the isolation oxide layer 200 is effectively reduced, so that no conductive material remains at the sidewall of the second semiconductor device 600, which is beneficial to ensuring the overall device performance of the formed semiconductor structure.
It should be noted that, although the present invention has been described with reference to the preferred embodiments, the present invention is not limited to the embodiments. It will be apparent to those skilled in the art from this disclosure that many changes and modifications can be made, or equivalents modified, in the embodiments of the invention without departing from the scope of the invention. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention are still within the protection scope of the technical solution of the present invention, unless the content of the technical solution of the present invention is departed from.
It should be further understood that the terms "first," "second," "third," and the like in the description are used for distinguishing between various components, elements, steps, and the like, and are not intended to imply a logical or sequential relationship between various components, elements, steps, or the like, unless otherwise indicated or indicated.
It is also to be understood that the terminology used herein is for the purpose of describing particular embodiments only, and is not intended to limit the scope of the present invention. It must be noted that, as used herein and in the appended claims, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. For example, reference to "a step" or "an apparatus" means a reference to one or more steps or apparatuses and may include sub-steps as well as sub-apparatuses. All conjunctions used should be understood in the broadest sense. And, the word "or" should be understood to have the definition of a logical "or" rather than the definition of a logical "exclusive or" unless the context clearly dictates otherwise. Further, implementation of the methods and/or apparatus of embodiments of the present invention may include performing the selected task manually, automatically, or in combination.
Claims (10)
1. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein an isolation oxide layer is formed on the substrate, and a second semiconductor device is formed on the isolation oxide layer;
forming a mask layer on the substrate, wherein the mask layer at least comprises a first mask layer with a material different from that of the isolation oxide layer, the mask layer covers the isolation oxide layer and the second semiconductor device, and a mask pattern is further formed in a region, located outside the isolation oxide layer, in the mask layer;
copying the mask pattern into the substrate for forming a first semiconductor device on the substrate outside the isolation oxide layer; and the number of the first and second groups,
and removing the mask layer.
2. The method of forming a semiconductor structure of claim 1, further comprising, prior to forming the mask layer, forming a liner oxide layer on a top surface of the substrate; and when the mask layer is formed, the mask layer covers the lining oxide layer.
3. The method of forming a semiconductor structure of claim 1, wherein a material of the first mask layer comprises silicon nitride.
4. The method of claim 3, wherein an etching process is performed to remove the first mask layer, and an etchant of the etching process comprises phosphoric acid.
5. The method of claim 1, wherein the mask layer is at least two stacked structures stacked and the first mask layer is a bottom layer of the stacked structures, such that the first mask layer directly covers the isolation oxide layer;
and the laminated structure further comprises a second mask layer, wherein the material of the second mask layer is different from that of the first mask layer.
6. The method of forming a semiconductor structure of claim 5, wherein removing the mask layer comprises:
executing a first etching process to remove the second mask layer and etch and stop on the first mask layer; and the number of the first and second groups,
and executing a second etching process to remove the first mask layer.
7. The method of forming a semiconductor structure of claim 5, wherein a thickness of the second mask layer is greater than a thickness of the first mask layer.
8. The method of claim 1, wherein the mask pattern of the mask layer comprises at least one opening;
and, copying the mask pattern into the substrate comprises: at least one trench is formed in the substrate.
9. The method of forming a semiconductor structure of claim 1, wherein the second semiconductor device is a temperature sensor and the first semiconductor device is a trench gate field effect transistor.
10. A semiconductor structure prepared by the formation method according to any one of claims 1 to 9, wherein the semiconductor structure comprises:
a substrate;
an isolation oxide layer formed on the substrate;
a second semiconductor device formed on the isolation oxide layer; and the number of the first and second groups,
and the first semiconductor device is formed on the substrate outside the isolation oxide layer.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111540672A (en) * | 2020-06-22 | 2020-08-14 | 中芯集成电路制造(绍兴)有限公司 | Super junction device manufacturing method and super junction device |
| CN115084051A (en) * | 2022-05-11 | 2022-09-20 | 上海华虹宏力半导体制造有限公司 | Method for integrating temperature sensor polycrystalline silicon layer on IGBT chip |
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2019
- 2019-12-06 CN CN201911243526.1A patent/CN110911346A/en not_active Withdrawn
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111540672A (en) * | 2020-06-22 | 2020-08-14 | 中芯集成电路制造(绍兴)有限公司 | Super junction device manufacturing method and super junction device |
| CN115084051A (en) * | 2022-05-11 | 2022-09-20 | 上海华虹宏力半导体制造有限公司 | Method for integrating temperature sensor polycrystalline silicon layer on IGBT chip |
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