CN115084051A - Method for integrating temperature sensor polycrystalline silicon layer on IGBT chip - Google Patents
Method for integrating temperature sensor polycrystalline silicon layer on IGBT chip Download PDFInfo
- Publication number
- CN115084051A CN115084051A CN202210512897.0A CN202210512897A CN115084051A CN 115084051 A CN115084051 A CN 115084051A CN 202210512897 A CN202210512897 A CN 202210512897A CN 115084051 A CN115084051 A CN 115084051A
- Authority
- CN
- China
- Prior art keywords
- layer
- temperature sensor
- etching process
- dry etching
- polysilicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 122
- 238000000034 method Methods 0.000 title claims abstract description 97
- 229920005591 polysilicon Polymers 0.000 claims abstract description 98
- 230000008569 process Effects 0.000 claims abstract description 61
- 238000001312 dry etching Methods 0.000 claims abstract description 44
- 238000005530 etching Methods 0.000 claims abstract description 44
- 239000004065 semiconductor Substances 0.000 claims abstract description 35
- 239000000758 substrate Substances 0.000 claims description 26
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 22
- 239000007789 gas Substances 0.000 claims description 21
- 239000000460 chlorine Substances 0.000 claims description 15
- CPELXLSAUQHCOX-UHFFFAOYSA-N Hydrogen bromide Chemical compound Br CPELXLSAUQHCOX-UHFFFAOYSA-N 0.000 claims description 14
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 claims description 12
- 229910052801 chlorine Inorganic materials 0.000 claims description 12
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 claims description 8
- 229910000042 hydrogen bromide Inorganic materials 0.000 claims description 6
- 230000003647 oxidation Effects 0.000 claims description 6
- 238000007254 oxidation reaction Methods 0.000 claims description 6
- 229910018503 SF6 Inorganic materials 0.000 claims description 5
- SFZCNBIFKDRMGX-UHFFFAOYSA-N sulfur hexafluoride Chemical compound FS(F)(F)(F)(F)F SFZCNBIFKDRMGX-UHFFFAOYSA-N 0.000 claims description 5
- 229960000909 sulfur hexafluoride Drugs 0.000 claims description 5
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 10
- 235000012239 silicon dioxide Nutrition 0.000 description 9
- 239000000377 silicon dioxide Substances 0.000 description 9
- 238000002360 preparation method Methods 0.000 description 8
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 230000007547 defect Effects 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 238000001000 micrograph Methods 0.000 description 3
- 239000002245 particle Substances 0.000 description 3
- 230000035945 sensitivity Effects 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 239000001307 helium Substances 0.000 description 2
- 229910052734 helium Inorganic materials 0.000 description 2
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 238000012544 monitoring process Methods 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 101100027017 Caenorhabditis elegans ntc-1 gene Proteins 0.000 description 1
- 101100100146 Candida albicans NTC1 gene Proteins 0.000 description 1
- 229910002601 GaN Inorganic materials 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 238000001878 scanning electron micrograph Methods 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
- H01L21/32137—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Plasma & Fusion (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Manufacturing & Machinery (AREA)
- Drying Of Semiconductors (AREA)
Abstract
The invention provides a method for integrating a temperature sensor polycrystalline silicon layer on an IGBT chip, which comprises the following steps: providing a semiconductor structure; forming a second oxide layer on the upper surface of the semiconductor structure; forming a polysilicon layer on the upper surface of the second oxide layer; etching the polysilicon layer by adopting a first dry etching process until the second oxide layer is leaked out, so as to form a temperature sensor polysilicon layer in an active area at a preset distance of the polysilicon gate, and simultaneously forming a side wall on the side wall of the polysilicon gate; and etching by adopting a second dry etching process to remove the side wall. The invention solves the problem of poor precision of the existing temperature sensor.
Description
Technical Field
The invention relates to the field of semiconductor manufacturing, in particular to a method for integrating a temperature sensor polycrystalline silicon layer on an IGBT chip.
Background
An IGBT (Insulated Gate Bipolar Transistor) is a power Semiconductor device composed of BJTs (Bipolar Junction transistors) and MOS (Metal-Oxide-Semiconductor Field-Effect transistors), and has the characteristics of reduced on-state voltage, fast response speed, and simple control, and thus, is increasingly widely used in the Field of power electronics. In order to ensure that the IGBT chip can operate normally, it is necessary to avoid damage to the IGBT chip due to excessive chip temperature, and also to avoid shortening the lifetime of the IGBT chip due to excessive temperature fluctuations. Therefore, in order to make the IGBT chip exert better performance, it is necessary to integrate a temperature sensor inside to realize monitoring of its temperature.
At present, when a polysilicon layer of a temperature sensor is integrated on an IGBT chip, a polysilicon layer is laid over a gate polysilicon layer. However, the temperature sensor manufactured by the above method has poor sensitivity. Moreover, the contact hole shape of the polysilicon layer of the temperature sensor is not good due to the step height difference between the polysilicon layer and the gate polysilicon of the temperature sensor.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, the present invention aims to provide a method for integrating a temperature sensor polysilicon layer on an IGBT chip, which is used to solve the problem of poor sensitivity of the temperature sensor caused by the preparation of the temperature sensor polysilicon layer by the existing method.
To achieve the above and other related objects, the present invention provides a method for integrating a polysilicon layer of a temperature sensor on an IGBT chip, the method comprising:
providing a semiconductor structure, which comprises a semiconductor substrate, a groove formed in the semiconductor substrate, a first oxidation layer formed at the bottom and the side wall of the groove and on the upper surface of the semiconductor substrate, and a polysilicon gate filling the groove and extending to the outer part of the groove to the upper surface of the first oxidation layer;
forming a second oxide layer on the upper surface of the semiconductor structure;
forming a polysilicon layer on the upper surface of the second oxide layer;
etching the polysilicon layer by adopting a first dry etching process until the second oxide layer is leaked out, so as to form a temperature sensor polysilicon layer in an active area at a preset distance of the polysilicon gate, and simultaneously forming a side wall on the side wall of the polysilicon gate;
etching by adopting a second dry etching process to remove the side wall;
the first dry etching process is anisotropic etching, and the second dry etching process is isotropic etching.
Optionally, before the polysilicon layer is etched by the first dry etching process, the method further includes a step of defining a pattern of the temperature sensor polysilicon layer on the upper surface of the second oxide layer by using a mask layer.
Optionally, when the second dry etching process is performed to remove the side wall, the mask layer is used to protect the polysilicon layer of the temperature sensor.
Optionally, the method further comprises: and modifying the boundary morphology of the temperature sensor polycrystalline silicon layer by adopting a third dry etching process, wherein the third dry etching process is isotropic etching.
Optionally, before performing the third dry etching process, the method includes a step of removing the mask layer.
Optionally, the etching gas in the third dry etching process includes hydrogen bromide, chlorine, and carbon tetrafluoride.
Optionally, the material of the first oxide layer and the second oxide layer includes silicon oxide.
Optionally, the etching gas in the first dry etching process includes sulfur hexafluoride and chlorine; the etching gas in the second dry etching process comprises hydrogen bromide, chlorine and carbon tetrafluoride.
According to the method for integrating the temperature sensor polycrystalline silicon layer on the IGBT chip, the temperature sensor polycrystalline silicon layer is directly formed on the oxide layer of the active area of the IGBT chip, so that the temperature sensor polycrystalline silicon layer is prevented from being isolated from the semiconductor substrate by the grid polycrystalline silicon layer, and the precision of the temperature sensor is improved; in addition, in the process of preparing the temperature sensor polycrystalline silicon layer, the temperature sensor polycrystalline silicon layer is obtained by utilizing an anisotropic etching process, and then the residues on the side wall of the polycrystalline silicon gate are removed by utilizing an isotropic etching process, so that the particle defect formed in the wafer is avoided, and the quality of the wafer is ensured.
Drawings
Fig. 1 to 5 are schematic cross-sectional views illustrating a conventional process for integrating a polysilicon layer of a temperature sensor on an IGBT chip.
Fig. 6 is a scanning electron microscope image of a contact hole of a polysilicon layer of a temperature sensor formed by a conventional method.
Fig. 7 shows a flow chart of a method for integrating a polysilicon layer of a temperature sensor on an IGBT chip according to the present invention.
Fig. 8-13 are schematic cross-sectional views illustrating a process of integrating a polysilicon layer of a temperature sensor on an IGBT chip according to the present invention.
Fig. 14 is a scanning electron micrograph of a polysilicon gate formed using the present invention.
Fig. 15 is a scanning electron microscope image of a polysilicon layer of a temperature sensor formed by the present invention.
FIG. 16 is a scanning electron microscope image of a sidewall formed after the first dry etching process of the present invention.
Fig. 17 shows a top view of a temperature sensor formed using the present invention.
Fig. 18 shows a temperature-voltage graph of the NTC temperature sensor.
Description of the element reference numerals
10. 101 semiconductor substrate
20. 102 trench
30 first silicon dioxide layer
40 grid polycrystalline silicon layer
41. 104 polysilicon gate
50 second silicon dioxide layer
60. 300 polycrystalline silicon layer
61 polysilicon layer of temperature sensor
70 photo resist
100 semiconductor structure
103 first oxide layer
200 second oxide layer
400 side wall
500 mask layer
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 1 to 18. It should be noted that the drawings provided in the present embodiment are only schematic and illustrate the basic idea of the present invention, and although the drawings only show the components related to the present invention and are not drawn according to the number, shape and size of the components in actual implementation, the form, quantity and proportion of the components in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.
Fig. 1 to 5 provide schematic structural diagrams corresponding to a method for integrating a polysilicon layer of a temperature sensor on an IGBT chip.
As shown in fig. 1, a semiconductor substrate 10 having a trench 20 is provided, and a silicon dioxide layer 30 is formed on the bottom, the sidewall and the upper surface of the semiconductor substrate 10 of the trench 20; filling a gate polysilicon layer 40 in the trench 20, and extending the gate polysilicon layer 40 to the upper surface of the first silicon dioxide layer 30; forming a second silicon dioxide layer 50 on the upper surface of the gate polysilicon layer 40; a polysilicon layer 60 is formed on the upper surface of the second silicon dioxide layer 50.
As shown in fig. 2, the temperature sensor polysilicon layer 61 is patterned by using a photoresist 70, and the polysilicon layer 60, which is not protected by the photoresist 70, is removed by using an etching process to form the temperature sensor polysilicon layer 61.
As shown in fig. 3, the photoresist 70 on the upper surface of the polysilicon layer 61 of the temperature sensor is removed.
As shown in fig. 4, a photoresist 70 is used to protect the polysilicon layer 61 of the temperature sensor and to define the pattern of the polysilicon gate 41, and an etching process is used to etch the gate polysilicon layer 40 until the first silicon dioxide layer 30 is exposed to obtain the polysilicon gate 41.
As shown in fig. 5, the photoresist on the upper surface and the sidewalls of the polysilicon gate 41 and the temperature sensor polysilicon layer 61 is removed.
The method for preparing the temperature sensor polycrystalline silicon layer is that the temperature sensor polycrystalline silicon layer is defined firstly, and then the polycrystalline silicon gate is defined, so that the temperature sensor polycrystalline silicon layer is separated from the substrate through the grid polycrystalline silicon, and the sensitivity of the temperature sensor is poor. Moreover, the step height difference between the temperature sensor polysilicon layer and the gate polysilicon layer may cause the contact hole of the temperature sensor polysilicon layer to have a poor shape (as shown in fig. 6).
As shown in fig. 7, the present embodiment provides a method for integrating a temperature sensor polysilicon layer on an IGBT chip, the method including:
providing a semiconductor structure 100 comprising a semiconductor substrate 101, a trench 102 formed in the semiconductor substrate 101, a first oxide layer 103 formed on the bottom and the sidewall of the trench 102 and the upper surface of the semiconductor substrate 101, and a polysilicon gate 104 filling the trench 102 and extending outward to the trench 102 to a portion of the upper surface of the first oxide layer 103;
forming a second oxide layer 200 on the upper surface of the semiconductor structure 100;
forming a polysilicon layer 300 on the upper surface of the second oxide layer 200;
etching the polysilicon layer 300 by adopting a first dry etching process until the second oxide layer 200 leaks out, so as to form a temperature sensor polysilicon layer 310 in an active area at a preset distance of the polysilicon gate 104, and simultaneously forming a side wall 400 on the side wall of the polysilicon gate 104;
etching by adopting a second dry etching process to remove the side wall 400;
the first dry etching process is anisotropic etching, and the second dry etching process is isotropic etching.
The preparation method of the present embodiment is described in detail below with reference to fig. 8 to 13:
as shown in fig. 8, a semiconductor structure 100 is provided, which includes a semiconductor substrate 101, a trench 102 formed in the semiconductor substrate 101, a first oxide layer 103 formed on the bottom, sidewalls and upper surface of the semiconductor substrate 101, and a polysilicon gate 104 filling the trench 102 and extending outwardly to the trench 102 to a portion of the upper surface of the first oxide layer 103.
The semiconductor substrate 101 includes, but is not limited to, a silicon substrate, a gallium nitride substrate, a silicon-on-insulator substrate. Optionally, in this embodiment, the semiconductor substrate is a silicon substrate.
Specifically, the material of the first oxide layer 103 includes silicon oxide. In this embodiment, the first oxide layer is made of silicon dioxide. The first oxide layer 103 may be formed on the bottom, the sidewall of the trench 102 and the upper surface of the semiconductor substrate 101 by a thermal oxidation process or a chemical vapor deposition process.
In this embodiment, the specific process of forming the polysilicon gate 104 is as follows: after the first oxide layer 103 is formed, the trench 102 is filled with a gate polysilicon layer, the gate polysilicon layer covers the first oxide layer 103 on the upper surface of the semiconductor substrate 101, a pattern of the polysilicon gate 104 is defined by photoresist, the gate polysilicon layer which is not protected by the photoresist is removed by an anisotropic dry etching process to form the polysilicon gate 104, and finally the photoresist is removed. And in the specific preparation, the grid polycrystalline silicon layer can be generated through a chemical vapor deposition process. And the thickness of the gate polysilicon layer formed on the upper surface of the first oxide layer 103 outside the trench 102 is 5000A-15000A. Optionally, in this embodiment, the gate polysilicon layer is deposited at a thickness of 8000 a (as shown in fig. 14).
As shown in fig. 9, a second oxide layer 200 is formed on the upper surface of the semiconductor structure 100.
Specifically, the material of the second oxide layer 200 includes silicon oxide. In this embodiment, the second oxide layer is made of silicon dioxide, and the second oxide layer 200 may be formed through a thermal oxidation process or a chemical vapor deposition process. Moreover, the thickness of the second oxide layer 200 may be the same as or different from the thickness of the first oxide layer 103, and may be selected according to the needs in the specific preparation process.
As shown in fig. 10, a polysilicon layer 300 is formed on the upper surface of the second oxide layer 200. In this embodiment, the polysilicon layer 300 may be formed by a chemical vapor deposition method. Moreover, the thickness of the polysilicon layer 300 comprises 1500A-15000A. Optionally, the thickness of the polysilicon layer 300 in this embodiment is 6000 a (as shown in fig. 15).
As shown in fig. 11, the polysilicon layer 300 is etched by a first dry etching process until the second oxide layer 200 leaks out, so as to form a temperature sensor polysilicon layer 310 in an active region at a predetermined distance from the polysilicon gate 104, and simultaneously form a sidewall 400 on a sidewall of the polysilicon gate 104.
Specifically, before the first dry etching process is performed to etch the polysilicon layer 300, the method further includes a step of defining a pattern of the temperature sensor polysilicon layer 310 on the upper surface of the second oxide layer 200 by using a mask layer 500. In this embodiment, the material of the mask layer 500 includes, but is not limited to, photoresist.
More specifically, the etching gas in the first dry etching process comprises sulfur hexafluoride (SF) 6 ) And chlorine (Cl) 2 ). In this embodiment, the flow range of the etching gas sulfur hexafluoride can be selected from 30sccm to 150sccm, the flow range of the chlorine can be selected from 90sccm to 110sccm, and the flow range of the etching gas required can be selected as required in the actual preparation process.
However, when the polysilicon layer 300 is etched by using the first dry etching process to form the temperature sensor polysilicon layer 310 in the active region of the IGBT chip, a sidewall 400 is formed on the sidewall of the polysilicon gate 104, and the sidewall 400 is a polysilicon residue (as shown in fig. 16), and drops in the subsequent preparation process (such as a wet process), which may cause a serious particle defect in the wafer (wafer), and thus needs to be removed.
As shown in fig. 12, a second dry etching process is used to etch to remove the sidewall spacers 400.
Specifically, the etching gas in the second dry etching process includes hydrogen bromide (HBr) and chlorine (Cl) 2 ) Carbon tetrafluoride (CF 4). In this embodiment, the flow range of the etching gas hydrogen bromide can be selected from 150sccm to 200sccm, the flow range of the etching gas chlorine can be selected from 150sccm to 200sccm, the flow range of the etching gas carbon tetrafluoride can be selected from 40sccm to 50sccm, and the flow range of the required etching gas can be selected as required in the actual preparation process. Further, the etching gas further includes oxygen (O) 2 ) And helium (He).
More specifically, when the sidewall 400 is removed by the second dry etching process, the temperature sensor polysilicon layer 310 is protected by the mask layer 500. In this embodiment, when the second dry etching process is performed, the polysilicon under the edge of the mask layer 500 is etched away, so that an arc is formed on the side of the temperature sensor 310, and therefore, the boundary of the temperature sensor polysilicon layer 310 needs to be modified.
As shown in fig. 13, the method further includes: and modifying the boundary morphology of the temperature sensor polysilicon layer 310 by adopting a third dry etching process, wherein the third dry etching process is isotropic etching. In this embodiment, the etching gas in the third dry etching process includes hydrogen bromide (HBr) and chlorine (Cl) 2 ) Carbon tetrafluoride (CF 4). In the embodiment, the flow range of the etching gas hydrogen bromide can be selected to be 150 sccm-200 sccm, the flow range of the etching gas chlorine can be selected to be 150 sccm-200 sccm, the flow range of the etching gas carbon tetrafluoride can be selected to be 40 sccm-50 sccm, and the flow range of the required etching gas can be selected as required in the actual preparation process. Go toThe etching gas further comprises oxygen (O) 2 ) And helium (He).
Specifically, before the third dry etching process is performed, the method includes a step of removing the mask layer 500.
According to the method, the NTC temperature sensor is prepared on the upper surface of the active area of the IGBT chip, the IGBT chip can be well protected due to the NTC temperature sensor, and more accurate monitoring can be achieved by arranging the NTC temperature sensors. Fig. 17 is a top view of a plurality of NTC temperature sensors. Fig. 18 shows a graph of temperature T versus voltage VF for 2 NTC temperature sensors (NTC 1 and NTC 2), from which it can be seen that the ratio of the voltage variation of NTC1 to the temperature variation thereof is smaller than the ratio of the voltage variation of NTC2 to the temperature variation thereof.
In summary, the present invention provides a method for integrating a temperature sensor polysilicon layer on an IGBT chip, in which the temperature sensor polysilicon layer is directly formed on an oxide layer of an active region of the IGBT chip, thereby preventing the temperature sensor polysilicon layer from being isolated from a semiconductor substrate by a gate polysilicon layer, and improving the accuracy of the temperature sensor; in addition, in the process of preparing the temperature sensor polycrystalline silicon layer, the temperature sensor polycrystalline silicon layer is obtained by utilizing an anisotropic etching process, and then the residues on the side wall of the polycrystalline silicon gate are removed by utilizing an isotropic etching process, so that the particle defect formed in the wafer is avoided, and the quality of the wafer is ensured. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (8)
1. A method of integrating a temperature sensor polysilicon layer on an IGBT chip, the method comprising:
providing a semiconductor structure, which comprises a semiconductor substrate, a groove formed in the semiconductor substrate, a first oxidation layer formed at the bottom and the side wall of the groove and on the upper surface of the semiconductor substrate, and a polysilicon gate filling the groove and extending to the outer part of the groove to the upper surface of the first oxidation layer;
forming a second oxide layer on the upper surface of the semiconductor structure;
forming a polysilicon layer on the upper surface of the second oxide layer;
etching the polysilicon layer by adopting a first dry etching process until the second oxide layer is leaked out, so as to form a temperature sensor polysilicon layer in an active area at a preset distance of the polysilicon gate, and simultaneously forming a side wall on the side wall of the polysilicon gate;
etching by adopting a second dry etching process to remove the side wall;
the first dry etching process is anisotropic etching, and the second dry etching process is isotropic etching.
2. The method of claim 1, wherein before the first dry etching process is performed to etch the polysilicon layer, the method further comprises a step of defining a pattern of the temperature sensor polysilicon layer on the upper surface of the second oxide layer by using a mask layer.
3. The method of claim 2, wherein the temperature sensor polysilicon layer is protected by the mask layer when the sidewall is removed by performing a second dry etching process.
4. The method of integrating a temperature sensor polysilicon layer on an IGBT chip according to claim 2 or 3, characterized in that the method further comprises: and modifying the boundary morphology of the temperature sensor polycrystalline silicon layer by adopting a third dry etching process, wherein the third dry etching process is isotropic etching.
5. The method of claim 4, wherein the method comprises a step of removing the mask layer before performing the third dry etching process.
6. The method of claim 4, wherein the etching gas in the third dry etching process comprises hydrogen bromide, chlorine and carbon tetrafluoride.
7. The method of claim 1, wherein the first oxide layer and the second oxide layer comprise silicon oxide.
8. The method of claim 1, wherein the etching gas in the first dry etching process comprises sulfur hexafluoride and chlorine; the etching gas in the second dry etching process comprises hydrogen bromide, chlorine and carbon tetrafluoride.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210512897.0A CN115084051A (en) | 2022-05-11 | 2022-05-11 | Method for integrating temperature sensor polycrystalline silicon layer on IGBT chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210512897.0A CN115084051A (en) | 2022-05-11 | 2022-05-11 | Method for integrating temperature sensor polycrystalline silicon layer on IGBT chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN115084051A true CN115084051A (en) | 2022-09-20 |
Family
ID=83247337
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210512897.0A Pending CN115084051A (en) | 2022-05-11 | 2022-05-11 | Method for integrating temperature sensor polycrystalline silicon layer on IGBT chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN115084051A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115602538A (en) * | 2022-12-13 | 2023-01-13 | 广州粤芯半导体技术有限公司（Cn） | Method for forming groove |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030082842A1 (en) * | 2001-10-31 | 2003-05-01 | National Taiwan University | On-chip temperature sensor formed of MOS tunneling diode |
| JP2004179608A (en) * | 2002-09-30 | 2004-06-24 | Sony Corp | Solid state imaging device and its manufacturing method |
| JP2010129707A (en) * | 2008-11-27 | 2010-06-10 | Fuji Electric Systems Co Ltd | Semiconductor device and method of manufacturing the same |
| CN109728081A (en) * | 2017-10-31 | 2019-05-07 | 比亚迪股份有限公司 | A kind of igbt chip and preparation method thereof |
| CN110911346A (en) * | 2019-12-06 | 2020-03-24 | 中芯集成电路制造(绍兴)有限公司 | Semiconductor structure and forming method thereof |
| CN111735549A (en) * | 2019-03-25 | 2020-10-02 | 株洲中车时代电气股份有限公司 | Temperature sensor integrated on IGBT chip and manufacturing method thereof |
-
2022
- 2022-05-11 CN CN202210512897.0A patent/CN115084051A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030082842A1 (en) * | 2001-10-31 | 2003-05-01 | National Taiwan University | On-chip temperature sensor formed of MOS tunneling diode |
| JP2004179608A (en) * | 2002-09-30 | 2004-06-24 | Sony Corp | Solid state imaging device and its manufacturing method |
| JP2010129707A (en) * | 2008-11-27 | 2010-06-10 | Fuji Electric Systems Co Ltd | Semiconductor device and method of manufacturing the same |
| CN109728081A (en) * | 2017-10-31 | 2019-05-07 | 比亚迪股份有限公司 | A kind of igbt chip and preparation method thereof |
| CN111735549A (en) * | 2019-03-25 | 2020-10-02 | 株洲中车时代电气股份有限公司 | Temperature sensor integrated on IGBT chip and manufacturing method thereof |
| CN110911346A (en) * | 2019-12-06 | 2020-03-24 | 中芯集成电路制造(绍兴)有限公司 | Semiconductor structure and forming method thereof |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115602538A (en) * | 2022-12-13 | 2023-01-13 | 广州粤芯半导体技术有限公司（Cn） | Method for forming groove |
| CN115602538B (en) * | 2022-12-13 | 2023-03-24 | 广州粤芯半导体技术有限公司 | Method for forming groove |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103985711B (en) | FinFETs with reduced parasitic capacitance and methods of forming the same | |
| US8853817B2 (en) | Isolation structure profile for gap filing | |
| US8236696B2 (en) | Transistor and method for fabricating the same | |
| CN102160158B (en) | Transistor with passive gate and methods of fabricating same | |
| US7344954B2 (en) | Method of manufacturing a capacitor deep trench and of etching a deep trench opening | |
| KR20080007404A (en) | Semiconductor processing methods, and semiconductor constructions | |
| CN107346759B (en) | Semiconductor structure and manufacturing method thereof | |
| US9515078B2 (en) | Semiconductor structure and method for forming the same | |
| CN105336571A (en) | Forming method of self-aligned multi-pattern mask | |
| TWI624032B (en) | Semiconductor device and method of forming the same | |
| TW201816855A (en) | Fin structure and method of forming the same | |
| KR102409130B1 (en) | Semiconductor device and manufacturing method thereof | |
| CN115084051A (en) | Method for integrating temperature sensor polycrystalline silicon layer on IGBT chip | |
| US20080290445A1 (en) | Method for manufacturing a semiconductor body with a trench and semiconductor body with a trench | |
| KR100597768B1 (en) | Method for fabricating gate spacer of semiconductor device | |
| CN108122843A (en) | The forming method and semiconductor structure of fin field effect pipe | |
| US20220037478A1 (en) | Fabrication method of buried wordline structure | |
| US20210118939A1 (en) | Method for forming image sensor | |
| CN114156183A (en) | Split gate power MOS device and manufacturing method thereof | |
| CN108831829B (en) | Side wall grid isolation etching film layer process under split gate structure | |
| US6541342B2 (en) | Method for fabricating element isolating film of semiconductor device, and structure of the same | |
| TWI833266B (en) | Semiconductor device and manufacturing method thereof | |
| US7629673B2 (en) | Contact etch stop film | |
| CN115116852A (en) | MOSFET device and manufacturing method thereof | |
| CN108565249B (en) | Method for forming flash memory side wall |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |