CN109728081A - A kind of igbt chip and preparation method thereof - Google Patents
A kind of igbt chip and preparation method thereof Download PDFInfo
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- CN109728081A CN109728081A CN201711045344.4A CN201711045344A CN109728081A CN 109728081 A CN109728081 A CN 109728081A CN 201711045344 A CN201711045344 A CN 201711045344A CN 109728081 A CN109728081 A CN 109728081A
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Abstract
The problem of temperature detection is there are hysteresis quality in encapsulating structure to overcome existing igbt chip, influences module protection effect, the present invention provides a kind of igbt chips, including insulated gate bipolar transistor area and diode region；The diode region includes silicon layer, first electrode and second electrode, and diode p type island region and diode N-type region are formed on the silicon layer, and the first electrode is electrically coupled with the diode p type island region, and the second electrode is electrically coupled with the diode N-type region；The insulated gate bipolar transistor area has substrate, and the partial region of the substrate is covered with field oxygen zone, and the silicon layer is formed in the field oxygen zone, so that the diode region and insulated gate bipolar transistor area mutually insulated are thermally conductive.Meanwhile the invention also discloses the preparation methods of above-mentioned igbt chip.Igbt chip provided by the invention is integrated with the diode region that can be used for temperature sense, can be improved the speed and accuracy of temperature sense, igbt chip is protected not to be damaged by heat.
Description
Technical field
The invention belongs to insulated gate bipolar transistor technical field of structures, and in particular to a kind of igbt chip and its preparation
Method.
Background technique
Insulated gate bipolar transistor IGBT (Insulated Gate Bipolar Transistor) comes out in recent years
Power semiconductor has on-state voltage drop low, the big feature of electric current handling capacity compared with MOSFET.With the hair of technology
Exhibition, it is wide that application field covers every field, the application prospects such as locomotive traction, new energy (such as electric car) and consumer electronics
It is wealthy.
The encapsulation of IGBT mainly uses the temperature detection of separate type at present, i.e., is welded on individual temperature detection diode
On module base, when temperature detection diode detects that IGBT or FRD are when the temperature is excessively high in module, external circuit is by detecting
Voltage change adjust the switch state of IGBT in time and prevent module damage to reduce temperature in time.
In above traditional module packaging technique, when temperature detection diode detects that temperature anomaly often lags behind IGBT
The variation of surface temperature causes to protect signal that can not timely pass to IGBT, while there is also the possibility of malfunction, so that
Module protection effect is bad.
Summary of the invention
For temperature detection in the encapsulating structure of existing igbt chip, there are hysteresis qualitys, influence asking for module protection effect
Topic, the present invention provides a kind of insulated gate bipolar transistors.
It is as follows that the present invention solves technical solution used by above-mentioned technical problem:
On the one hand, the embodiment of the invention provides a kind of igbt chips, double including the insulated gate electrode for conducting control
The diode region in polar crystal area under control and the temperature for incuding the insulated gate bipolar transistor area；
The diode region includes silicon layer, first electrode and second electrode, be formed on the silicon layer diode p type island region and
Diode N-type region, the first electrode are electrically coupled with the diode p type island region, the second electrode and the diode N-type region
It is electrically coupled；
The insulated gate bipolar transistor area has substrate, and the partial region of the substrate is covered with field oxygen zone, described
Silicon layer is formed in the field oxygen zone, so that the diode region and insulated gate bipolar transistor area mutually insulated are led
Heat.
Optionally, the silicon layer is polysilicon layer.
Optionally, the insulated gate bipolar transistor area further include collector, collector area, p type island region, N+ emitter region,
Grid oxygen area, gate electrode and emitter, the collector area is formed in the substrate surface, and the collector area has first to lead
Electric similar properties, the substrate have the second conduction type characteristic, and the collector is electrically coupled with the collector area, the P
Type area is formed on the substrate, and the N+ emitter region is isolated with the substrate by the p type island region, and the p type island region is distinguished
The emitter and the grid oxygen area are connected, the gate electrode is located at the one side for deviating from the p type island region in the grid oxygen area, described
N+ emitter region is electrically coupled with the emitter.
Optionally, the field oxygen zone is formed in the surface for deviating from the collector area on the substrate.
Optionally, the p type island region is located at the side for deviating from the collector area on the substrate, and the p type island region is embedded in
In the surface of the substrate, the p type island region includes p-well region and the injection region P+, and the injection region P+ is formed in the p-well region
Portion, the N+ emitter region are surrounded between the outer rim and the p-well region of the injection region P+, and the injection region P+ connects the hair
Emitter-base bandgap grading, the p-well region connect the grid oxygen area.
Optionally, the igbt chip further includes insulating medium layer, the insulating medium layer be covered in the gate electrode and
The outer surface of the silicon layer, and mutually completely cut off between the gate electrode and the silicon layer by the insulating medium layer；It is described exhausted
The first intercommunicating pore for being connected to the injection region P+ and the N+ emitter region is formed on edge dielectric layer, for being connected to described two
Second intercommunicating pore of pole pipe p type island region, and the third connecting hole for being connected to the diode N-type region；The emitter passes through
The first connection through-hole is electrically coupled with the injection region P+ and the N+ emitter region；The first electrode passes through described second and connects
Hole is connected to be electrically coupled with the diode p type island region；The second electrode passes through third connection through-hole and the diode N-type
Area is electrically coupled.
Optionally, the insulating medium layer is Si3N4+ USG+BPSG or USG+BPSG, the insulating medium layer with a thickness of
0.5um~3um.
On the other hand, the embodiment of the invention also provides the preparation methods of igbt chip as described above, including following behaviour
Make step:
Field oxygen zone is covered in the partial region of substrate；
Silicon layer is formed in field oxygen zone；
Diode p type island region and diode N-type region are formed on silicon layer；
The first electrode being electrically coupled with diode p type island region is drawn, the second electrode being electrically coupled with diode N-type region is drawn；
Prior to, concurrently with, or after above-mentioned steps, insulated gate bipolar transistor area is formed over the substrate.
Optionally, described " covering field oxygen zone in the partial region of substrate " includes:
Grow layer of silicon dioxide layer with the method for thermal oxide or chemical vapor deposition on substrate, then by photoetching and
The method of etching removes silicon dioxide layer redundance, forms field oxygen zone.
Optionally, after described " covering field oxygen zone in the partial region of substrate " further include: on substrate with thermal oxide
Surface of the method on substrate in addition to field oxygen zone grows the grid oxygen area of layer of silicon dioxide；
" silicon layer is formed in field oxygen zone " includes: by way of chemical vapor deposition in grid oxygen area and field oxygen zone
Surface deposits one layer of polysilicon, and the predetermined portions pattern of polysilicon is then removed by way of photoetching and dry etching, to obtain in place
In the silicon layer in the field oxygen zone and the gate electrode in grid oxygen area, the silicon layer and the gate electrode mutually completely cut off, in institute
The opening for being formed on gate electrode and being connected to the substrate surface is stated, substrate portions are exposed.
Optionally, described " diode p type island region and diode N-type region are formed on silicon layer " includes:
Diode p type island region and diode N-type region are formed on silicon layer by way of photoetching and ion implanting, in the lining
Bottom forms p-well region by way of photoetching and ion implanting, passes through photoetching and ion implanting in the position that the opening is exposed
Mode form the injection region P+ in the center of the p-well region, then in the p-well region by way of photoetching and ion implanting
N+ emitter region is formed between the injection region P+.
Optionally, the injection ion of the p-well region, the injection region P+ and the diode p type island region is boron ion, described
The implantation dosage of p-well region is 1E13~9E14 ion/cm2, the implantation dosage of the injection region P+ be 1E14~1E16 ion/
cm2, diode p type island region dosage is 1E13~1E16 ion/cm2；The note of the N+ emitter region and the diode N-type region
Entering ion is arsenic ion or phosphonium ion, and the N+ emitter region implantation dosage is 1E14~1E16 ion/cm2, the diode N-type
Area's implantation dosage is 5E14~1E16 ion/cm2。
Optionally, described " to draw the first electrode being electrically coupled with diode p type island region, extraction is electrically coupled with diode N-type region
Second electrode " include:
It is formed with the outside deposition insulating medium layer of gate electrode and silicon layer over the substrate, and passes through photoetching and etching
Mode the surface of the insulating medium layer be formed with for being connected to the injection region P+ and the N+ emitter region first connect
Through-hole, the third for being connected to the second intercommunicating pore of the diode p type island region, and for being connected to the diode N-type region connect
Through-hole；
The deposited metal layer on insulating medium layer, the metal layer by first intercommunicating pore and the injection region P+ and
The N+ emitter region connection, the metal layer are connect by second intercommunicating pore with the diode p type island region, the metal layer
It is connect by described and third connecting hole with the diode N-type region；By photoetching and etching formed predetermined pattern emitter,
First electrode and second electrode, the emitter pass through the first connection through-hole and the injection region P+ and the N+ emitter region
It is electrically coupled；The first electrode passes through the second connection through-hole and is electrically coupled with the diode p type island region；The second electrode is worn
The third connection through-hole is crossed to be electrically coupled with the diode N-type region.
Optionally, described " to draw the first electrode being electrically coupled with diode p type island region, extraction is electrically coupled with diode N-type region
Second electrode " after further include:
The thinning back side that substrate is deviated to the polysilicon carries out ion implanting on the back side of substrate and forms collector
Area, so that the collector area has the first conduction type characteristic, the substrate has the second conduction type characteristic, in the collection
The surface of electrode district forms collector by the method for evaporation or sputtering.
Optionally, before described " covering field oxygen zone in the partial region of substrate " further include:
Using the highly doped silicon with the first conduction type characteristic as collector area, on the highly doped surface of collector area
It carries out growth and is epitaxially formed the substrate with the second conduction type characteristic, it is logical away from the surface of the substrate in the collector area
Pervaporation or the method for sputtering form collector.
Igbt chip provided by the invention, is integrated with the diode region that can be used for temperature sense on igbt chip surface, and two
Pole pipe Qu Yuqi is conducted only by floor field oxygen zone insulation heat transfer between the insulated gate bipolar transistor area of control, once
Igbt chip surface current increases temperature and increases, it will it is communicated the temperature on diode region with the extremely short time, and diode
Diode p type island region and diode N-type region are formed in area, the PN junction electric conductivity of formation is increased with temperature to be changed, and two poles are caused
Area under control itself will lead to the change of VF (Forward Voltage, forward voltage) with temperature change, in this way in external detection electricity
Road can detect corresponding △ VF variation, so as to feed back temperature change to control circuit, to adjust an IGBT in time
Open and turn off.Compared to the prior art, reaction speed faster, simultaneously because insulated gate bipolar transistor area and two poles
Area under control manufactures simultaneously, can there is better consistency, more convenient fine tuning temperature-sensitive curve.
Detailed description of the invention
Fig. 1 is the sectional view of igbt chip provided in an embodiment of the present invention；
Fig. 2 is the relation curve between the VF value and junction temperature Tj of its diode region of igbt chip provided in an embodiment of the present invention
Figure.
Appended drawing reference in Figure of description is as follows:
1, insulated gate bipolar transistor area；11, emitter；12, insulating medium layer；121, the first connection through-hole；122,
Second connection through-hole；123, third connects through-hole；13, gate electrode；131, it is open；14, grid oxygen area；15, N+ emitter region；16, p-type
Area；161, the injection region P+；162, p-well region；17, substrate；18, collector area；19, collector；2, diode region；21, the first electricity
Pole；22, second electrode；23, silicon layer；231, diode p type island region；232, diode N-type region；3, field oxygen zone.
Specific embodiment
In order to which the technical problems, technical solutions and beneficial effects solved by the present invention is more clearly understood, below in conjunction with
Accompanying drawings and embodiments, the present invention will be described in further detail.It should be appreciated that specific embodiment described herein is only used
To explain the present invention, it is not intended to limit the present invention.
Embodiment one
Shown in Figure 1, embodiment one discloses a kind of igbt chip, double including the insulated gate electrode for conducting control
The diode region 2 in polar crystal area under control 1 and the temperature for incuding the insulated gate bipolar transistor area 1；
The diode region 2 includes silicon layer 23, first electrode 21 and second electrode 22, is formed with two poles on the silicon layer 23
Pipe p type island region 231 and diode N-type region 232, the first electrode 21 are electrically coupled with the diode p type island region 231, and described second
Electrode 22 is electrically coupled with the diode N-type region 232；
The insulated gate bipolar transistor area 1 has substrate 17, and the partial region of the substrate 17 is covered with field oxygen zone
3, the silicon layer 23 is formed in the field oxygen zone 3, so that the diode region 2 and the insulated gate bipolar transistor area 1
Mutually insulated is thermally conductive.
The field oxygen zone 3 is insulating materials, can avoid the diode region 2 and the insulated gate bipolar transistor area 1
Between existing electrical property influence each other.
It is integrated with the diode region 2 that can be used for temperature sense on the igbt chip surface, diode region 2 is conducted with rising
It is only conducted heat by a floor field oxygen zone 3 insulation between the insulated gate bipolar transistor area 1 of control, once igbt chip surface current
Increase temperature to increase, it will communicate the temperature on diode region 2 with the extremely short time, and be formed with two poles on diode region 2
Pipe p type island region 231 and diode N-type region 232, the PN junction electric conductivity of formation is increased with temperature to be changed, and leads to diode region 2 itself
As temperature change will lead to the change of VF (Forward Voltage, forward voltage), in this way in outer detecting circuit
Detect corresponding △ VF variation, so as to by temperature change feedback to control circuit, with adjust in time IGBT open with
Shutdown.In the present embodiment, the silicon layer 23 is polysilicon layer.
It is usually negative temperature coefficient by the diode region 2 that polysilicon layer makes, when igbt chip is powered, chip list
Face temperature can increase, and since our temperature detection diode is integrated on igbt chip, centre is only every a thin layer of
Field oxygen zone 3, so temperature can be transmitted on diode quickly, due to the negative temperature coefficient feature of diode, on igbt chip
Temperature it is higher, the VF value of diode will reduce accordingly, and outer detecting circuit is by detecting VF value and scheduled pass
It is that curve can extrapolate the temperature on igbt chip surface in time and adjust ON-OFF control circuit in time, shortens igbt chip
Service time, and igbt chip service time shortens, the calorific value of chip surface will reduce, and temperature just reduces accordingly,
Igbt chip overheat may finally be avoided to burn.
As shown in Fig. 2, in the present embodiment between the VF value of diode region 2 and the junction temperature Tj in edge gate bipolar transistor area
Graph of relation, You Tuzhong can be seen that, as the junction temperature Tj in edge gate bipolar transistor area is increased, the diode region 2
VF value is gradually reduced.
It should be noted that in other embodiments, the silicon layer 23 can also be used other and realize same or like function
Material, such as monocrystalline silicon layer etc..
In the present embodiment, the insulated gate bipolar transistor area 1 further includes collector 19, collector area 18, p type island region
16, N+ emitter region 15, grid oxygen area 14, gate electrode 13 and emitter 11, the collector area 18 are formed in 17 surface of substrate,
And the collector area 18 has the first conduction type characteristic, the substrate 17 has the second conduction type characteristic, the current collection
Pole 19 is electrically coupled with the collector area 18, and the p type island region 16 is formed on the substrate 17, the N+ emitter region 15 with it is described
Substrate 17 is isolated by the p type island region 16, and the p type island region 16 is separately connected the emitter 11 and the grid oxygen area 14, institute
It states gate electrode 13 and is located at the one side for deviating from the p type island region 16 in the grid oxygen area 14, the N+ emitter region 15 and the emitter
11 are electrically coupled.
The substrate 17 and the collector area 18 are silicon materials.
The first conduction type characteristic can be p-type, be also possible to N-type, when the first conduction type characteristic is p-type
When, the second conduction type characteristic is N-type；When the first conduction type characteristic is N-type, second conduction type is special
Property is p-type.
In the present embodiment, the first wire type characteristic is p-type, and the second conduction type characteristic is N-type.
The insulated gate bipolar transistor area 1 is used for the control conducted, and control principle is:
The emitter 11 is used for the transmitting of electronics, accesses the low potential of power supply, and the emitter 11 and the N+ are sent out
It penetrates area 15 to be electrically coupled, the collector 19 is used for the collection of electronics, accesses the high potential of power supply, and the collector 19 and current collection
Polar region 18 is electrically coupled, and the collector area 18 is electrically coupled with the substrate 17, due to the N+ emitter region 15 and has N-type characteristic
Substrate 17 between be isolated by the p type island region 16, and the conductive of the N+ emitter region 15 and the substrate 17 with N-type characteristic carries
Body is electronegative electronics, and the conductive carrier of the p type island region 16 is positively charged hole, therefore the emitter 11 and the current collection
It is nonconducting state in the initial state between pole 19；The p type island region 16 is separately connected the emitter 11 and the grid oxygen area
14, the gate electrode 13 is arranged by the grid oxygen area 14 and the p type island region 16 interval, and the resistance in the grid oxygen area 14 is larger,
Similar capacitance structure is formed i.e. between the p type island region 16 and the gate electrode 13, is sent out when applying ratio on the gate electrode 13
The high current potential of emitter-base bandgap grading 11 and when reaching certain potentials difference, can be in p type island region 16 close to grid oxygen area by the attraction of gate electrode 13
14 side forms electronics aggregation, so that the N+ emitter region 15 and the substrate 17 with N-type characteristic be connected, makes the emitter
11 and the collector 19 it is in the conductive state, when the gate electrode 13 apply the current potential lower than emitter 11 then make it is described
Emitter 11 and the collector 19 are restored to nonconducting state, realize the control conducted.
In other embodiments, the first wire type characteristic is N-type, and the second conduction type characteristic is p-type, this
Shi Suoshu insulated gate bipolar transistor area 1 forms the field-effect tube structure for being similar to NPN type, the emitter 11 and the collection
The voltage applied on electrode 19 is contrary to the above, and specific workflow is known to those skilled in the art, repeats no more.
In the present embodiment, the field oxygen zone 3 is formed in the surface for deviating from the collector area 18 on the substrate 17.
In other embodiments, the field oxygen zone 3 is also possible to be set to its of the insulated gate bipolar transistor area 1
His surface, for example can be the surface that the collector area 18 is provided on the substrate 17, it can be the gate electrode 13
The surface in surface or the grid oxygen area 14 should all include within protection scope of the present invention.
It should be noted that the substrate 17 is the biggish position of calorific value on the igbt chip, the field oxygen zone 3
It is directly contacted with the substrate 17, advantageously reduces the thermal resistance of diode region 2 and the insulated gate bipolar transistor area 1, mention
High-heat conductive efficency.
In the present embodiment, the p type island region 16 is located at the side for deviating from the collector area 18 on the substrate 17, described
P type island region 16 is formed by the partial region of the substrate 17 by ion implanting and thermal diffusion, thus the p type island region 16 be embedded in it is described
The surface of substrate 17 is integrally formed with the substrate 17.
The p type island region 16 includes p-well region 162 and the injection region P+ 161, and the injection region P+ 161 is formed in the p-well region
The majority carrier concentration at 162 middle part, the p type island region 16 depends on its ion doping concentration, in the present embodiment, the P+
The ion doping concentration of injection region 161 is greater than the ion doping concentration of the p-well region 162, advantageously reduces the injection region P+
Contact resistance between 161 and the emitter 11, the N+ emitter region 15 are surrounded on outer rim and the institute of the injection region P+ 161
It states between p-well region 162, the injection region P+ 161 connects the emitter 11, and the p-well region 162 connects the grid oxygen area 14.
It should be noted that in other embodiments, the p type island region 16 can also only include the p-well region 162, pass through institute
It states p-well region 162 and is separately connected the emitter 11 and the grid oxygen area 14.
In the present embodiment, the igbt chip further includes insulating medium layer 12, and the insulating medium layer 12 is covered in institute
The outer surface for stating gate electrode 13 and the silicon layer 23 avoids external electrical interference；And the gate electrode 13 and the silicon layer 23
Between by the mutually isolation of the insulating medium layer 12, to avoid the electricity between the gate electrode 13 and the insulating medium layer 12
Property interference.
First for being connected to the injection region P+ 161 and the N+ emitter region 15 is formed on the insulating medium layer 12
Intercommunicating pore, for being connected to the second intercommunicating pore of the diode p type island region 231, and for being connected to the diode N-type region 232
Third connecting hole；The emitter 11 passes through the first connection through-hole 121 and the injection region P+ 161 and the N+ emits
Area 15 is electrically coupled；The first electrode 21 passes through the second connection through-hole 122 and is electrically coupled with the diode p type island region 231；Institute
It states second electrode 22 to be electrically coupled across third connection through-hole 123 with the diode N-type region 232, and passes through the insulation
Dielectric layer 12 completely cuts off the emitter 11 and the gate electrode 13.
In the present embodiment, the insulating medium layer 12 is Si3N4(Undoped Silicate Glass is undoped by+USG
Silica glass)+BPSG (boro-phospho-silicate-glass boron-phosphorosilicate glass) or USG+BPSG, the dielectric
Layer 12 with a thickness of 0.5um~3um, if the thickness of the insulating medium layer 12 is too thin, insulation effect is poor, is easy to appear
Electrical breakdown problem；If the thickness of the insulating medium layer 12 is too thick, higher cost, the first connection through-hole 121, the are improved
Two connection through-holes 122 connect the difficulty of processing of through-hole 123 with third.
The collector 19 be metal material, specifically, the collector 19 be Ti/Ni/Ag or Al/Ti/Ni/Ag or
Al/TiN/Ni/Ag, the collector 19 with a thickness of 0.5um~10um.
The resistivity of the substrate 17 is 10~300ohm.cm.
The emitter 11 be AlSi or AlSiCu, the emitter 11 with a thickness of 1um~5um.Specifically, in part
In embodiment, the first electrode 21, second electrode 22 and emitter 11, which are that same metal deposition layer is etched, to be obtained, therefore described
First electrode 21, the material of second electrode 22 are identical as the material of the emitter 11 and thickness.
The field oxygen zone 3 is silicon dioxide layer, the field oxygen zone 3 with a thickness of 0.1um~2um, if the field oxygen zone 3
Thickness is too thin, then is difficult to play electric insulating effect, so that the VF value of the diode region 2 is by insulated gate bipolar transistor area
1 current potential influences.
The grid oxygen area 14 be silicon dioxide layer, the grid oxygen area 14 with a thickness of 0.05um~2um, if the grid oxygen area
14 thickness is too thin, then electrical breakdown easy to form, influences the electronics aggregation in the p type island region 16；If the thickness in the grid oxygen area 14
Degree is too thick, then can be attenuated to the gate electrode 13 to the electronics sucting strength in the p type island region 16, and then influence 11 He of emitter
Current flowing between collector 19.
Embodiment two
The embodiment of the present invention two discloses the preparation method of the igbt chip as described in embodiment one, including following operation
Step:
Field oxygen zone 3 is covered in the partial region of substrate 17；
Silicon layer 23 is formed in field oxygen zone 3；
Diode p type island region 231 and diode N-type region 232 are formed on silicon layer 23；
The first electrode 21 being electrically coupled with diode p type island region 231 is drawn, the be electrically coupled with diode N-type region 232 is drawn
Two electrodes 22；
Prior to, concurrently with, or after above-mentioned steps, insulated gate bipolar transistor area 1 is formed on the substrate 17.
As described above, the preparation method of the igbt chip diode region 2 for being used for temperature sense is integrated in it is described
Igbt chip is protected not to be damaged by heat for improving the speed and accuracy of temperature sense in 17 surface of substrate of igbt chip.
In different embodiments of the invention, the diode region 2 and the insulated gate bipolar transistor area 1 can separate
It is separately machined, it can also simultaneous processing.
In some embodiments of the invention, in order to preferably guarantee that diode region 2 and insulated gate electrode are double on igbt chip
Consistency between polar crystal area under control 1 is finely adjusted temperature-sensitive curve with facilitating, and diode region 2 and insulated gate bipolar is brilliant
Body area under control 1 carries out machine-shaping simultaneously, and the following are specific operation process:
" the covering field oxygen zone 3 in the partial region of substrate 17 " includes:
Layer of silicon dioxide layer is grown with the method for thermal oxide or chemical vapor deposition on substrate 17, then passes through photoetching
Silicon dioxide layer redundance is removed with the method for etching, forms field oxygen zone 3.The thermal oxide is by the condition in high temperature
Under, using the oxidation reaction between silicon and oxidant, silicon dioxide layer is formed on silicon substrate 17.It should be noted that described
The formation of field oxygen zone 3 can also be physical vapour deposition (PVD) and anodic oxidation etc..
After described " covering field oxygen zone 3 in the partial region of substrate 17 " further include: use the side of thermal oxide on substrate 17
Surface of the method on substrate 17 in addition to field oxygen zone 3 grows the grid oxygen area 14 of layer of silicon dioxide.In other embodiments, described
The generation type in grid oxygen area 14 can also be chemical vapor deposition, physical vapour deposition (PVD) and anodic oxidation etc..
In other embodiments, since the field oxygen zone 3 is similar with the preparation method in the grid oxygen area 14, therefore the field oxygen
Area 3 and grid oxygen area 14, which can separate, to be formed, and can also be formed simultaneously.
In the present embodiment, the gate electrode of the silicon layer 23 of the diode region 2 and the insulated gate bipolar transistor area 1
13 be polysilicon, can be by the processing stream of the silicon layer 23 and the gate electrode 13 to guarantee consistency and reducing processing flow
Journey merges, specifically: it is described " one layer of polysilicon to be deposited in field oxygen zone 3 by way of chemical vapor deposition, to polysilicon portion
The silicon layer 23 " for dividing removal to obtain being located in field oxygen zone 3 includes: by way of chemical vapor deposition in grid oxygen area 14 and field oxygen zone
3 surface deposits one layer of polysilicon, removes the predetermined portions pattern of polysilicon, by way of photoetching and dry etching then to obtain
Silicon layer 23 in the field oxygen zone 3 and the gate electrode 13 in grid oxygen area 14, by the silicon layer 23 and the gate electrode
Polysilicon between 13 is removed by dry etching, completely cuts off the silicon layer 23 and the gate electrode 13 mutually, in the gate electrode 13
On be formed with the opening 131 for being connected to 17 surface of substrate, the opening 131 sequentially passes through the gate electrode 13 and the grid
Oxygen area 14 exposes 17 part of substrate.
The photoetching and dry etching are common lithographic method, and photoetching mainly includes silicon wafer surface cleaning drying, linging, spin coating
Photoresist, it is soft dry, alignment exposure, it is rear dry, development, it is hard dry, etching and detection process, to form photomask pattern, dry etching be
It is etched on the photomask pattern being lithographically formed, to obtain three-dimensional etch structures.
" diode p type island region 231 and diode N-type region 232 are formed on silicon layer 23 " includes:
Diode p type island region 231 and diode N-type region 232 are formed on silicon layer 23 by way of photoetching and ion implanting,
In the position that the substrate 17 exposes at the opening 131, p-well region 162 is formed by way of photoetching and ion implanting, is led to
Cross the mode of photoetching and ion implanting and form the injection region P+ 161 in the center of the p-well region 162, then by photoetching and from
The mode of son injection forms N+ emitter region 15 between the p-well region 162 and the injection region P+ 161.
Photomask pattern is formed by way of photoetching, then photomask pattern expose position carry out ion implanting and
Diffusion, to form P-type silicon or N-type silicon.
The injection ion of the p-well region 162, the injection region P+ 161 and the diode p type island region 231 is boron ion, institute
The implantation dosage for stating p-well region 162 is 1E13~9E14 ion/cm2, the implantation dosage of the injection region P+ 161 be 1E14~
1E16 ion/cm2, 231 dosage of diode p type island region is 1E13~1E16 ion/cm2；The N+ emitter region 15 and described two
The injection ion of pole pipe N-type region 232 be arsenic ion or phosphonium ion, 15 implantation dosage of N+ emitter region be 1E14~1E16 from
Son/cm2, 232 implantation dosage of diode N-type region is 5E14~1E16 ion/cm2。
It should be noted that in other embodiments, the p-well region 162, the injection region P+ 161 and the diode P
The injection ion in type area 231 can also be to form other ions of P-type silicon, such as aluminium ion, the N+ emitter region 15 and described
The injection ion of diode N-type region 232 is also possible to form other ions of N-type silicon, such as antimony ion, those skilled in the art
It can be selected as needed.
It is described " to draw the first electrode 21 being electrically coupled with diode p type island region 231, draw and 232 thermocouple of diode N-type region
The second electrode 22 " of conjunction includes:
The outside deposition insulating medium layer 12 of gate electrode 13 and silicon layer 23, the insulation are formed on the substrate 17
Dielectric layer 12 is covered in the outer surface of the gate electrode 13 and silicon layer 23, while being deposited on the gate electrode 13 and the silicon layer 23
Between gap neutralize in the opening 131, and in the surface shape of the insulating medium layer 12 by way of photoetching and etching
At the first intercommunicating pore having for being connected to the injection region P+ 161 and the N+ emitter region 15, for being connected to the diode p-type
Second intercommunicating pore in area 231, and the third connecting hole for being connected to the diode N-type region 232；The first connection hole location
In 131 positions of the opening.
The deposited metal layer on insulating medium layer 12, the metal layer pass through first intercommunicating pore and the injection region P+
161 and the N+ emitter region 15 connection, the metal layer connect with the diode p type island region 231 by second intercommunicating pore,
The metal layer is connect by described and third connecting hole with the diode N-type region 232；It is formed by photoetching and etching predetermined
Emitter 11, first electrode 21 and the second electrode 22 of pattern, the emitter 11 pass through the first connection through-hole 121 and institute
It states the injection region P+ 161 and the N+ emitter region 15 is electrically coupled；The first electrode 21 passes through the second connection through-hole 122 and institute
Diode p type island region 231 is stated to be electrically coupled；The second electrode 22 passes through third connection through-hole 123 and the diode N-type region
232 are electrically coupled.
In the present embodiment, described " to draw the first electrode 21 being electrically coupled with diode p type island region 231, extraction and diode
After the second electrode 22 " that N-type region 232 is electrically coupled further include:
The thinning back side that substrate 17 is deviated to the polysilicon carries out ion implanting on the back side of substrate 17 and forms current collection
Polar region 18, so that the collector area 18 has the first conduction type characteristic, the substrate 17 has the second conduction type characteristic,
Collector 19 is formed by the method for evaporation or sputtering on the surface of the collector area 18.
Embodiment three
The embodiment of the present invention three discloses a kind of preparation method of igbt chip, including most of operation such as embodiment two
Step, the difference is that:
The preparation method of collector area 18 described in the present embodiment and the substrate 17 is different from embodiment two.
Specifically, in the preparation method of the igbt chip, it is described " covering field oxygen zone 3 in the partial region of substrate 17 "
Before further include:
Using the highly doped silicon with the first conduction type characteristic as collector area 18, in the highly doped of collector area 18
Surface carries out growth and is epitaxially formed the substrate 17 with the second conduction type characteristic, deviates from the substrate in the collector area 18
17 surface forms collector 19 by the method for evaporation or sputtering.
The foregoing is merely illustrative of the preferred embodiments of the present invention, is not intended to limit the invention, all in essence of the invention
Made any modifications, equivalent replacements, and improvements etc., should all be included in the protection scope of the present invention within mind and principle.
Claims (15)
1. a kind of igbt chip, which is characterized in that including the insulated gate bipolar transistor area for conducting control and be used for
Incude the diode region of the temperature in the insulated gate bipolar transistor area；
The diode region includes silicon layer, first electrode and second electrode, and diode p type island region and two poles are formed on the silicon layer
Pipe N-type region, the first electrode are electrically coupled with the diode p type island region, the second electrode and the diode N-type region thermocouple
It closes；
The insulated gate bipolar transistor area has substrate, and the partial region of the substrate is covered with field oxygen zone, the silicon layer
It is formed in the field oxygen zone, so that the diode region and insulated gate bipolar transistor area mutually insulated are thermally conductive.
2. igbt chip according to claim 1, which is characterized in that the silicon layer is polysilicon layer.
3. igbt chip according to claim 1, which is characterized in that the insulated gate bipolar transistor area further includes collection
Electrode, collector area, p type island region, N+ emitter region, grid oxygen area, gate electrode and emitter, the collector area are formed in the substrate
Surface, and the collector area has the first conduction type characteristic, the substrate has the second conduction type characteristic, the current collection
Pole is electrically coupled with the collector area, and the p type island region is formed on the substrate, and the N+ emitter region and the substrate pass through institute
P type island region isolation is stated, and the p type island region is separately connected the emitter and the grid oxygen area, the gate electrode is located at the grid oxygen
Deviate from the one side of the p type island region in area, the N+ emitter region is electrically coupled with the emitter.
4. igbt chip according to claim 3, which is characterized in that the field oxygen zone is formed on the substrate away from institute
State the surface of collector area.
5. igbt chip according to claim 3, which is characterized in that the p type island region is located on the substrate away from described
The side of collector area, and the p type island region is embedded in the surface of the substrate, the p type island region include p-well region and the injection region P+,
The injection region P+ is formed in the middle part of the p-well region, the N+ emitter region be surrounded on the injection region P+ outer rim and the P
Between well region, the injection region P+ connects the emitter, and the p-well region connects the grid oxygen area.
6. igbt chip according to claim 5, which is characterized in that the igbt chip further includes insulating medium layer, institute
The outer surface that insulating medium layer is covered in the gate electrode and the silicon layer is stated, and is passed through between the gate electrode and the silicon layer
The insulating medium layer mutually completely cuts off；It is formed on the insulating medium layer for being connected to the injection region P+ and N+ transmitting
First intercommunicating pore in area, for being connected to the second intercommunicating pore of the diode p type island region and for being connected to the diode N-type region
Third connecting hole；The emitter passes through the first connection through-hole and the injection region P+ and the N+ emitter region thermocouple
It closes；The first electrode passes through the second connection through-hole and is electrically coupled with the diode p type island region；The second electrode passes through institute
Third connection through-hole is stated to be electrically coupled with the diode N-type region.
7. igbt chip according to claim 6, which is characterized in that the insulating medium layer is Si3N4+ USG+BPSG or
USG+BPSG, the insulating medium layer with a thickness of 0.5um~3um.
8. the preparation method of the igbt chip as described in claim 1~7 any one characterized by comprising
Field oxygen zone is covered in the partial region of substrate；
Silicon layer is formed in field oxygen zone；
Diode p type island region and diode N-type region are formed on silicon layer；
The first electrode being electrically coupled with diode p type island region is drawn, the second electrode being electrically coupled with diode N-type region is drawn；
Prior to, concurrently with, or after above-mentioned steps, insulated gate bipolar transistor area is formed over the substrate.
9. the preparation method of igbt chip according to claim 8, which is characterized in that described " in the partial region of substrate
Cover field oxygen zone " include:
Layer of silicon dioxide layer is grown with the method for thermal oxide or chemical vapor deposition on substrate, then passes through photoetching and etching
Method remove silicon dioxide layer redundance, formed field oxygen zone.
10. the preparation method of igbt chip according to claim 8 or claim 9, which is characterized in that described " in the part of substrate
After region overlay field oxygen zone " further include: with the method for thermal oxide, the surface in addition to field oxygen zone is grown on substrate on substrate
The grid oxygen area of layer of silicon dioxide out；
" silicon layer is formed in field oxygen zone " includes: the surface by way of chemical vapor deposition in grid oxygen area and field oxygen zone
One layer of polysilicon is deposited, the predetermined portions pattern of polysilicon is then removed by way of photoetching and dry etching, to obtain being located at institute
The silicon layer in field oxygen zone and the gate electrode in grid oxygen area are stated, the silicon layer and the gate electrode mutually completely cut off, in the grid
It is formed with the opening for being connected to the substrate surface on electrode, exposes substrate portions.
11. the preparation method of igbt chip according to claim 10, which is characterized in that described " to form two on silicon layer
Pole pipe p type island region and diode N-type region " include:
Diode p type island region and diode N-type region are formed on silicon layer by way of photoetching and ion implanting, is existed in the substrate
The position that the opening is exposed, forms p-well region by way of photoetching and ion implanting, passes through the side of photoetching and ion implanting
Formula forms the injection region P+ in the center of the p-well region, then in the p-well region and institute by way of photoetching and ion implanting
State formation N+ emitter region between the injection region P+.
12. the preparation method of igbt chip according to claim 11, which is characterized in that the p-well region, P+ injection
The injection ion of area and the diode p type island region is boron ion, the implantation dosage of the p-well region be 1E13~9E14 ion/
cm2, the implantation dosage of the injection region P+ is 1E14~1E16 ion/cm2, diode p type island region dosage is 1E13~1E16
Ion/cm2；The injection ion of the N+ emitter region and the diode N-type region is arsenic ion or phosphonium ion, the N+ emitter region
Implantation dosage is 1E14~1E16 ion/cm2, the diode N-type region implantation dosage is 5E14~1E16 ion/cm2。
13. the preparation method of igbt chip according to claim 11, which is characterized in that described " to draw and diode p-type
The first electrode that area is electrically coupled draws the second electrode being electrically coupled with diode N-type region " include:
It is formed with the outside deposition insulating medium layer of gate electrode and silicon layer over the substrate, and passes through the side of photoetching and etching
Formula is formed with the first intercommunicating pore for being connected to the injection region P+ and the N+ emitter region on the surface of the insulating medium layer,
For being connected to the second intercommunicating pore of the diode p type island region, and the third connecting hole for being connected to the diode N-type region；
The deposited metal layer on insulating medium layer, the metal layer pass through first intercommunicating pore and the injection region P+ and described
The connection of N+ emitter region, the metal layer are connect by second intercommunicating pore with the diode p type island region, and the metal layer passes through
Described and third connecting hole is connect with the diode N-type region；The emitter of predetermined pattern, first are formed by photoetching and etching
Electrode and second electrode, the emitter pass through the first connection through-hole and the injection region P+ and the N+ emitter region thermocouple
It closes；The first electrode passes through the second connection through-hole and is electrically coupled with the diode p type island region；The second electrode passes through institute
Third connection through-hole is stated to be electrically coupled with the diode N-type region.
14. the preparation method of igbt chip according to claim 8, which is characterized in that described " to draw and diode p-type
The first electrode that area is electrically coupled draws the second electrode being electrically coupled with diode N-type region " after further include:
The thinning back side that substrate is deviated to the polysilicon carries out ion implanting on the back side of substrate and forms collector area, makes
Obtaining the collector area has the first conduction type characteristic, and the substrate has the second conduction type characteristic, in the collector
The surface in area forms collector by the method for evaporation or sputtering.
15. the preparation method of igbt chip according to claim 8, which is characterized in that described " in the partial region of substrate
Cover field oxygen zone " before further include:
Using the highly doped silicon with the first conduction type characteristic as collector area, carried out on the highly doped surface of collector area
Growth is epitaxially formed the substrate with the second conduction type characteristic, passes through steaming away from the surface of the substrate in the collector area
Hair or the method for sputtering form collector.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110620041A (en) * | 2019-09-25 | 2019-12-27 | 上海华虹宏力半导体制造有限公司 | Method for integrating temperature sensor on IGBT chip |
| CN115084051A (en) * | 2022-05-11 | 2022-09-20 | 上海华虹宏力半导体制造有限公司 | Method for integrating temperature sensor polycrystalline silicon layer on IGBT chip |
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Application publication date: 20190507 |