CN109860274A - A kind of VDMOS device and preparation method thereof - Google Patents
A kind of VDMOS device and preparation method thereof Download PDFInfo
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Abstract
The present invention relates to a kind of VDMOS devices and preparation method thereof, which comprises the substrate of the first conduction type is provided, in the first epitaxial layer of one conduction type of substrate surface growth regulation；Groove is formed in first epi-layer surface；The first separation layer is formed in the flute surfaces and first epitaxial layer upper surface；The first polysilicon layer is formed in the first insulation surface of the flute surfaces；The second separation layer is formed on the surface of the first polysilicon layer of the bottom of the groove；The second epitaxial layer of spaced multiple first conduction types and the third epitaxial layer of the second conduction type are formed on second separation layer, the groove to be filled up, wherein, the bottom end of second epitaxial layer and the third epitaxial layer is connect with second separation layer, and the first polysilicon layer at the trenched side-wall is connect with one second epitaxial layer.
Description
Technical field
The present invention relates to technical field of semiconductors, specifically a kind of VDMOS device and preparation method thereof.
Background technique
VDMOS(vertical double-deffused metal oxide semiconductor field effect
Transistor, vertical bilateral diffusion field-effect tranisistor) drain-source the two poles of the earth of device respectively in the two sides of device, make electric current in device
Internal vertical circulation, increases current density, improves rated current, the conducting resistance of unit area is also smaller, is a kind of use
Very extensive power device on the way.The gate controller part channel of VDMOS device is opened, the high pressure resistant energy of the oxide layer of gate location
Power is poor (usually < 100V), is highly prone to transient voltage surge destruction, leads to component failure, therefore logical in the grid of VDMOS device
Often need to increase electrostatic protection structure to avoid transient voltage surge from causing the destruction to device, however existing electrostatic protection knot
It is configured to the increase of device area, and then increases packaging cost, is unfavorable for the reliability of product.
Summary of the invention
The embodiment of the invention provides a kind of production methods of VOMOS device, can mention under the premise of not increasing area
The power of high device.
In a first aspect, the embodiment of the invention provides a kind of production methods of VOMOS device, which comprises provide
The substrate of first conduction type, in the first epitaxial layer of one conduction type of substrate surface growth regulation；In first extension
Layer surface forms groove；The first separation layer is formed in the flute surfaces and first epitaxial layer upper surface；In the groove
First insulation surface on surface forms the first polysilicon layer；It is formed on the surface of the first polysilicon layer of the bottom of the groove
Second separation layer；The second epitaxial layer and second of spaced multiple first conduction types is formed on second separation layer
The third epitaxial layer of conduction type, the groove is filled up, wherein the bottom of second epitaxial layer and the third epitaxial layer
End is connect with second separation layer, and the first polysilicon layer at the trenched side-wall is connect with one second epitaxial layer；
The second epitaxial layer of part and part third epitaxial layer of the top of the groove are removed, to expose the portion for being located at the trenched side-wall
Divide the first polysilicon layer；Side wall is formed on part the first polysilicon layer surface exposed；In second epitaxial layer and third
The fourth epitaxial layer is grown on epitaxial layer, the groove is filled up, outside the bottom surface of the fourth epitaxial layer and described second
Prolong layer and the connection of third epitaxial layer.
Second aspect, the embodiment of the present invention provide a kind of VDMOS device, and the VDMOS device includes: to provide the first conduction
The substrate of type, in the first epitaxial layer of one conduction type of substrate surface growth regulation；In the first epi-layer surface shape
At groove；The first separation layer is formed in the flute surfaces and first epitaxial layer upper surface；The of the flute surfaces
One insulation surface forms the first polysilicon layer；The second isolation is formed on the surface of the first polysilicon layer of the bottom of the groove
Layer；The second epitaxial layer and the second conduction type of spaced multiple first conduction types are formed on second separation layer
Third epitaxial layer, the groove is filled up, wherein the bottom end of second epitaxial layer and the third epitaxial layer is and institute
The connection of the second separation layer is stated, the first polysilicon layer at the trenched side-wall is connect with one second epitaxial layer；Described in removal
The second epitaxial layer of part and part third epitaxial layer of the top of the groove, to expose the part more than first for being located at the trenched side-wall
Crystal silicon layer；Side wall is formed on part the first polysilicon layer surface exposed；On second epitaxial layer and third epitaxial layer
The fourth epitaxial layer is grown, the groove is filled up, the bottom surface of the fourth epitaxial layer and second epitaxial layer and the
The connection of three epitaxial layers.
It is appreciated that the VDMOS device that the present invention is formed by the above method, avoids Conventional power devices needs
Method by encapsulating with protecting device to connect, reduces device area, reduces encapsulation manufacturing cost, it is reliable to improve product
Property.The electrostatic protection structure of second epitaxial layer and third the epitaxial layer composition formed is formed by using extensional mode, into
And reduce leakage current, further improve the reliability of VDMOS device provided by the invention.
Detailed description of the invention
In order to illustrate the technical solution of the embodiments of the present invention more clearly, below to needed in embodiment description
Attached drawing is briefly described, it should be apparent that, drawings in the following description are some embodiments of the invention, general for this field
For logical technical staff, without creative efforts, it is also possible to obtain other drawings based on these drawings.
It constitutes a part of attached drawing of the invention to be used to provide further understanding of the present invention, schematic implementation of the invention
Example and its specification are used to explain the present invention, and do not constitute the improper restriction to not allowing you to invent.
Fig. 1 is the flow diagram of the method for the production VDMOS device that the embodiment of the present invention proposes；
Fig. 2 is the structural schematic diagram for the VDMOS device that the embodiment of the present invention proposes；
Fig. 3 to Figure 16 is the schematic diagram of the section structure of the method for the production VDMOS device that the embodiment of the present invention proposes；
Description of symbols: 1, substrate；2, the first epitaxial layer；3, groove；4, the first separation layer；5, the first polysilicon layer；
6, the second separation layer；7, the second epitaxial layer；8, third epitaxial layer；9, side wall；10, fourth epitaxial layer；11, dielectric layer；12, positive
Metal layer；13, metal layer on back.
Specific embodiment
It is clear in order to be more clear the purpose of the present invention, technical solution and advantageous effects, below in conjunction with this hair
Attached drawing in bright embodiment, technical scheme in the embodiment of the invention is clearly and completely described, it is clear that described
Embodiment is only a part of the embodiment of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, this field
Those of ordinary skill's every other embodiment obtained without making creative work, belongs to protection of the present invention
Range.
In the description of the present invention, it should be noted that term " center ", "upper", "lower", "left", "right", "vertical",
The orientation or positional relationship of the instructions such as "horizontal", "inner", "outside" is to be based on the orientation or positional relationship shown in the drawings, or be somebody's turn to do
Invention product using when the orientation or positional relationship usually put, be merely for convenience of description of the present invention and simplification of the description, without
It is that the device of indication or suggestion meaning or element must have a particular orientation, be constructed and operated in a specific orientation, therefore not
It can be interpreted as limitation of the present invention.In addition, term " first ", " second ", " third " etc. are only used for distinguishing description, and cannot manage
Solution is indication or suggestion relative importance.
It should be appreciated that being known as being located at another floor, another area when by a floor, a region in the structure of outlines device
When domain " above " or " top ", can refer to above another layer, another region, or its with another layer, it is another
Also comprising other layers or region between a region.Also, if device overturn, this layer, a region will be located at it is another
Layer, another region " following " or " lower section ".
If will use that " A is directly on B herein to describe located immediately at another layer, another region above scenario
The expression method of face " or " A on B and therewith abut ".In this application, " A is in B " indicates that A is located in B, and
And A and B is abutted directly against, rather than A is located in the doped region formed in B.
In this application, term " semiconductor structure " refers to entire half formed in each step of manufacturing semiconductor devices
The general designation of conductor structure, including all layers formed or region.
Many specific details of the invention, such as structure, material, the size, processing side of device are described hereinafter
Method and technology, to be more clearly understood that the present invention.But it just as the skilled person will understand, can not press
The present invention is realized according to these specific details.
Referring to Fig. 1, Fig. 1 is the flow diagram of the method for the production triode that the embodiment of the present invention proposes, the present invention
A kind of production method of triode is provided, comprising:
Step S01: the substrate of the first conduction type is provided, outside the first of one conduction type of substrate surface growth regulation
Prolong layer；
Step S02: groove is formed in first epi-layer surface；
Step S03: the first separation layer is formed in the flute surfaces and first epitaxial layer upper surface；
Step S04: the first polysilicon layer is formed in the first insulation surface of the flute surfaces；
Step S05: the second separation layer is formed on the surface of the first polysilicon layer of the bottom of the groove；
Step S06: the second epitaxial layer of spaced multiple first conduction types is formed on second separation layer
And second conduction type third epitaxial layer, the groove is filled up, wherein second epitaxial layer and the third extension
The bottom end of layer is connect with second separation layer, the first polysilicon layer and one second epitaxial layer at the trenched side-wall
Connection；
Step S07: the second epitaxial layer of part and part third epitaxial layer of the top of the groove are removed, is located at exposing
The first polysilicon layer of part of the trenched side-wall；
Step S08: side wall is formed on part the first polysilicon layer surface exposed；
Step S09: the fourth epitaxial layer is grown on second epitaxial layer and third epitaxial layer, by the groove
It fills up, the bottom surface of the fourth epitaxial layer is connect with second epitaxial layer and third epitaxial layer.
It is appreciated that the VDMOS device that the present invention is formed by the above method, avoids Conventional power devices needs
Method by encapsulating with protecting device to connect, reduces device area, reduces encapsulation manufacturing cost, it is reliable to improve product
Property.The electrostatic protection structure of second epitaxial layer and third the epitaxial layer composition formed is formed by using extensional mode, into
And reduce leakage current, further improve the reliability of VDMOS device provided by the invention.
With reference to the accompanying drawings, the method for the above-mentioned formation transistor is elaborated.
For convenience of subsequent description, special to illustrate herein: technical solution of the present invention is related to designing and manufacturing for semiconductor devices,
Semiconductor refers to that a kind of electric conductivity can be controlled, conductive extensions can from insulator to the material changed between conductor, common half
Conductor material has silicon, germanium, GaAs etc., and silicon be in various semiconductor materials it is most powerful, be most widely used one
Kind.Semiconductor is divided into intrinsic semiconductor, P-type semiconductor and N-type semiconductor, and free from foreign meter and without lattice defect semiconductor is known as
Intrinsic semiconductor mixes triad (such as boron, indium, gallium) in pure silicon crystal, is allowed to replace silicon atom in lattice
Seat just forms P-type semiconductor, mixes pentad (such as phosphorus, arsenic) in pure silicon crystal, is allowed to replace silicon in lattice
The position of atom is formed N-type semiconductor, and P-type semiconductor is different with the conduction type of N-type semiconductor, in reality of the invention
It applies in example, the first conduction type is N-type, and the second conduction type is p-type, in an embodiment of the present invention, if without especially saying
Bright, the preferred Doped ions of every kind of conduction type are all that can be changed to the ion with same conductivity type.
Attached drawing 3 is please referred to, step S01 is executed: the substrate 1 of the first conduction type is provided, in the 1 surface growth regulation of substrate
First epitaxial layer 2 of one conduction type；Specifically, carrier of the substrate 1 as the device, primarily serves the work of support
With.Under normal circumstances, the material of the substrate 1 can have silicon substrate, silicon carbide substrates, silicon nitrate substrate etc., in this embodiment party
In formula, the substrate 1 is silicon substrate, and silicon is most common, cheap and stable performance semiconductor material.In some realities of the invention
It applies in mode, the substrate 1 is N-type substrate, and 1 resistivity of substrate is 0.001~0.005 Ω * cm, with a thickness of 250~350
μm, in the present embodiment, the Doped ions of the substrate 1 are specially phosphonium ion, certainly, in other embodiments, described
The Doped ions of substrate 1 can be also other pentavalent ions such as arsenic or antimony.In an embodiment of the present invention, the substrate 1 is as this
Invent the collector contact area of the triode proposed.The thickness of first epitaxial layer 2 and the close phase of pressure resistance of concentration and device
It closes, in some embodiments of the invention, 2 resistivity of the first epitaxial layer is 45~60 Ω * cm, and thickness is at 15~18 μm
Between.Preferably, first epitaxial layer 2 is formed by the relatively simple homoepitaxy of technique, i.e., described first epitaxial layer 2
Material is identical as the material of the substrate 1, and when the material of substrate 1 is silicon, the material of first epitaxial layer 2 is also silicon.Institute
State the upper surface that the first epitaxial layer 2 can be formed in the substrate 1 using epitaxial growth method.The doping of first epitaxial layer 2
Type is identical as the doping type of the substrate 1, and in the present embodiment, the substrate 1 is n-type doping, first extension
Layer 2 is n-type doping, and in other embodiments, if the substrate 1 is p-type doping, first epitaxial layer 2 is p-type doping.
In the present embodiment, the Doped ions of first epitaxial layer 2 are specially phosphonium ion, in other embodiments, described
The Doped ions of one epitaxial layer 2 can be also other pentavalent ions such as arsenic or antimony.More specifically, the epitaxial growth method can be gas
Phase epitaxy growth method, liquid phase epitaxial process, vacuum evaporation growth method, high-frequency sputtering growth method, molecular beam epitaxial growth method etc.,
Preferably chemical vapor deposition method (or vapor phase epitaxial growth), chemical vapor deposition method are a kind of former with vapor reaction
Material reacts and deposits into the technique of solid thin layer or film on solid matrix surface, is a kind of extension of the transistor of comparative maturity
Growth method, this method spray silicon and doped chemical on the substrate 1, and uniformity is reproducible, and step coverage is excellent
It is good.The perfection of silicon materials can be improved in chemical vapor deposition method simultaneously, improves the integrated level of device, reaches raising few sub- longevity
Life, reduces the leakage current of storage element.
Attached drawing 4 is please referred to, step S02 is executed: forming groove 3 on 2 surface of the first epitaxial layer；Form the groove 3
Process can be with are as follows: form etching barrier layer on first epitaxial layer 2, then formed in etching barrier layer (not shown)
Photoresist layer (not shown) is later exposed the photoresist layer using the mask plate with 3 figure of groove, then into
Row development, obtains the photoresist layer with 3 figure of groove.Using the photoresist layer with 3 figure of groove as exposure mask, adopt
With lithographic methods such as reactive ion etching methods, etching forms the figure opening (not shown) of the groove 3 on etching barrier layer.
Then it using the etching barrier layer being open with 3 figure of groove as exposure mask, using the methods of wet etching or dry etching, goes
Except first epitaxial layer 2 for the barrier layer covering that is not etched, the groove 3 is formed in first epitaxial layer 2.Hereafter may be used
Photoresist layer and etching barrier layer are removed using the methods of chemical cleaning.In above process, in order to guarantee exposure accuracy, may be used also
Anti-reflecting layer (not shown) is formed between photoresist layer and etching barrier layer.
It please refers to attached drawing 5, executes step S03: forming the on 3 surface of groove and 2 upper surface of the first epitaxial layer
One separation layer 4.Specifically, the material of first separation layer 4 can be silica, silicon nitride, aluminium oxide and silicon oxynitride
Etc. one of or any a variety of combination, in the present embodiment, material is silica.First separation layer 4 can be with
It is formed in the surface of first epitaxial layer 2 and the groove 3 by depositing technics, can also be formed by thermal oxidation technology；
In the present embodiment, first separation layer 4 is formed by thermal oxidation technology, and the thermal oxidation technology is those skilled in the art
The conventional technical means of member, is no longer described in detail herein.
Attached drawing 6 and Fig. 7 are please referred to, step S04 is executed: forming first on 4 surface of the first separation layer on 3 surface of groove
Polysilicon layer 5；Further, the first polysilicon layer 5 is formed on 4 surface of the first separation layer on 3 surface of groove to specifically include:
Polysilicon 5a is filled in the groove 3；Polysilicon 5a described in dry etching forms first polysilicon layer 5.Wherein, institute
Stating dry etching includes photoablation, gaseous corrosion, plasma etching etc., and dry etching has easily realization automation, processing
Process is not introduced into the high advantage of pollution, cleannes.Thickness of first polysilicon layer 5 on 3 bottom of groove and side wall
It can be the same or different, preferably identical, thickness of first polysilicon layer 5 on 3 bottom of groove and side wall is equal
Greater than 3000A.
It please refers to attached drawing 8, executes step S05: forming the on the surface of the first polysilicon layer 5 of the bottom of the groove 3
Two separation layers 6；The material of second separation layer 6 can be silica, silicon nitride, aluminium oxide and silicon oxynitride etc. wherein one
Kind or any a variety of combination, in the present embodiment, material is silica.For silica, silicon nitride, aluminium oxide and nitrogen
One of or arbitrarily a variety of combination such as silica, in the present embodiment, material are silica.Second separation layer
6 can be formed in the surface of first epitaxial layer 2 and the groove 3 by depositing technics, can also pass through thermal oxidation technology
It is formed；In the present embodiment, second separation layer 6 is formed by depositing technics, and depositing technics is a kind of important technique,
Two main directions of physical vapor deposition and chemical vapor deposition are had developed at present.The deposition technology of metal is usually physics
Property, belong to physical vapor deposition, and the depositing technics of semiconductor layer and insulating layer generally falls into chemical vapor deposition.At this
In embodiment, second separation layer 6 is formed using CVD method, and chemical vapor deposition method is a kind of to use gaseous state
Reaction raw materials react and deposit into the technique of solid thin layer or film on solid matrix surface, are that a kind of extension of comparative maturity is raw
Regular way.
Attached drawing 9,10,11,12 and 13 is please referred to, step S06 is executed: being formed and be alternatively arranged on second separation layer 6
Multiple first conduction types the second epitaxial layer 7 and the second conduction type third epitaxial layer 8, the groove 3 is filled up,
Wherein, the bottom end of second epitaxial layer 7 and the third epitaxial layer 8 is connect with second separation layer 6, is located at the ditch
First polysilicon layer 5 of 3 side-walls of slot is connect with one second epitaxial layer 7.It should be noted that second epitaxial layer 7 and institute
It states third epitaxial layer 8 to arrange in the horizontal direction, when vertical view, second epitaxial layer 7 is cyclic annular knot with the third epitaxial layer 8
Structure, in the present embodiment, the quantity of second epitaxial layer 7 are 2, and the quantity of the third epitaxial layer 8 is 1, wherein first
A second epitaxial layer 7 is located at the periphery of the third epitaxial layer 8, and the third epitaxial layer 8 is located at second described second
The periphery of epitaxial layer 7, first polysilicon layer 5 is located at the periphery of first second epitaxial layer 7, in other modes,
The quantity of second epitaxial layer 7 and the third epitaxial layer 8 can change according to the requirement of device.More specifically, described
The third extension of second epitaxial layer 7 of spaced multiple first conduction types and the second conduction type on second separation layer 6
Layer 8 specifically includes: the epitaxial layer of the first conduction type is filled in the groove 3；Etch the extension of first conduction type
Layer, retains the epitaxial layer of the first conduction type of 3 side wall of groove, the epitaxial layer of first conduction type retained is
Second epitaxial layer 7；The epitaxial layer of the second conduction type is filled in the remaining area of the groove 3；Described second is etched to lead
The epitaxial layer of electric type retains the epitaxial layer of 3 second conduction type of side wall of groove, second conduction type retained
Epitaxial layer be the third epitaxial layer 8.The extension of the first conduction type is continued to fill up in the remaining area of the groove 3
Layer, to form second epitaxial layer 7.
Attached drawing 14 is please referred to, step S07 is executed: removing second epitaxial layer of part 7 and part third at 3 top of groove
Epitaxial layer 8, to expose the first polysilicon layer of part 5 for being located at 3 side wall of groove；It is appreciated that the removal groove 3 pushes up
After second epitaxial layer of part 7 and the third epitaxial layer 8 in portion, the upper end of second epitaxial layer 7 and the third epitaxial layer 8
The level height in face where the level height in face is open lower than the groove 3.It is appreciated that of the invention is several spaced
Second epitaxial layer 7 and third epitaxial layer 8 form electrostatic protection structure, and the electrostatic protection structure is by using extensional mode shape
At leakage current is small.
Please continue to refer to attached drawing 14, step S08 is executed: forming side wall on 5 surface of the first polysilicon layer of part exposed
9；The thickness of the side wall 9 is determined according to the requirement of device, generally 2000-5000A, and the material of the side wall 9 can be oxygen
One of or arbitrarily a variety of combination such as SiClx, silicon nitride, aluminium oxide and silicon oxynitride, in the present embodiment, material
Matter is silica.For silica, silicon nitride, aluminium oxide and silicon oxynitride etc. be one of or any a variety of combination, at this
In embodiment, material is silica.The side wall 9 can be formed in 5 table of the first polysilicon layer by depositing technics
Face can also be formed in the surface of first polysilicon layer 5 by thermal oxidation technology；The thermal oxidation technology and the deposit
Technique is the conventional techniques of those skilled in the art, and this is no longer going to repeat them.Further, the side wall 9 is being formed
While, also first polysilicon layer 5 upper surface formed third separation layer, the third separation layer by described first every
Absciss layer 4 links together with the side wall 9, and the material of the third separation layer is identical as the side wall 9, the third separation layer
It is formed simultaneously with the side wall 9.
Further, after the second epitaxial layer of part 7 and part third epitaxial layer 8 that remove 3 top of groove, sudden and violent
5 surface of the first polysilicon layer of part of exposing is formed before side wall 9, the method also includes: first time annealing process is carried out, is moved back
Fiery temperature is 900 DEG C, and annealing time is 30 seconds；Second of annealing process is carried out, annealing temperature is 980 DEG C, annealing time 20
Second；It is cleaned using the ammonium hydroxide that concentration is 20% to structure is formed by.Wherein, first time thermal anneal process and the are being carried out
During secondary thermal anneal process, heating rate is greater than 80 DEG C/s, and rate of temperature fall is greater than 60 DEG C/s, which can eliminate table
Planar defect is improved surface quality and subsequent epitaxy technique is facilitated to carry out, cleaned, gone using 20% ammonium hydroxide after the completion of injection
Except movable charge.
Attached drawing 15 is please referred to, step S09 is executed: growing the described 4th on second epitaxial layer 7 and third epitaxial layer 8
Epitaxial layer 10 fills up the groove 3, the bottom surface of the fourth epitaxial layer 10 and second epitaxial layer 7 and third extension
Layer 8 connects；Wherein, the fourth epitaxial layer 10 is intrinsic epitaxial layer, and the intrinsic epitaxial layer is formed by epitaxy technique
It is entirely free of impurity and the pure semiconductor layer without lattice defect.But practical semiconductor cannot be absolute pure, this based semiconductor
Referred to as extrinsic semiconductor, main common representative have the monoclinic crystal structure of silicon, germanium both elements.It is appreciated that increasing under the gate
Add the fourth epitaxial layer 10 that can reduce parasitic capacitance, improves the switching speed of chip, and then promote the VDMOS device
Reliability.
Further, attached drawing 15 is please referred to, the method also includes: in 2 region of the first epitaxial layer form second
The body area (not shown) of conduction type and the body surface formed the first conduction type source region (not shown)；Described
One separation layer 4, fourth epitaxial layer 10 and 9 upper surface of side wall form dielectric layer 11 and form the first contact on the dielectric layer 11
Hole and the second contact hole；Front metal layer 12 and metal layer on back 13 are formed, the front metal layer 12 passes through the first contact hole
It connect and is connect by the second contact hole with the fourth epitaxial layer 10, the metal layer on back 13 with the source region and body area
It is connect with the substrate.
Attached drawing 2 is please referred to, further embodiment of this invention provides a kind of VDMOS device, and the VDMOS device includes: first
The substrate of conduction type；It is formed in the first epitaxial layer 2 of the first conduction type on the substrate；It is formed in first extension
Groove 3 on layer 2；It is formed in first separation layer 4 on 3 surface of groove and 2 upper surface of the first epitaxial layer；It is formed in institute
State first polysilicon layer 5 on 4 surface of the first separation layer on 3 surface of groove；It is formed in the first polysilicon of the bottom of the groove 3
Second separation layer 6 on the surface of layer 5 is formed in the of spaced multiple first conduction types on second separation layer 6
The bottom end of the third epitaxial layer 8 of two epitaxial layers 7 and the second conduction type, second epitaxial layer 7 and the third epitaxial layer 8 is equal
It is connect with second separation layer 6, the first polysilicon layer 5 positioned at 3 side wall of groove is connect with one second epitaxial layer 7, institute
State the height that the height of the second epitaxial layer 7 and the third epitaxial layer 8 in the vertical direction is less than the groove 3；It is formed in ditch
The side wall 9 on surface that first polysilicon layer 5 of 3 side-walls of slot is not covered by second epitaxial layer 7, the side wall 9
Bottom end connect with second epitaxial layer 7；The fourth epitaxial layer being grown on second epitaxial layer 7 and third epitaxial layer 8
10, the groove 3 is filled up, the bottom surface of the fourth epitaxial layer 10 and second epitaxial layer 7 and third epitaxial layer 8 connect
It connects.
It is appreciated that the VDMOS device that the present invention passes through, avoids Conventional power devices and needs through encapsulation and protect
The method for protecting device connection, reduces device area, reduces encapsulation manufacturing cost, improve product reliability.The institute of formation
It states the electrostatic protection structure that the second epitaxial layer 7 and third epitaxial layer 8 form to be formed by using extensional mode, and then reduces electric leakage
Stream, further improves the reliability of VDMOS device provided by the invention.
Further, specifically, carrier of the substrate 1 as the device, primarily serves the effect of support.General feelings
Under condition, the material of the substrate 1 can have silicon substrate, silicon carbide substrates, silicon nitrate substrate etc., in the present embodiment, described
Substrate 1 is silicon substrate, and silicon is most common, cheap and stable performance semiconductor material.In certain embodiments of the present invention,
The substrate 1 is N-type substrate, and 1 resistivity of substrate is 0.001~0.005 Ω * cm, with a thickness of 250~350 μm, in this reality
It applies in mode, the Doped ions of the substrate 1 are specially phosphonium ion, and certainly, in other embodiments, the substrate 1 is mixed
Heteroion can be also other pentavalent ions such as arsenic or antimony.In an embodiment of the present invention, the substrate 1 is as proposed by the present invention
The collector contact area of triode.The pressure resistance of the thickness and concentration and device of first epitaxial layer 2 is closely related, in the present invention
Some embodiments in, 2 resistivity of the first epitaxial layer be 45~60 Ω * cm, thickness is between 15~18 μm.It is preferred that
, first epitaxial layer 2 is formed by the relatively simple homoepitaxy of technique, i.e., the material of described first epitaxial layer 2 and institute
The material for stating substrate 1 is identical, and when the material of substrate 1 is silicon, the material of first epitaxial layer 2 is also silicon.Outside described first
Prolong the upper surface that layer 2 can be formed in the substrate 1 using epitaxial growth method.The doping type of first epitaxial layer 2 and institute
The doping type for stating substrate 1 is identical, and in the present embodiment, the substrate 1 is n-type doping, and first epitaxial layer 2 is N-type
Doping, in other embodiments, if the substrate 1 is p-type doping, first epitaxial layer 2 is p-type doping.In this implementation
In mode, the Doped ions of first epitaxial layer 2 are specially phosphonium ion, in other embodiments, first epitaxial layer 2
Doped ions can be also other pentavalent ions such as arsenic or antimony.More specifically, the epitaxial growth method can be raw for vapour phase epitaxy
Regular way, liquid phase epitaxial process, vacuum evaporation growth method, high-frequency sputtering growth method, molecular beam epitaxial growth method etc., preferably change
Chemical vapor deposition method (or vapor phase epitaxial growth), chemical vapor deposition method be it is a kind of with vapor reaction raw material in solid-state
Matrix surface reacts and deposits into the technique of solid thin layer or film, is a kind of epitaxial growth method of the transistor of comparative maturity,
This method sprays silicon and doped chemical on the substrate 1, and uniformity is reproducible, and step coverage is excellent.Simultaneously
The perfection of silicon materials can be improved in chemical vapor deposition method, improves the integrated level of device, reaches raising minority carrier life time, reduces
The leakage current of storage element.
Further, the process for forming the groove 3 can be with are as follows: etching barrier layer is formed on first epitaxial layer 2,
Then photoresist layer (not shown) is formed in etching barrier layer (not shown), later using covering with 3 figure of groove
Film version is exposed the photoresist layer, then develops, and obtains the photoresist layer with 3 figure of groove.To have
The photoresist layer of 3 figure of groove is that exposure mask is etched on etching barrier layer using lithographic methods such as reactive ion etching methods
Form the figure opening (not shown) of the groove 3.It then is to cover with the etching barrier layer being open with 3 figure of groove
Film removes first epitaxial layer 2 for the barrier layer covering that is not etched, in institute using the methods of wet etching or dry etching
It states in the first epitaxial layer 2 and forms the groove 3.Hereafter the methods of chemical cleaning removal photoresist layer and etch stopper can be used
Layer.In above process, in order to guarantee exposure accuracy, anti-reflecting layer can be also formed between photoresist layer and etching barrier layer
(not shown).
Further, the material of first separation layer 4 can be silica, silicon nitride, aluminium oxide and silicon oxynitride
Etc. one of or any a variety of combination, in the present embodiment, material is silica.First separation layer 4 can be with
It is formed in the surface of first epitaxial layer 2 and the groove 3 by depositing technics, can also be formed by thermal oxidation technology；
In the present embodiment, first separation layer 4 is formed by thermal oxidation technology, and the thermal oxidation technology is those skilled in the art
The conventional technical means of member, is no longer described in detail herein.
Further, the first polysilicon layer 5 is formed on 4 surface of the first separation layer on 3 surface of groove to be specifically included in
Polysilicon is filled in the groove 3；Polysilicon described in dry etching forms first polysilicon layer 5.Wherein, the dry method
Etching includes photoablation, gaseous corrosion, plasma etching etc., and dry etching has easy realization automation, treatment process not
The high advantage of introducing pollution, cleannes.Thickness of first polysilicon layer 5 on 3 bottom of groove and side wall can phase
With can also be different, preferably identical, thickness of first polysilicon layer 5 on 3 bottom of groove and side wall is all larger than
3000A。
Further, the second separation layer 6 is formed on the surface of the first polysilicon layer 5 of the bottom of the groove 3；Described
The material of two separation layers 6 can be one of or arbitrarily a variety of group such as silica, silicon nitride, aluminium oxide and silicon oxynitride
It closes, in the present embodiment, material is silica.For one of which such as silica, silicon nitride, aluminium oxide and silicon oxynitrides
Or any a variety of combination, in the present embodiment, material is silica.Second separation layer 6 can be by depositing work
Skill is formed in the surface of first epitaxial layer 2 and the groove 3, can also be formed by thermal oxidation technology；In this embodiment party
In formula, second separation layer 6 is formed by depositing technics, and depositing technics is a kind of important technique, has developed into object at present
Manage two main directions of vapor deposition and chemical vapor deposition.The deposition technology of metal is usually physical property, belongs to object
Vapor deposition is managed, and the depositing technics of semiconductor layer and insulating layer generally falls into chemical vapor deposition.In the present embodiment, institute
State the second separation layer 6 and formed using CVD method, chemical vapor deposition method be it is a kind of with vapor reaction raw material solid
State matrix surface reacts and deposits into the technique of solid thin layer or film, is a kind of epitaxial growth method of comparative maturity.
Further, second epitaxial layer 7 arranges in the horizontal direction with the third epitaxial layer 8, when vertical view, described
Two epitaxial layers 7 are cyclic structure with the third epitaxial layer 8, and in the present embodiment, the quantity of second epitaxial layer 7 is 2,
The quantity of the third epitaxial layer 8 is 1, wherein first second epitaxial layer 7 is located at the periphery of the third epitaxial layer 8,
The third epitaxial layer 8 is located at the periphery of second second epitaxial layer 7, and first polysilicon layer 5 is located at described first
The periphery of a second epitaxial layer 7, in other modes, the quantity of second epitaxial layer 7 and the third epitaxial layer 8 can root
Change according to the requirement of device.Several spaced second epitaxial layers 7 of the invention and third epitaxial layer 8 form electrostatic protection knot
Structure, the electrostatic protection structure are formed by using extensional mode, and leakage current is small.
Further, the thickness of the side wall 9 is determined according to the requirement of device, generally 2000-5000A, the side wall 9
Material can or any a variety of combination one of for silica, silicon nitride, aluminium oxide and silicon oxynitride etc., in this reality
It applies in mode, material is silica.It is one of or any more for silica, silicon nitride, aluminium oxide and silicon oxynitride etc.
The combination of kind, in the present embodiment, material are silica.The side wall 9 can be formed in described by depositing technics
One polysilicon layer, 5 surface can also be formed in the surface of first polysilicon layer 5 by thermal oxidation technology；The thermal oxide
Technique and the depositing technics are the conventional techniques of those skilled in the art, and this is no longer going to repeat them.
Further, the fourth epitaxial layer 10 is intrinsic epitaxial layer, and the intrinsic epitaxial layer is by epitaxy technique shape
At be entirely free of impurity and pure semiconductor layer without lattice defect.But practical semiconductor cannot be absolute it is pure, such half
Conductor is known as extrinsic semiconductor, and main common representative has the monoclinic crystal structure of silicon, germanium both elements.It is appreciated that in grid
The lower increase intrinsic epitaxial layer can reduce parasitic capacitance, improve the switching speed of chip, and then promote the VDMOS device
The reliability of part.
Further, the fourth epitaxial layer 10 is intrinsic epitaxial layer, and the intrinsic epitaxial layer is by epitaxy technique shape
At be entirely free of impurity and pure semiconductor layer without lattice defect.But practical semiconductor cannot be absolute it is pure, such half
Conductor is known as extrinsic semiconductor, and main common representative has the monoclinic crystal structure of silicon, germanium both elements.It is appreciated that in grid
The lower increase intrinsic epitaxial layer can reduce parasitic capacitance, improve the switching speed of chip, and then promote the VDMOS device
The reliability of part.
Further, the VDMOS device further includes being formed in first separation layer 4, fourth epitaxial layer 10 and side wall 9
The dielectric layer 11 of upper surface and the first contact hole and the second contact hole being formed on the dielectric layer 11；Front metal layer 12 and
Metal layer on back 13, the front metal layer 12 are connect with the source region and body area and are connect by second by the first contact hole
Contact hole is connect with the fourth epitaxial layer 10, and the metal layer on back 13 is connect with the substrate.
Further, although preferred embodiments of the present invention have been described, but those skilled in the art once learn
Basic creative concept, then additional changes and modifications may be made to these embodiments.So appended claims are intended to solve
It is interpreted as including preferred embodiment and all change and modification for falling into the scope of the invention.
Obviously, various changes and modifications can be made to the invention without departing from essence of the invention by those skilled in the art
Mind and range.In this way, if these modifications and changes of the present invention belongs to the range of the claims in the present invention and its equivalent technologies
Within, then the present invention is also intended to include these modifications and variations.
Claims (10)
1. a kind of production method of VDMOS device, which is characterized in that the described method includes:
The substrate of the first conduction type is provided, in the first epitaxial layer of one conduction type of substrate surface growth regulation；
Groove is formed in first epi-layer surface；
The first separation layer is formed in the flute surfaces and first epitaxial layer upper surface；
The first polysilicon layer is formed in the first insulation surface of the flute surfaces；
The second separation layer is formed on the surface of the first polysilicon layer of the bottom of the groove；
The second epitaxial layer and the second conductive-type of spaced multiple first conduction types are formed on second separation layer
The third epitaxial layer of type, the groove is filled up, wherein the bottom end of second epitaxial layer and the third epitaxial layer with
The second separation layer connection, the first polysilicon layer at the trenched side-wall are connect with one second epitaxial layer；
The second epitaxial layer of part and part third epitaxial layer of the top of the groove are removed, is located at the trenched side-wall to expose
The first polysilicon layer of part；
Side wall is formed on part the first polysilicon layer surface exposed；
The fourth epitaxial layer is grown on second epitaxial layer and third epitaxial layer, the groove is filled up, described
The bottom surface of four epitaxial layers is connect with second epitaxial layer and third epitaxial layer.
2. the production method of VDMOS device as described in claim 1, which is characterized in that the method also includes:
The body area of the second conduction type is formed in first epitaxial layer region and forms the first conduction in the body surface
The source region of type；
Dielectric layer is formed in first separation layer, fourth epitaxial layer and side wall upper surface and forms first on the dielectric layer
Contact hole and the second contact hole；
Front metal layer and metal layer on back are formed, the front metal layer passes through the first contact hole and the source region and body Qu Lian
It connects and is connect by the second contact hole with the fourth epitaxial layer, the metal layer on back is connect with the substrate.
3. the production method of VDMOS device as described in claim 1, which is characterized in that side wall and bottom in the groove
Forming the first polysilicon layer includes:
Polysilicon is filled in the groove；
Polysilicon described in dry etching forms first polysilicon layer.
4. the production method of VDMOS device as described in claim 1, which is characterized in that remove the part of the top of the groove
After second epitaxial layer and part third epitaxial layer, before part the first polysilicon layer surface exposed forms side wall, institute
State method further include:
First time annealing process is carried out, annealing temperature is 900 DEG C, and annealing time is 30 seconds；
Second of annealing process is carried out, annealing temperature is 980 DEG C, and annealing time is 20 seconds；
It is cleaned using the ammonium hydroxide that concentration is 20% to structure is formed by.
5. the production method of VDMOS device as claimed in claim 3, which is characterized in that be spaced on second separation layer
The second epitaxial layer of multiple first conduction types and the third epitaxial layer of the second conduction type of arrangement specifically include:
The epitaxial layer of the first conduction type is filled in the groove；
The epitaxial layer for etching first conduction type retains the epitaxial layer of the first conduction type of the trenched side-wall, is protected
The epitaxial layer of first conduction type stayed is second epitaxial layer；
The epitaxial layer of the second conduction type is filled in the remaining area of the groove；
The epitaxial layer for etching second conduction type retains the epitaxial layer of second conduction type of trenched side-wall, is retained
Second conduction type epitaxial layer be the third epitaxial layer；
The epitaxial layer of the first conduction type is continued to fill up, in the remaining area of the groove to form second epitaxial layer.
6. the production method of VDMOS device as described in claim 1, which is characterized in that the fourth epitaxial layer is intrinsic outer
Prolong layer.
7. a kind of VDMOS device characterized by comprising
The substrate of first conduction type；
It is formed in the first epitaxial layer of the first conduction type on the substrate；
The groove being formed on first epitaxial layer；
It is formed in the first separation layer of the flute surfaces and first epitaxial layer upper surface；
It is formed in the first polysilicon layer of the first insulation surface of the flute surfaces；
It is formed in second separation layer on the surface of the first polysilicon layer of the bottom of the groove
It is formed in the second epitaxial layer and the second conduction of spaced multiple first conduction types on second separation layer
The bottom end of the third epitaxial layer of type, second epitaxial layer and the third epitaxial layer is connect with second separation layer,
The first polysilicon layer positioned at the trenched side-wall is connect with one second epitaxial layer, second epitaxial layer and the third extension
The height of layer in the vertical direction is less than the height of the groove；
The side wall being formed on the surface that first polysilicon layer at trenched side-wall is not covered by second epitaxial layer, institute
The bottom end for stating side wall is connect with second epitaxial layer；
The fourth epitaxial layer being grown on second epitaxial layer and third epitaxial layer, the groove is filled up, and the described 4th
The bottom surface of epitaxial layer is connect with second epitaxial layer and third epitaxial layer.
8. a kind of VDMOS device as claimed in claim 7, which is characterized in that further include:
It the body area for the second conduction type being formed in first epitaxial layer region and is formed in the body surface first and leads
The source region of electric type.
9. a kind of VDMOS device as claimed in claim 8, which is characterized in that further include:
It is formed in first separation layer, fourth epitaxial layer and the dielectric layer of side wall upper surface and is formed on the dielectric layer
First contact hole and the second contact hole；
Front metal layer and metal layer on back, the front metal layer by the first contact hole connect with the source region and body area with
And connect by the second contact hole with the fourth epitaxial layer, the metal layer on back is connect with the substrate.
10. a kind of VDMOS device as claimed in claim 7, which is characterized in that the fourth epitaxial layer is intrinsic epitaxial layer.
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| CN201910016269.1A CN109860274A (en) | 2019-01-08 | 2019-01-08 | A kind of VDMOS device and preparation method thereof |
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