CN109119483A - A kind of transistor and preparation method thereof - Google Patents
A kind of transistor and preparation method thereof Download PDFInfo
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- CN109119483A CN109119483A CN201811309093.0A CN201811309093A CN109119483A CN 109119483 A CN109119483 A CN 109119483A CN 201811309093 A CN201811309093 A CN 201811309093A CN 109119483 A CN109119483 A CN 109119483A
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- 238000002360 preparation method Methods 0.000 title description 4
- 238000002347 injection Methods 0.000 claims abstract description 111
- 239000007924 injection Substances 0.000 claims abstract description 111
- 239000000758 substrate Substances 0.000 claims abstract description 42
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 34
- 229920005591 polysilicon Polymers 0.000 claims abstract description 33
- 238000004519 manufacturing process Methods 0.000 claims abstract description 27
- 238000000034 method Methods 0.000 claims abstract description 25
- 229910052751 metal Inorganic materials 0.000 claims description 18
- 239000002184 metal Substances 0.000 claims description 18
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 13
- 229910052710 silicon Inorganic materials 0.000 claims description 13
- 239000010703 silicon Substances 0.000 claims description 13
- 230000003647 oxidation Effects 0.000 claims description 11
- 238000007254 oxidation reaction Methods 0.000 claims description 11
- 230000008569 process Effects 0.000 claims description 11
- 238000005516 engineering process Methods 0.000 claims description 9
- 238000005468 ion implantation Methods 0.000 claims description 9
- 239000013078 crystal Substances 0.000 claims description 3
- 230000008859 change Effects 0.000 abstract description 4
- 150000002500 ions Chemical class 0.000 description 41
- 239000004065 semiconductor Substances 0.000 description 19
- 239000000463 material Substances 0.000 description 14
- 229920002120 photoresistant polymer Polymers 0.000 description 12
- 238000005530 etching Methods 0.000 description 7
- 229910052760 oxygen Inorganic materials 0.000 description 7
- 239000001301 oxygen Substances 0.000 description 7
- 238000010586 diagram Methods 0.000 description 6
- 238000001312 dry etching Methods 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 4
- 238000000151 deposition Methods 0.000 description 4
- 239000000243 solution Substances 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 229910052785 arsenic Inorganic materials 0.000 description 3
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 229910044991 metal oxide Inorganic materials 0.000 description 3
- 150000004706 metal oxides Chemical class 0.000 description 3
- 238000005457 optimization Methods 0.000 description 3
- 230000003071 parasitic effect Effects 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 238000003892 spreading Methods 0.000 description 2
- 230000007480 spreading Effects 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 1
- 229910052797 bismuth Inorganic materials 0.000 description 1
- JCXGWMGPZLAOME-UHFFFAOYSA-N bismuth atom Chemical compound [Bi] JCXGWMGPZLAOME-UHFFFAOYSA-N 0.000 description 1
- -1 boron ion Chemical class 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- RCJVRSBWZCNNQT-UHFFFAOYSA-N dichloridooxygen Chemical compound ClOCl RCJVRSBWZCNNQT-UHFFFAOYSA-N 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 238000005868 electrolysis reaction Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 125000004435 hydrogen atom Chemical class [H]* 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 230000008439 repair process Effects 0.000 description 1
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- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 238000012216 screening Methods 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000003786 synthesis reaction Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
Abstract
The present invention provides a kind of production method of transistor, and method includes: to provide the substrate of the first conduction type；Surface forms the epitaxial layer of the first conduction type over the substrate；Surface forms the first injection region of the first conduction type on said epitaxial layer there；Surface forms gate oxide on said epitaxial layer there；Polysilicon layer is formed in the gate oxide upper surface；Surface forms the second injection region of the second conduction type on said epitaxial layer there；Surface forms the third injection region of the second conduction type on said epitaxial layer there；The source region of the first conduction type is formed in third injection region upper surface, the production process that the present invention passes through change VDMOS, by the way of energetic ion injection, it is primary to form the area Ji Shenti of body area, and then cost of manufacture is saved, the EAS performance parameters for improving device, improve the working performance of VDMOS.
Description
Technical field
The present invention relates to technical field of semiconductors, and in particular to a kind of novel semi-conductor transistor and preparation method thereof.
Background technique
In power application equipment, (Vertical Diffused Metal Oxide Semiconductor's VDMOS hangs down
Straight double-diffused metal oxide semiconductor field effect transistor) it is that one kind can be with widely used metal oxide semiconductcor field effect
Transistor power device is answered, with input impedance is high, switching speed is fast, working frequency is high, voltage control, thermal stability are good etc.
A series of unique features are applied to the side such as switching power supply, high-frequency heating, Computer interface circuit and power amplifier
Face.VDMOS device has a very important parameter, EAS (Energy Avalanche Stress, pulse avalanche energy),
It is defined as the ceiling capacity that device can consume under single avalanche condition.When power device works, it can be generated in source electrode and drain electrode
Biggish due to voltage spikes, it is necessary to consider the avalanche energy of device.EAS ability is also that one of measurement VDMOS device is extremely important
Parameter.In current production method, due to having carried out multiple ion implanting when forming body area and source region, cause process flow multiple
Miscellaneous, cost of manufacture is higher.
Summary of the invention
In view of the above circumstances, the following technical solution is employed in order to solve its technical problem to realize by the present invention.
In a first aspect, the embodiment of the present invention provides a kind of production method of transistor, comprising: provide the first conduction type
Substrate；Surface forms the epitaxial layer of the first conduction type over the substrate；It is conductive to form first for surface on said epitaxial layer there
First injection region of type；Surface forms gate oxide on said epitaxial layer there；Polycrystalline is formed in the gate oxide upper surface
Silicon layer；Surface forms the second injection region of the second conduction type on said epitaxial layer there；Surface forms the on said epitaxial layer there
The third injection region of two conduction types；The source region of the first conduction type is formed in third injection region upper surface；Described more
Crystal silicon layer upper surface forms dielectric layer；Source metal is formed in the dielectric layer upper surface；It is formed in the substrate lower surface
Drain metal layer.
Further, the first injection region that surface forms the first conduction type on said epitaxial layer there specifically includes, in institute
State epitaxial layer upper surface by ion implanting on said epitaxial layer there surface formed the first conduction type the first injection region.
Further, formation gate oxide in surface specifically includes on said epitaxial layer there, and surface is logical on said epitaxial layer there
Peroxidating technique forms gate oxide.
Further, the second injection region that surface forms the second conduction type on said epitaxial layer there specifically includes, in institute
State epitaxial layer upper surface by ion implanting on said epitaxial layer there surface formed the second conduction type the second injection region.
Further, the third injection region that surface forms the second conduction type on said epitaxial layer there specifically includes, in institute
State epitaxial layer upper surface by ion implanting on said epitaxial layer there surface formed the second conduction type third injection region.
Second aspect, the embodiment of the present invention also provide a kind of transistor, including, the substrate of the first conduction type；First leads
The epitaxial layer of electric type is formed in the upper surface of substrate；First injection region of the first conduction type, is formed in the epitaxial layer
Upper surface；Gate oxide is formed in the epitaxial layer upper surface；Polysilicon layer is formed in the gate oxide upper surface；Second
Second injection region of conduction type is formed in the epitaxial layer upper surface；The third injection region of second conduction type, is formed in institute
State epitaxial layer upper surface；The source region of first conduction type is formed in third injection region upper surface；Dielectric layer is formed in institute
State polysilicon layer upper surface；Source metal is formed in the dielectric layer upper surface；Drain metal layer is formed in the substrate
Lower surface.
Further, expose the ion of subsequent third injection region after the polysilicon layer is formed by etched portions polysilicon
Inject window.
Further, second injection region and the third injection region pass through simultaneously ion implantation technology be formed in it is described
Epitaxial layer upper surface.
Further, second injection region and the third injection region are used after carrying out ion implanting by hot injection process
Ion in diffusion injection region.
Further, the ion concentration of second injection region is less than the ion concentration of the third injection region, and described the
Three injection regions, which are used to form the area Shen Ti, reduces body area resistance.
The technical solution of the embodiment of the present invention passes through the production process of optimization VDMOS, by the way of energetic ion injection,
It is primary to form the area Ji Shenti of body area, and then cost of manufacture has been saved, the EAS performance parameters of device are improved, improve VDMOS's
Working performance.
Detailed description of the invention
The attached drawing for constituting a part of the invention is used to provide further understanding of the present invention, schematic reality of the invention
It applies example and its explanation is used to explain the present invention, do not constitute improper limitations of the present invention.
In the accompanying drawings:
Fig. 1 is preparation method of transistor flow diagram described in the embodiment of the present invention；
Fig. 2 is substrate and epitaxial layer structure schematic diagram described in the embodiment of the present invention；
Fig. 3 is gate structure structural schematic diagram described in the embodiment of the present invention；
Fig. 4 is the second injection region and third injection region schematic diagram described in the embodiment of the present invention；
Fig. 5 is source region and medium schematic diagram of a layer structure described in the embodiment of the present invention；
Fig. 6 is source metal and drain metal schematic diagram of a layer structure described in the embodiment of the present invention.
Specific embodiment
It is clear in order to be more clear the purpose of the present invention, technical solution and advantageous effects, below in conjunction with this hair
Attached drawing in bright embodiment, technical scheme in the embodiment of the invention is clearly and completely described, it is clear that described
Embodiment is a part of the embodiment of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, this field is common
Technical staff's every other embodiment obtained without making creative work belongs to the model that the present invention protects
It encloses.
In the description of the present invention, it should be noted that term " center ", "upper", "lower", "left", "right", "vertical",
The orientation or positional relationship of the instructions such as "horizontal", "inner", "outside" is to be based on the orientation or positional relationship shown in the drawings, or be somebody's turn to do
Invention product using when the orientation or positional relationship usually put, be merely for convenience of description of the present invention and simplification of the description, without
It is that the device of indication or suggestion meaning or element must have a particular orientation, be constructed and operated in a specific orientation, therefore not
It can be interpreted as limitation of the present invention.In addition, term " first ", " second ", " third " etc. are only used for distinguishing description, and cannot manage
Solution is indication or suggestion relative importance.
Usually using two complicated manufacture craft manufacturing semiconductor devices: front end manufacture and back-end manufacturing.Front end manufacture
It include that multiple small pieces are formed on the surface of semiconductor wafer.Each small pieces include active and passive electronic member on the wafer
Part, described active and passive electronic components are electrically connected to form functional circuitry, active electron component, such as transistor and two poles
Pipe has the ability of control electric current flowing.Passive electronic components, such as capacitor, inductor, resistor and transformer.It generates
Relationship between voltage and current necessary to execution circuit function.
By a series of processing step, passive and active element, the processing step are formed on the surface of semiconductor
Including doping, deposition, photoetching, etching and planarization.Doping passes through the technology of such as ion implanting or thermal diffusion, adds impurities to
In semiconductor material.Doping process changes the conductivity of the semiconductor material in active device, and semiconductor material is converted to absolutely
Edge body, conductor, or dynamically change in response to electric field or base current the conductivity of semiconductor material.
Active and passive element is formed by the layer of the material with different electrical properties.It can be by partly by deposited material
A variety of deposition techniques that the type of material is determined form these layers.For example, film deposition may include chemical vapor deposition, physics
Vapor deposition, electrolysis plating and plated by electroless plating technique.Usually pattern each layer with formed active component, passive element or
The part of electrical connection between element.
Below in conjunction with Fig. 1-Fig. 6, the production method for providing a kind of transistor to the embodiment of the present invention is described in detail, this
Inventive embodiments provide a kind of production method of transistor, which includes:
S01: the substrate 1 of the first conduction type is provided；
S02: surface forms the epitaxial layer 2 of the first conduction type over the substrate；
S03: surface forms the first injection region 3 of the first conduction type on the epitaxial layer 2；
S04: surface forms gate oxide 4 on the epitaxial layer 2；
S05: polysilicon layer 5 is formed in 4 upper surface of gate oxide；
S06: surface forms the second injection region 6 of the second conduction type on the epitaxial layer 2；
S07: surface forms the third injection region 7 of the second conduction type on the epitaxial layer 2；
S08: the source region 8 of the first conduction type is formed in 7 upper surface of third injection region；
S09: dielectric layer 9 is formed in 5 upper surface of polysilicon layer；
S10: source metal 10 is formed in 9 upper surface of dielectric layer；
S11: drain metal layer 11 is formed in 1 lower surface of substrate；
With reference to the accompanying drawings, the specific method of the above-mentioned formation transistor is elaborated.
As shown in Fig. 2, step S01: the substrate 1 of the first conduction type is provided, specifically, first conduction type is P
One of type doping and n-type doping, second conduction type are p-type doping and the another kind in n-type doping.
Special to illustrate herein for convenience of description: first conduction type can be n-type doping, so that described second is conductive
Type is p-type doping；First conduction type can also adulterate for p-type, so that second conduction type is n-type doping.
In next embodiment, using first conduction type as n-type doping, second conduction type is doped to for p-type
Example is described, but is defined not to this.
Specifically, P type substrate and p-type extension belong to P-type semiconductor, and N-type substrate and N-type extension belong to N-type and partly lead
Body.The P-type semiconductor is the silicon wafer for adulterating triad, such as any group of boron element or phosphide element or aluminium element or three
It closes, the N-type semiconductor be any combination of silicon wafer of doping pentad, such as P elements or arsenic element or both.
The substrate 1 is the carrier in integrated circuit, and the substrate 1 plays the role of support, and the substrate 1 also assists in institute
State the work of integrated circuit.The substrate 1 can be silicon substrate, or Sapphire Substrate, it might even be possible to it is silicon Chu substrate,
Preferably, the substrate 1 is silicon substrate, and the especially described substrate 1 is monocrystalline substrate, this is because silicon substrate material and wherein
Single crystal silicon material have the characteristics that low cost, large scale, conductive, avoid edge effect, yield can be increased substantially.
In some embodiments of the invention, the substrate 1 is the semiconductor of the first conduction type, and the substrate 1 can be in monocrystalline
Any combination that P elements or arsenic element or both are adulterated in silicon is made.
As shown in Fig. 2, step S02: the epitaxial layer 2 of the first conduction type is formed in 1 upper surface of substrate, specifically,
The n-type doping that the first conduction type is carried out on the substrate 1 forms the epitaxial layer 2, and the doping concentration and thickness of epitaxial layer 2 are not
It only determines the breakdown voltage of device, also affects the conducting resistance of device, high breakdown voltage requires being lightly doped for thickness outer
Prolong layer, and low conducting resistance then requires the epitaxial layer of thin heavy doping, it is therefore necessary to optimal extension parameter is selected, so that full
It is smaller that sufficient breakdown voltage simultaneously turns on resistance, and in one embodiment, 2 doping concentration of epitaxial layer is less than the semiconductor
Doping concentration so that epitaxial layer 2 has a higher breakdown voltage, and then protects device.
As shown in Fig. 2, step S03: surface forms the first injection region 3 of the first conduction type, tool on the epitaxial layer 2
Body, on the epitaxial layer 2 surface by ion implantation technology formed the first conduction type the first injection region 3, by
The semiconductor epitaxial layers coat photoresist, carry out ion implantation technology, note to the semiconductor using photoresist as masking film
The ionic type entered is the first conductive type ion, such as phosphorus, arsenic, antimony, bismuth plasma, forms the of first conduction type
One injection region, for reducing the conducting resistance of device.
As shown in figure 3, step S04: surface forms gate oxide 4 on the epitaxial layer 2, specifically, logical to semiconductor
Cross dry-oxygen oxidation formed gate oxide 4, wherein method for oxidation include dry-oxygen oxidation, wet-oxygen oxidation, steam oxidation, mix oxychloride,
Oxidation Process By Hydrogen Oxygen Synthesis etc., preferred dry-oxygen oxidation, oxidizing temperature are 900 DEG C -1100 DEG C in oxidation process in the present embodiment,
It is passed directly into oxygen to be aoxidized, the gate oxide compact structure generated by dry-oxygen oxidation, uniformity and reproducible, to miscellaneous
The advantages that matter screening ability is strong, good with the adhesion of photoresist.The thickness of gate oxide depend on transistor threshold voltage and
Grid pressure resistance demand, it is preferable that the gate oxide 4 is with a thickness of between 0.05~0.20um.
As shown in figure 3, step S05: polysilicon layer 5 is formed in 4 upper surface of gate oxide, specifically, in the grid
4 upper surface of oxide layer forms the polysilicon layer 5 by depositing technics to form gate structure, and deposit mode includes atmospheric pressure
Vapour deposition process, Low Pressure Chemical Vapor Deposition, plasma auxiliary chemical vapor deposition method etc. are learned, in the present embodiment,
Preferably Low Pressure Chemical Vapor Deposition, the polysilicon purity is high of doping, uniformity are strong.Preferably, the polysilicon layer 5
With a thickness of between 0.30~0.80um.More specifically, after the completion of the polysilicon layer 5 deposits, light is carried out to the polysilicon layer 5
Etching forms gate structure, wherein the method for etching includes dry etching and wet etching, it is preferred that the etching used
Method is dry etching, and dry etching includes photoablation, gaseous corrosion, plasma etching etc., and dry etching is easily realized certainly
Dynamicization, treatment process are not introduced into pollution, cleannes height.In some embodiments of the invention, the dry etching that uses specifically,
Mask material is prepared in the upper surface of the polysilicon layer, the mask material is specially photoresist, and photoresist is in the polycrystalline
The upper surface of silicon layer forms photoresist layer, forms grid in the polysilicon layer upper surface by etching on the photoresist layer
Structure removes the photoresist layer.
As shown in figure 4, step S06: surface forms the second injection region 6 of the second conduction type, tool on the epitaxial layer 2
Body, surface forms the second injection region 6 of the second conduction type by ion implantation technology on the epitaxial layer 2, in this hair
In bright one embodiment, the ion of injection is boron ion, and concentration is 1.0E14~1.0E15/cm, energy be 500KEV~
2000KEV。
As shown in figure 4, step S07: surface forms the third injection region 7 of the second conduction type, tool on the epitaxial layer 2
Body, surface forms the third injection region 7 of the second conduction type by ion implantation technology on the epitaxial layer 2, and described the
Three injection regions 7 are formed simultaneously with second injection region 6 by primary ions injection, in ion implanting, the gate oxide 4
Cause the thickness of different zones of 2 upper surface of epitaxial layer different from the polysilicon layer 5, during ion implanting,
Since the obstacle thickness of different zones is different, and then the ion concentration and area that cause different zones to be injected are different.It is described more
The window that crystal silicon layer 5 is formed through over etching forms the third injection region 7 in ion implanting, and region blocks object thickness is most herein
It is few, so that the ion of the third injection region 7 injection is most, and then the area Shen Ti is formed, the area Shen Ti ion concentration is higher,
Resistance is lower, and it is bigger compared to the volume in body area, thereby reduces the resistance in entire body area, can prevent parasitic three
Pole pipe conducting, the area Shen Ti improve the EAS ability of device for reducing body area resistance；The area of other ion implantings
Domain range forms second injection region 6 by the gate oxide 4 and the polysilicon layer 5, and then forms body area.Form institute
It states and carries out heat after the second injection region 6 and the third injection region 7 and drive in, driving in temperature is between 1100 DEG C~1200 DEG C, when
Between be 50~200min, for spreading second injection region 6 and the third injection region 7.
As shown in figure 5, step S08: forming the source region 8 of the first conduction type in 7 upper surface of third injection region, specifically
, mask material is prepared in the upper surface of the third injection region 7, the mask material is specially photoresist, and photoresist is in institute
The upper surface for stating epitaxial layer forms photoresist layer, passes through the heavy doping ion of the first conduction type of injection on the photoresist layer
Source region 7 is formed, the source region 7 is formed in 6 upper surface of the area Shen Ti, increases the short circuit area of source region 7 Yu the body area.
As shown in figure 5, step S09: dielectric layer 9 is formed in 5 upper surface of polysilicon layer, specifically, the polysilicon
5 upper surface of layer by using sputtering or thermal oxidation method or chemical vapor deposition process or in which several formation dielectric layer 9,
The dielectric layer 9 is usually formed by the preferable material of insulating properties, for example, the material of the dielectric layer 9 is silicon oxide or silicon nitride
Or silicon oxynitride in one embodiment, passes through the method for sputtering for protecting device not contaminated and having the function of isolation
Surface forms the dielectric layer 9 of silica on the epitaxial layer 2.
As shown in fig. 6, step S10: source metal 10 is formed in 9 upper surface of dielectric layer, specifically, the extension
Layer upper surface forms the source metal 10 by sputtering method.
As shown in fig. 6, step S11: drain metal layer 11 is formed in 1 lower surface of substrate, specifically, the substrate 1
Lower surface forms the drain metal layer 11 by the method evaporated.
A kind of production method of transistor provided in an embodiment of the present invention, by the way of energetic ion injection, a shape
The area Ji Shenti of adult area, and then cost of manufacture has been saved, the EAS performance parameters of device are improved, the workability of VDMOS is improved
Energy.
As shown in fig. 6, the embodiment of the present invention provides a kind of transistor, comprising:
The substrate 1 of first conduction type；
The epitaxial layer 2 of first conduction type is formed in 1 upper surface of substrate；
First injection region 3 of the first conduction type is formed in 2 upper surface of epitaxial layer；
Gate oxide 4 is formed in 2 upper surface of epitaxial layer；
Polysilicon layer 5 is formed in 4 upper surface of gate oxide；
Second injection region 6 of the second conduction type is formed in 2 upper surface of epitaxial layer；
The third injection region 7 of second conduction type is formed in 2 upper surface of epitaxial layer；
The source region 8 of first conduction type is formed in 7 upper surface of third injection region；
Dielectric layer 9 is formed in 5 upper surface of polysilicon layer；
Source metal 10 is formed in 9 upper surface of dielectric layer；
Drain metal layer 11 is formed in 1 lower surface of substrate.
Further, after the polysilicon layer 5 is formed by etched portions polysilicon expose subsequent third injection region 7 from
Son injection window, the polysilicon layer 5 are both used to form the gate structure of the transistor after chemical wet etching, while
The ion implantation window for exposing subsequent third injection region 7, for forming doping concentration bigger third note when subsequent ion injection
Enter area 7.
Further, second injection region 6 is formed in institute by ion implantation technology simultaneously with the third injection region 7
2 upper surface of epitaxial layer is stated, the gate oxide 4 makes 2 upper surface of epitaxial layer when ion implanting with the polysilicon layer 5
Obstacle thickness it is different, and then injected by primary ions and be formed simultaneously second injection region 6 and the third injection region
7。
Further, second injection region 6 and the third injection region 7 pass through hot injection process after carrying out ion implanting
For spreading the ion of injection region.
Further, the ion concentration of second injection region 6 is less than the ion concentration 7 of the third injection region, described
Third injection region, which is used to form the area Shen Ti, reduces body area resistance, and the area Shen Ti reduces body area resistance, promotes device EAS ability.
Further, the third injection region 7 is formed simultaneously with second injection region 6 by primary ions injection, by
In in ion implanting, the gate oxide 4 and the polysilicon layer 5 lead to the different zones of 2 upper surface of epitaxial layer
Thickness is different, during ion implanting, since the obstacle thickness of different zones is different, and then different zones is caused to be injected
Ion concentration and area it is different.The window that the polysilicon layer 5 is formed through over etching forms the third in ion implanting
Injection region 7, region blocks object thickness is minimum herein, so that the ion of the third injection region 7 injection is most, and then forms deep body
Area, the area Shen Ti ion concentration is higher, and resistance is lower, and it is bigger compared to the volume in body area, thereby reduces whole
The resistance in individual area, can prevent parasitic triode ON, and the area Shen Ti improves device for reducing body area resistance
The EAS ability of part；The regional scope of other ion implantings of the epitaxial layer upper surface passes through the gate oxide 4 and the polycrystalline
Silicon layer 5 forms second injection region 6, and then forms body area.Pass through the thickness of the gate oxide 4 and the polysilicon layer 5
The difference of structure, and then the area Ji Shenti of body area, the technique system for not only reducing transistor are formed simultaneously by one-time process
Make process, and effectively improves the EAS performance parameters of device.
The technical scheme of the present invention has been explained in detail above with reference to the attached drawings, and the present invention passes through the production process of optimization VDMOS,
It is primary to form the area Ji Shenti of body area by the way of energetic ion injection, manufacture craft is simplified, manufacturing cost is reduced.Separately
Outside, the area Shen Ti is formed by using ion implanting, the area Shen Ti doping concentration is higher, and resistance is lower, and its phase
Volume compared with body area is bigger, thereby reduces the resistance in entire body area, parasitic triode ON can be prevented, to be promoted
The EAS ability of device.In conclusion the present invention goes out from the production process of optimization power device and the structure of change power device
Hair, it is primary to form the area Ji Shenti of body area by the way of energetic ion injection, and then cost of manufacture has been saved, improve device
EAS performance parameters, improve the working performance of VDMOS.
The foregoing is only a preferred embodiment of the present invention, is not intended to restrict the invention, for the skill of this field
For art personnel, the invention may be variously modified and varied.All within the spirits and principles of the present invention, made any to repair
Change, equivalent replacement, improvement etc., should all be included in the protection scope of the present invention.
Claims (10)
1. a kind of production method of transistor, which is characterized in that the described method includes:
The substrate of first conduction type is provided；
Surface forms the epitaxial layer of the first conduction type over the substrate；
Surface forms the first injection region of the first conduction type on said epitaxial layer there；
Surface forms gate oxide on said epitaxial layer there；
Polysilicon layer is formed in the gate oxide upper surface；
Surface forms the second injection region of the second conduction type on said epitaxial layer there；
Surface forms the third injection region of the second conduction type on said epitaxial layer there；
The source region of the first conduction type is formed in third injection region upper surface；
Dielectric layer is formed in the polysilicon layer upper surface；
Source metal is formed in the dielectric layer upper surface；
Drain metal layer is formed in the substrate lower surface.
2. manufacturing method according to claim 1, which is characterized in that surface forms the first conductive-type on said epitaxial layer there
First injection region of type specifically includes, and by ion implanting, surface forms the on said epitaxial layer there on surface on said epitaxial layer there
First injection region of one conduction type.
3. manufacturing method according to claim 1, which is characterized in that surface forms gate oxide tool on said epitaxial layer there
Body includes that surface forms gate oxide by oxidation technology on said epitaxial layer there.
4. manufacturing method according to claim 1, which is characterized in that surface forms the second conductive-type on said epitaxial layer there
Second injection region of type specifically includes, and by ion implanting, surface forms the on said epitaxial layer there on surface on said epitaxial layer there
Second injection region of two conduction types.
5. manufacturing method according to claim 1, which is characterized in that surface forms the second conductive-type on said epitaxial layer there
The third injection region of type specifically includes, and by ion implanting, surface forms the on said epitaxial layer there on surface on said epitaxial layer there
The third injection region of two conduction types.
6. a kind of transistor characterized by comprising
The substrate of first conduction type；
The epitaxial layer of first conduction type is formed in the upper surface of substrate；
First injection region of the first conduction type is formed in the epitaxial layer upper surface；
Gate oxide is formed in the epitaxial layer upper surface；
Polysilicon layer is formed in the gate oxide upper surface；
Second injection region of the second conduction type is formed in the epitaxial layer upper surface；
The third injection region of second conduction type is formed in the epitaxial layer upper surface；
The source region of first conduction type is formed in third injection region upper surface；
Dielectric layer is formed in the polysilicon layer upper surface；
Source metal is formed in the dielectric layer upper surface；
Drain metal layer is formed in the substrate lower surface.
7. transistor according to claim 6, which is characterized in that the polysilicon layer passes through etched portions polycrystalline after being formed
The ion implantation window of silicon exposing subsequent third injection region.
8. transistor according to claim 6, which is characterized in that second injection region and the third injection region are simultaneously
The epitaxial layer upper surface is formed in by ion implantation technology.
9. transistor according to claim 6, which is characterized in that second injection region and the third injection region carry out
It is used to spread the ion of injection region after ion implanting by hot injection process.
10. crystal pipe fitting according to claim 6, which is characterized in that the ion concentration of second injection region is less than institute
The ion concentration of third injection region is stated, the third injection region, which is used to form the area Shen Ti, reduces body area resistance.
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| CN110047930A (en) * | 2019-04-02 | 2019-07-23 | 芯兴(北京)半导体科技有限公司 | VDMOS device |
| CN114420758A (en) * | 2021-12-08 | 2022-04-29 | 西安理工大学 | SiC MOSFET with high threshold voltage and method of manufacture |
| CN117096153A (en) * | 2023-10-18 | 2023-11-21 | 荣湃半导体（上海）有限公司 | ESD integrated MOSFET device and preparation method thereof |
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| CN104299907A (en) * | 2013-07-19 | 2015-01-21 | 北大方正集团有限公司 | Preparation method of VDMOS device |
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| US4757032A (en) * | 1984-10-25 | 1988-07-12 | Sgs Thomson Microelectronics S.P.A. | Method for DMOS semiconductor device fabrication |
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| CN110047930A (en) * | 2019-04-02 | 2019-07-23 | 芯兴(北京)半导体科技有限公司 | VDMOS device |
| CN114420758A (en) * | 2021-12-08 | 2022-04-29 | 西安理工大学 | SiC MOSFET with high threshold voltage and method of manufacture |
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| CN117096153B (en) * | 2023-10-18 | 2024-01-19 | 荣湃半导体（上海）有限公司 | ESD integrated MOSFET device and preparation method thereof |
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