CN105225957A - Slot type power device manufacture method and slot type power device - Google Patents
Slot type power device manufacture method and slot type power device Download PDFInfo
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- CN105225957A CN105225957A CN201410300234.8A CN201410300234A CN105225957A CN 105225957 A CN105225957 A CN 105225957A CN 201410300234 A CN201410300234 A CN 201410300234A CN 105225957 A CN105225957 A CN 105225957A
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Abstract
The invention provides slot type power device manufacture method and slot type power device, wherein, slot type power device manufacture method, comprise: after substrate surface implanting p-type ion forms territory, p type island region, at substrate surface silicon oxide deposition layer, by photoetching and be etched in territory, p type island region formed contact hole; Be formed with substrate surface deposit first silicon nitride layer of contact hole; Etch the first silicon nitride layer, the sidewall of contact hole forms side wall; Inject N-type doped chemical to territory, p type island region, bottom contact hole, form N-type region territory; Be formed with substrate surface deposit second silicon nitride layer in N-type region territory; Etch the second silicon nitride layer, bottom contact hole, form groove.By technical scheme of the present invention, reduce the width of groove, eliminate the restriction of photoetching process precision to groove width, reduce power device manufacturing cost, reduce the conducting resistance of power device simultaneously, improve the performance of power device.
Description
Technical field
The present invention relates to semiconductor device and manufacture technics field thereof, in particular to a kind of slot type power device manufacture method and a kind of slot type power device.
Background technology
The drain electrode of trench vertical bilateral diffusion field-effect tranisistor and source electrode are respectively in the both sides of power device, electric current vertically circulates at device inside, adds current density, improves rated current, the conducting resistance of unit are is also less, is a kind of purposes power device widely.
At present, the development trend of trench vertical bilateral diffusion field-effect tranisistor is: reduce switching speed and switching loss, reduction chip area, reduce conducting resistance, raising power device is withstand voltage.Wherein, reduce the total conducting resistance of power device and can reduce static power consumption, the total conducting resistance of power device is formed primarily of three parts: channel resistance, drift zone resistance and resistance substrate.The size of this three partial ohmic value is all determined by the structure of power device and manufacturing process.
For low voltage power devices, in the total conducting resistance of power device, drift zone resistance is less relative to proportion with resistance substrate, so channel resistance plays major decision effect in conducting resistance part, therefore the conducting resistance that channel resistance significantly can reduce power device is reduced, and the cellular size reducing power device can make the quantity of raceway groove in per device area increase, add the breadth length ratio of raceway groove, current path is increased, thus reduce channel resistance.And the main method reducing the cellular size of power device is the width reducing groove.In conventional groove manufacturing method, groove width is determined by the minimum line thickness of photoetching process, and in order to reduce groove width, need to use more advanced lithographic equipment, power device manufacturing cost can significantly rise.
Because adjacent cellular size reduces, also namely can under equal area integrated more power device, thus make resistance in parallel more, total conducting resistance of equivalence also will be less, adjacent cellular size reduces, both can play the effect reducing total conducting resistance, also can reduce chip area, reduce power device manufacturing cost.But reducing of cellular size, is subject to the restriction of photoetching process precision, uses traditional technique to become to the slot type power device manufacturing high density primitive unit cell and be more and more difficult to realize.
Therefore the groove width how using traditional technique to reduce power device becomes technical problem urgently to be resolved hurrily at present.
Summary of the invention
The present invention just based on above-mentioned technical problem one of at least, propose a kind of slot type power device manufacture method, by preparing bilateral wall, reduce the width of groove, without the need to adopting the photoetching process of high cost just can reduce groove width, eliminating the restriction of photoetching process precision to groove width, reducing power device manufacturing cost, reduce the conducting resistance of power device simultaneously, improve the performance of power device.
In view of this, according to an aspect of the present invention, provide a kind of slot type power device manufacture method, comprising: after substrate surface implanting p-type ion forms territory, p type island region, at described substrate surface silicon oxide deposition layer, by photoetching and be etched in territory, described p type island region formed contact hole; Be formed with substrate surface deposit first silicon nitride layer of described contact hole; Etch described first silicon nitride layer, the sidewall of described contact hole forms side wall; Inject N-type doped chemical to territory, described p type island region, bottom described contact hole, form N-type region territory; Be formed with substrate surface deposit second silicon nitride layer in described N-type region territory; Etch described second silicon nitride layer, bottom described contact hole, form groove.
By at substrate surface deposit first silicon nitride layer, etch after this first silicon nitride layer forms side wall on the sidewall of contact hole, at substrate surface deposit second silicon nitride layer, etch this second silicon nitride layer, bilateral wall is formed in contact hole, owing to forming bilateral wall in contact hole, reduce the width of contact hole internal channel, just groove width can be reduced without the need to using the photoetching process of high cost, reduce the production cost of power device, eliminate the restriction of photoetching process precision to groove width, compared with prior art, decrease a lithography step, reduce the complexity of power device manufacture craft, simultaneously because bilateral wall reduces the width of groove, groove density is largely increased, the quantity of the raceway groove in per device area increases, add the breadth length ratio of raceway groove, current path is increased, thus reduction channel resistance, improve the Performance And Reliability of power device.
According to a further aspect in the invention, propose a kind of slot type power device, described slot type power device adopts the slot type power device manufacture method described in above-mentioned arbitrary technical scheme to be made.
Accompanying drawing explanation
Fig. 1 shows the schematic flow diagram of slot type power device manufacture method according to an embodiment of the invention;
Fig. 2 shows the power device cross-sectional view forming territory, p type island region according to an embodiment of the invention at substrate surface implanting p-type ion;
Fig. 3 shows the power device cross-sectional view according to an embodiment of the invention after substrate surface silicon oxide deposition layer;
Fig. 4 shows the power device cross-sectional view according to an embodiment of the invention after substrate surface forms photoresist mask;
Fig. 5 shows the power device cross-sectional view after forming contact hole according to an embodiment of the invention on silicon oxide layer;
Fig. 6 shows the power device cross-sectional view after forming contact hole according to an embodiment of the invention on territory, p type island region;
Fig. 7 shows the power device cross-sectional view according to an embodiment of the invention after substrate surface deposit first silicon nitride layer;
Fig. 8 shows the power device cross-sectional view according to an embodiment of the invention after N-type doped chemical is injected in territory, p type island region;
Fig. 9 shows the power device cross-sectional view according to an embodiment of the invention after substrate surface deposit second silicon nitride layer;
Figure 10 shows the power device cross-sectional view etched according to an embodiment of the invention after the second silicon nitride layer formation groove;
Figure 11 shows the power device cross-sectional view according to an embodiment of the invention after substrate surface depositing polysilicon layer;
Figure 12 shows etch polysilicon polysilicon top in groove according to an embodiment of the invention and forms the power device cross-sectional view after silicon oxide layer;
Figure 13 shows the power device cross-sectional view after forming metal silicide according to an embodiment of the invention in contact hole.
Embodiment
In order to more clearly understand above-mentioned purpose of the present invention, feature and advantage, below in conjunction with the drawings and specific embodiments, the present invention is further described in detail.It should be noted that, when not conflicting, the feature in the embodiment of the application and embodiment can combine mutually.
Set forth a lot of detail in the following description so that fully understand the present invention, but the present invention can also adopt other to be different from other modes described here and implement, and therefore, the present invention is not limited to the restriction of following public specific embodiment.
Fig. 1 shows the schematic flow diagram of slot type power device manufacture method according to an embodiment of the invention.
As shown in Figure 1, slot type power device manufacture method, comprising: step 102 according to an embodiment of the invention, after substrate surface implanting p-type ion forms territory, p type island region, at described substrate surface silicon oxide deposition layer, by photoetching and be etched in territory, described p type island region formed contact hole; Step 104, is being formed with substrate surface deposit first silicon nitride layer of described contact hole; Step 106, etches described first silicon nitride layer, the sidewall of described contact hole forms side wall; Step 108, injects N-type doped chemical to territory, described p type island region, forms N-type region territory bottom described contact hole; Step 110, is being formed with substrate surface deposit second silicon nitride layer in described N-type region territory; Step 112, etches described second silicon nitride layer, bottom described contact hole, forms groove.
By at substrate surface deposit first silicon nitride layer, etch after this first silicon nitride layer forms side wall on the sidewall of contact hole, at substrate surface deposit second silicon nitride layer, etch this second silicon nitride layer, bilateral wall is formed in contact hole, owing to forming bilateral wall in contact hole, reduce the width of contact hole internal channel, just groove width can be reduced without the need to using the photoetching process of high cost, reduce the production cost of power device, eliminate the restriction of photoetching process precision to groove width, compared with prior art, decrease a lithography step, reduce the complexity of power device manufacture craft, simultaneously because bilateral wall reduces the width of groove, groove density is largely increased, the quantity of the raceway groove in per device area increases, add the breadth length ratio of raceway groove, current path is increased, thus reduction channel resistance, improve the Performance And Reliability of power device.
In technique scheme, preferably, etch described first silicon nitride layer and described second silicon nitride layer by plasma dry etch process, described plasma dry etch process is anisotropic etching straight down.
In this technical scheme, by dry etching first silicon nitride layer and the second silicon nitride layer, make the anisotropy in etching process good, controllability, flexibility, repeatability better, can control the precision etched preferably, improve the performance of power device.
In technique scheme, preferably, the thickness of described first silicon nitride layer is 0.5 μm to 3 μm, and the thickness of described second silicon nitride layer is 0.1 μm to 1 μm.
In technique scheme, preferably, described by photoetching and when being etched in territory, described p type island region formation contact hole, the degree of depth of described contact hole is greater than longitudinal degree of depth of described silicon oxide layer, and the bottom of described contact hole is arranged in territory, described p type island region.
In technique scheme, preferably, the bottom of described groove is arranged in described substrate.
In technique scheme, preferably, described P type ion is single ionic or compound ion, wherein, described ion comprise following at least one or a combination set of: hydrogen, helium, boron, arsenic, aluminium.
In technique scheme, preferably, the thickness of described silicon oxide layer is 1 μm to 10 μm.
In technique scheme, preferably, described bottom described contact hole, form groove after, also comprise: by carrying out thermal oxidation to described substrate, form the first oxide layer at the inner surface of described groove; Be formed with the substrate surface depositing polysilicon layer of described first oxide layer; Etch the silicon nitride on described polysilicon layer and described contact hole sidewall, described N-type region territory is arranged in make the top of the polysilicon retained in described groove, carry out described thermal oxidation by described substrate, the second oxide layer is formed on polysilicon top in the trench; In described substrate surface deposited metal, form metal silicide by the region of annealing in process bottom the sidewall and described contact hole of described contact hole except described second oxide layer portion; Metal thickening, passivation, etching are carried out to described substrate.
In this technical scheme, metal silicide is formed by the region bottom the volume sidewall and contact hole of contact hole except the second oxide layer portion, formation source metal contacts, and conveniently technique carries out metal thickening afterwards, passivation, the techniques such as etching finally can be made into the less power device of groove width, groove width reduces, and adds the breadth length ratio of raceway groove, current path is increased, thus reduction channel resistance, improve the Performance And Reliability of power device.
In technique scheme, preferably, the thickness of described polysilicon layer is 1 μm to 10 μm, and the temperature of described annealing in process is 700 DEG C to 1200 DEG C, and the time of described annealing in process is 10 minutes to 400 minutes.
Next further describe according to one embodiment of the invention referring to figs. 2 to Figure 13.
Slot type power device manufacture method according to an embodiment of the invention, wherein, substrate is described for silicon chip, can comprise:
As shown in Figure 2, P type ion implantation is carried out on the surface of silicon chip 202, form P type injection zone 204 on the surface of silicon chip 202, wherein, P type ion can be hydrogen and/or helium and/or boron plasma, P type ion can adopt single ionic also can adopt compound ion, certainly, also having of one skilled in the art will appreciate that P type ion herein can select is a lot, herein and be not used in concrete restriction, such as: arsenic, aluminium etc.
As shown in Figure 3, carry out high-temperature annealing process on silicon chip 202 surface, form silicon oxide layer 302 on silicon chip 202 surface, wherein, silicon oxide layer thickness is 1 μm to 10 μm.
As shown in Figure 4, deposit photoresist layer 402 on silicon oxide layer 302, and on described silicon oxide layer 302, form photoresist window 404 by the mode of photoetching, etching.
As shown in Figure 5, anisotropic dry etch silicon oxide layer 302 straight down, form silicon oxide layer contact hole (not shown), the bottom of silicon oxide layer contact hole contacts with territory, p type island region, and also namely longitudinal degree of depth of contact hole equals longitudinal degree of depth of silicon oxide layer.
As shown in Figure 6, by territory, silicon oxide layer contact hole dry etching p type island region, form contact hole 602, wherein, the bottom of contact hole 602 is arranged in P type tagma.
As shown in Figure 7, at surface deposition first silicon nitride layer 702 of silicon chip 202, wherein, the thickness of the first silicon nitride layer is 0.5 μm to 3 μm.The the first silicon nitride layer thickness adopting the mode of deposit that the sidewall of the surface of silicon oxide layer 302 and contact hole 602 is formed is identical.
As shown in Figure 8, anisotropic dry etch is straight down carried out to silicon chip 202, etch away the first silicon nitride layer bottom silicon oxide layer 302 surface and contact hole 602, the first silicon nitride layer side wall (in figure, 702 is the first silicon nitride layer) is formed at the sidewall of contact hole 602, inject N-type doped chemical by contact hole 602 to territory, p type island region, form N-type region territory 802 in the bottom of contact hole 602.
As shown in Figure 9, at surface deposition second silicon nitride layer 902 of silicon chip 202, wherein, the thickness of the second silicon nitride layer is 0.1 μm to 1 μm.
As shown in Figure 10, anisotropic dry etch is straight down carried out to silicon chip, groove 10A is formed in the bottom of contact hole 602, the width of groove 10A is reduced by twice deposit silicon nitride layer (the first silicon nitride layer and the second silicon nitride layer), because bilateral wall reduces the width of groove 10A, groove 10A density is largely increased, the quantity of the raceway groove in per device area increases, add the breadth length ratio of raceway groove, current path is increased, thus reduction channel resistance, improve the Performance And Reliability of power device, wherein, the bottom of groove 10A is arranged in silicon chip 202, thermal oxidation is carried out to silicon chip 202, oxide layer 10B (being equivalent to the first oxide layer) is formed in groove 10A.
As shown in figure 11, at the superficial growth polysilicon layer 11A of silicon chip 202.
As shown in figure 12, the polysilicon layer 11A on dry etching silicon slice 202 surface, etch away the silicon nitride in the polysilicon on silicon oxide layer 302 surface and contact hole 602 and polysilicon, the top of the polysilicon in groove 10A is made to be positioned at N-type region territory 802, carry out thermal oxidation to silicon chip 202, oxide layer 10B (being equivalent to the second oxide layer) is formed on the top of the polysilicon in groove 10A.
As shown in figure 13, in the surface deposition metal level (not shown) of silicon chip 202, thermal anneal process is carried out to silicon chip 202, metal silicide 13A is formed in the region that metal level and silicon directly contact, also the region namely bottom the sidewall and contact hole 602 of contact hole 602 except groove 10A forms metal silicide 13A, the surface of silicon oxide layer 302 and the protection of groove 10A top silica, metal can not react with silicon, then wet etching falls metal level, metal silicide 13A cannot etch away, formation source metal contacts, follow-up conveniently technique carries out metal thickening, passivation, the techniques such as etching are finally made into slot type power device.
Slot type power device according to an embodiment of the invention, adopts as the slot type power device manufacture method described in above-mentioned arbitrary technical scheme is made.
According to slot type power device of the present invention, by preparing bilateral wall, reduce the width of groove, just groove width can be reduced without the need to adopting the photoetching process of high cost, eliminate the restriction of photoetching process precision to groove width, reduce power device manufacturing cost, reduce the conducting resistance of power device simultaneously, improve the performance of power device.
These are only the preferred embodiments of the present invention, be not limited to the present invention, for a person skilled in the art, the present invention can have various modifications and variations.Within the spirit and principles in the present invention all, any amendment done, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (10)
1. a slot type power device manufacture method, is characterized in that, comprising:
Formed after territory, p type island region at substrate surface implanting p-type ion, at described substrate surface silicon oxide deposition layer, by photoetching and be etched in territory, described p type island region and form contact hole;
Be formed with substrate surface deposit first silicon nitride layer of described contact hole;
Etch described first silicon nitride layer, the sidewall of described contact hole forms side wall;
Inject N-type doped chemical to territory, described p type island region, bottom described contact hole, form N-type region territory;
Be formed with substrate surface deposit second silicon nitride layer in described N-type region territory;
Etch described second silicon nitride layer, bottom described contact hole, form groove.
2. slot type power device manufacture method according to claim 1, it is characterized in that, etch described first silicon nitride layer and described second silicon nitride layer by plasma dry etch process, described plasma dry etch process is anisotropic etching straight down.
3. slot type power device manufacture method according to claim 2, is characterized in that, the thickness of described first silicon nitride layer is 0.5 μm to 3 μm, and the thickness of described second silicon nitride layer is 0.1 μm to 1 μm.
4. slot type power device manufacture method according to claim 1, it is characterized in that, described by photoetching and when being etched in territory, described p type island region formation contact hole, the degree of depth of described contact hole is greater than longitudinal degree of depth of described silicon oxide layer, and the bottom of described contact hole is arranged in territory, described p type island region.
5. slot type power device manufacture method according to claim 1, is characterized in that, the bottom of described groove is arranged in described substrate.
6. slot type power device manufacture method according to claim 1, is characterized in that, described P type ion is single ionic or compound ion, wherein, described ion comprise following at least one or a combination set of: hydrogen, helium, boron, arsenic, aluminium.
7. slot type power device manufacture method according to claim 1, is characterized in that, the thickness of described silicon oxide layer is 1 μm to 10 μm.
8. slot type power device manufacture method according to any one of claim 1 to 7, is characterized in that, described bottom described contact hole, form groove after, also comprise:
By carrying out thermal oxidation to described substrate, form the first oxide layer at the inner surface of described groove;
Be formed with the substrate surface depositing polysilicon layer of described first oxide layer;
Etch the silicon nitride on described polysilicon layer and described contact hole sidewall, described N-type region territory is arranged in make the top of the polysilicon retained in described groove, carry out described thermal oxidation by described substrate, the second oxide layer is formed on polysilicon top in the trench;
In described substrate surface deposited metal, form metal silicide by the region of annealing in process bottom the sidewall and described contact hole of described contact hole except described second oxide layer portion;
Metal thickening, passivation, etching are carried out to described substrate.
9. slot type power device manufacture method according to claim 8, is characterized in that, the thickness of described polysilicon layer is 1 μm to 10 μm, and the temperature of described annealing in process is 700 DEG C to 1200 DEG C, and the time of described annealing in process is 10 minutes to 400 minutes.
10. a slot type power device, is characterized in that, described slot type power device adopts slot type power device manufacture method as claimed in any one of claims 1-9 wherein to be made.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN107658341A (en) * | 2017-09-27 | 2018-02-02 | 上海朕芯微电子科技有限公司 | A kind of groove type power MOS FET and preparation method thereof |
| CN109427884A (en) * | 2017-08-23 | 2019-03-05 | 深圳市敦为技术有限公司 | A kind of manufacturing method of dual buried layer groove power device |
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| US20110303925A1 (en) * | 2010-06-10 | 2011-12-15 | Fuji Electric Co., Ltd. | Semiconductor device and the method of manufacturing the same |
| CN103681850A (en) * | 2012-09-13 | 2014-03-26 | 台湾积体电路制造股份有限公司 | Power mosfet and forming method thereof |
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| CN101908488A (en) * | 2009-06-08 | 2010-12-08 | 尼克森微电子股份有限公司 | Ditching type metal-oxide semiconductor assembly manufacturing method |
| US20110303925A1 (en) * | 2010-06-10 | 2011-12-15 | Fuji Electric Co., Ltd. | Semiconductor device and the method of manufacturing the same |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109427884A (en) * | 2017-08-23 | 2019-03-05 | 深圳市敦为技术有限公司 | A kind of manufacturing method of dual buried layer groove power device |
| CN107658341A (en) * | 2017-09-27 | 2018-02-02 | 上海朕芯微电子科技有限公司 | A kind of groove type power MOS FET and preparation method thereof |
| CN107658341B (en) * | 2017-09-27 | 2020-09-15 | 上海朕芯微电子科技有限公司 | Groove type power MOSFET and preparation method thereof |
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