200926420 九、發明說明： ..【發明所屬之技術領域】 ；.. 本發明係關於半導體裝置和製造該半導體裝置之方 法，且洋吕之，係關於提供有非揮發性.記憶體之半導體裝 置和製造該半導體裝置之方法。 【先前技術】 最近，已廣泛使用一種其為半導體裝置、能夠於關斷 電源後保持住資料之非揮發性記憶體。於由非揮發性記憶 〇體所表示之快閃記憶體中，形成記憶體胞（mem〇ry⑶⑴之 電晶體具有浮置閘極或稱之為電荷儲存層用於儲存電荷至 記錄資料之絕緣膜。具有絕緣膜作為電荷儲存層之快閃記 憶體包含SONOS(矽化物氧化物氮化物氧化物矽化物）結構 用來儲存電荷於ΟΝΟ膜（氧化物膜/氮化物膜/氧化物膜）内 部之陷捕層（trap layer)。美國專利第6,〇〗j，725號揭示一種 類型之SONOS快閃記憶體，也就是，具有虛擬接地類型 ❹記憶體胞之快閃記憶體，該記憶體胞以對稱方式操作可交 換之源極和没極。 曰本專利申請公報第2000-004014和2004-343014號 揭不一種具有電荷儲存層部分形成於閘極電極下方區域上 之技術。 抑於美國專利第6,〇11，725號中，二位元資料能儲存於 單一記憶體胞中。當記憶體胞最小化時，二位元資料之間 之干擾更可能發生。電荷儲存層被分離用來分別儲存二個 位元以便抑制干擾。然而，不容易製造在閘極電極下方具 5 94452 200926420 • 有電荷儲存層被分為二段之半導體裝置。 【發明内容】 本發明提供一種在閘極電極下方具有分離之電荷儲疒 ’層之半導體裝置’以及一種用來容易製造該半導體裝子 方法。 之 根據本發明之一態樣，提供一種半導體裝置，其包含 閘極電極，設在半導體基板之上方；閘極絕緣膜，設在該 半導體基板上而在該閘極電極中央之下方；第一絕緣膜， 〇設置從該閘極絕緣膜上方區域至該閘電極之二端下方之區 域，且其由與該閘極絕緣膜之材料不同之材料形成；隧道 絕緣膜，形成在該半導體基板上於該閘極絕緣膜之二端 處；以及電荷儲存層，㈣於該随道絕緣膜和該第一絕緣 膜之間。根據本發明，能夠容易製造在閘極電極下方具有 分離之電荷儲存層之半導體裝置，以及能夠個別設定第一 絕緣膜和隧道絕緣膜之各膜的厚度。 ❾ 根據本發明之另一態樣，提供一種用於製造半導體裝 置之方法，該方法包含下列步驟：在半導體基板上形成間 極絕緣膜；在該閘極絕緣膜上形成第-絕緣膜；在該第-f緣膜上形成閘極電極；選擇性地去除該閘極電極、該第 一絕緣膜和該Μ極絕緣膜，該閘極電極、該第—絕緣膜和 該閘極絕緣膜係疊層以允許該閉極電極和該第一絕緣族被 各向異I*生地钱刻’和該閘極絕緣膜被側面鞋刻；於半導體 基板上該閘極絕緣膜被側面姓刻的區域上形成随道絕緣 膜’以及在該隨道絕緣臈上形成電荷儲存層。根據本發明， 94452 200926420 :能夠容純造在閘極電極下方具有分離 導體装置，以及能夠個別設定第一絕緣膜之半 ..各膜的厚度。 隨道絕緣膜之 , 【實施方式】 記憶2=據:!較的範例和第一至第三實施例之快閃 ==二為擴散區3°之位元線延伸㈣板 予兀線34延伸相交於半導體基板10上之 區30。擴散區30之間之半導體美板 、 〇在其上形成電荷儲存層26侧" = = = 線34,如影線區所示。電荷儲== Π 34之延伸方向於通道區44上之£1和以端。告電 層2Μ皮此分離，則儲存於單一記憶體胞中之二：位 散區;二制。電荷儲存層26可以連續地形㈣ 0 f著$字說明根據比較的範例製造半導體裝置之方 1刘a jA至Μ圖之各圖對應沿著第Ϊ圖中所示線Λ-Α &⑺》·參知第圖，閘極絕緣膜12形成於半導體基 ^ 以及假層（dummy layer)%進一步形成在閘極絕 夂昭笛上假層36和閘極絕緣膜12之預定區域被蝕刻。 ^ 圖，閘極絕緣膜12受到從假層36之二端之侧 ^』以形成底切部（undercut p〇rtion)18。參照第2C圖， 、邑緣膜2G分別形成在閘極絕緣膜12之側面、半導體基板 ^表面上。於半導體基板1〇上 成隧道絕緣膜21，而假層36下方之絕緣膜 7 94452 200926420 .-20變成第二絕緣膜23。 ..#照第3A圖’電荷儲存層26形成於第二絕緣膜23 和隧道絕緣膜21之間。擴散層3〇使用假層36作為遮罩， 形成於半導體基板ίο之内侧。形成絕緣層32以覆蓋假層 36’該絕緣層32被研磨直到假層％之上表面被暴露為止。 參照第3B圖，去除假層36。络 ^ 矛0㈣假！ 36。弟-絕緣膜38形成於該閘極 絕緣膜12、第二絕緣膜23、和頌矮a 19 l . 和、、色緣層32上。上絕緣膜（top Ο ΓΤ^)40係由第一絕緣膜3 8和第二絕緣膜23形 以成。參照第3C圖，亦用作盔泰 _力用作為間極電極之字元線34形成於 第一絕緣膜38上。於此種方法， 、 導體裝置。 種方去產生根據比較的範例之半 於比較的範例中，-柄|尹& 士两 夕τ士· 個電何儲存層26形成於閉極電極200926420 IX. Description of the invention: .. [Technical field to which the invention pertains] The present invention relates to a semiconductor device and a method of fabricating the same, and the invention relates to a semiconductor device provided with a non-volatile memory. And a method of manufacturing the semiconductor device. [Prior Art] Recently, a non-volatile memory which is a semiconductor device capable of holding data after the power is turned off has been widely used. In a flash memory represented by a non-volatile memory cartridge, a memory cell is formed (mem〇ry(3)(1) has a floating gate or a charge storage layer for storing charge to an insulating film for recording data. A flash memory having an insulating film as a charge storage layer includes a SONOS (methane oxide oxide nitride oxide) structure for storing a charge inside the tantalum film (oxide film/nitride film/oxide film) Trap layer. U.S. Patent No. 6, 〇J, 725 discloses a type of SONOS flash memory, that is, a flash memory having a virtual ground type ❹ memory cell, the memory cell The exchangeable source and the finite electrode are operated in a symmetrical manner. The patent application publications Nos. 2000-004014 and 2004-343014 disclose a technique in which a portion of the charge storage layer is formed on a region below the gate electrode. In No. 6, No. 11,725, the two-dimensional data can be stored in a single memory cell. When the memory cell is minimized, the interference between the two-dimensional data is more likely to occur. The charge storage layer is separated. It is used to store two bits separately to suppress interference. However, it is not easy to manufacture under the gate electrode with 5 94452 200926420 • A semiconductor device having a charge storage layer divided into two segments. SUMMARY OF THE INVENTION The present invention provides a gate device A semiconductor device having a separate charge storage layer under the electrode and a method for easily fabricating the semiconductor device. According to an aspect of the present invention, a semiconductor device including a gate electrode and a semiconductor is provided Above the substrate; a gate insulating film disposed on the semiconductor substrate below the center of the gate electrode; and a first insulating film disposed from an upper region of the gate insulating film to a region below the two ends of the gate electrode And formed of a material different from a material of the gate insulating film; a tunnel insulating film formed on the semiconductor substrate at both ends of the gate insulating film; and a charge storage layer, (4) the trace insulating film And the first insulating film. According to the present invention, it is possible to easily manufacture a semiconductor device having a separate charge storage layer under the gate electrode And the thickness of each of the films of the first insulating film and the tunnel insulating film can be individually set. ❾ According to another aspect of the present invention, a method for fabricating a semiconductor device is provided, the method comprising the steps of: forming a semiconductor substrate a pole insulating film; forming a first insulating film on the gate insulating film; forming a gate electrode on the first-f edge film; selectively removing the gate electrode, the first insulating film, and the drain insulating film The gate electrode, the first insulating film, and the gate insulating film are laminated to allow the closed electrode and the first insulating group to be etched and the gate insulating film is laterally The shoe is inscribed on the semiconductor substrate, and the gate insulating film is formed on the side surface of the gate insulating film and the charge storage layer is formed on the track insulating layer. According to the present invention, 94452 200926420: a device having a separate conductor disposed under the gate electrode and capable of individually setting a half of the first insulating film. In the case of the insulating film, [Embodiment] Memory 2 = according to: The comparative example and the flashing of the first to third embodiments == two are the diffusion region 3° bit line extension (four) the board is extended to the line 34 The regions 30 intersect on the semiconductor substrate 10. The semiconductor plate between the diffusion regions 30 and the germanium on which the charge storage layer 26 side is formed " = = = line 34, as indicated by the hatched area. The charge storage == Π 34 extends in the direction of the £1 and the ends of the channel region 44. The layer 2 is separated from the skin, and is stored in the second memory cell: the dislocation area; the second system. The charge storage layer 26 can be continuously topographically formed (4) 0 f with a $ word description. According to the comparative example, the square of the semiconductor device is manufactured, and each of the figures is corresponding to the line shown in the figure Λ-Α & (7) In the figure, the gate insulating film 12 is formed on the semiconductor substrate and the dummy layer is further formed in a predetermined region of the dummy layer 36 and the gate insulating film 12 on the gate electrode. ^, the gate insulating film 12 is received from the side of the two ends of the dummy layer 36 to form an undercut portion 18 . Referring to Fig. 2C, the edge film 2G is formed on the side surface of the gate insulating film 12 and the surface of the semiconductor substrate ^, respectively. The tunnel insulating film 21 is formed on the semiconductor substrate 1 while the insulating film 7 94452 200926420 .-20 under the dummy layer 36 becomes the second insulating film 23. The charge storage layer 26 is formed between the second insulating film 23 and the tunnel insulating film 21 as shown in Fig. 3A. The diffusion layer 3 is formed on the inner side of the semiconductor substrate by using the dummy layer 36 as a mask. An insulating layer 32 is formed to cover the dummy layer 36'. The insulating layer 32 is ground until the surface of the dummy layer is exposed. Referring to Figure 3B, the dummy layer 36 is removed. Network ^ Spear 0 (four) fake! 36. The insulating film 38 is formed on the gate insulating film 12, the second insulating film 23, and the dwarf a 19 l and the color fringe layer 32. The upper insulating film (top ) ) ^) 40 is formed by the first insulating film 38 and the second insulating film 23. Referring to Fig. 3C, a word line 34, which is also used as a mesa electrode, is formed on the first insulating film 38. In this way, the conductor device. The recipe is to generate a half of the comparative example. In the comparative example, the -handle|Yin& 士二 夕 士 士 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、
:一而’使用假層36使製造步驟複雜化。假層36 用來形成要較随道絕緣膜2】主；© μ L ㈣瞪” ^ 厚的上絕.緣臈4G。當隧道 絕緣膜21和第二絕緣膜23使用如第％圖中所示切 ❹=形成時’隨道絕緣㈣具有與 質 同的厚度。因此，如第犯_ _ ▼膜實質相 第’於去除假層36之後， 弟，’、邑緣膜38形成於第二絕缝腔 由第一㈣m故 以及上絕緣膜40 第、、邑緣膜38和第二絕緣膜23形成。 4〇能夠製得較隨道絕緣膜21為厚。、° 緣膜 上絕緣膜40製得較隧道 由：要求薄_道絕_21是為了厚録於下列理 儲存層26和通道區44 ^去除施加於電荷 求上絕緣膜40之屋* 電荷（電子）。同時，要 、 又要厚係為了維持電荷儲存層26之電 94452 8 200926420 :荷保持性。也就是說，要求上絕緣膜4〇要厚是為了當去除 能抑制電荷從閘極電極16遷移至電荷儲存層％。 攻疋為什麼上絕緣膜40要製得較隧道絕緣膜21為厚的 ’因。 … ’、 、，第1圖顯示在閘極電極下方具有分離之電荷儲存層26 之半導體裝置，該閘極電極透過簡單的製程而產生，該製 程使得各隧道絕緣膜21和上絕緣膜4〇具有最佳的厚度而 不須使用假層36。 又 ❾J 一實施例 參照第4A至7B圖，將說明根據第一實施例製造該半 導體裝置之方法。第4A至6圖為對應分別沿著第丨圖中 所不線A-A和B-B之剖面圖。第7A圖為對應沿著第j圖 中所示線A-A之剖面之圖式，第7B圖為對應沿著第i圖 中所示線B-B之剖面之圖式。 參^、第4 A圖，二氧化石夕膜形成之閘極絕緣膜丨2透過 〇熱氧化製程形成於P型矽半導體基板1〇上（或矽半導體基 板中之P型區中）。由氧化鋁形成之第一絕緣膜14透過原 子層沉積（Atomic Layer Deposition，ALD)製程形成於閘極 絕緣膜12上。由多晶矽形成之閘極電極16透過化學氣相 沉積（Chemical Vapor Deposition，CVD)製程形成於第一絕 緣膜14上。閘極絕緣臈12、第一絕緣膜14、和閘極電極 16之厚度可分別設定至2〇nm、l〇nm、和150nm。參照第 4B圖’閘極電極16、第一絕緣膜14、和閘極絕緣膜12 經受到各向異性独刻（anisotropic etching)被去除以便形成 9 94452 200926420 .·延伸於位元線方向之條狀圖案（stripe pattern)。參照第4c 圖，閘極絕緣膜12使用例如氟化酸水溶液經受到側面蝕 .刻。因此，其為側面蝕刻區之底切部18形成於閘極電 ’ 16之下方。 參照第5A圖，透過ALD製程形成由氧化鋁形成之絕 緣膜20，以覆蓋底切部18之内表面（也就是說在半導體 基板ίο上和第一絕緣膜14下方之底切部18，和閘極絕緣 膜12之侧表面之區域）和閘極電極16。絕緣膜2〇之厚度 〇可以設定至5nm。在半導體基板1〇上底切部以之區域二 之絕緣膜20變成隧道絕緣膜21。在第一絕緣膜14下方在 底切部18之區域上之絕緣膜2〇變成第二絕緣膜22。第一 絕緣膜14和第二絕緣膜22形成上絕緣膜24。參照第 圖，由氧化铪（hafnium oxide)形成之電荷儲存層26透過 ALD製程而.形成，以便填滿底切部18和覆蓋該絕緣膜⑼。 結果，包含随道絕緣膜21、電荷儲存層26、和上絕緣膜 ❹24之疊層（iaminated layer)28形成於底切部丨8之内側。參 照第5C圖，使用閘極電極16作為遮罩而姓刻電荷儲存層 26和絕緣膜2〇。 參照第6圖’特子係使用閉極電極16作為遮罩而植 入於半導體基板1G中，以形成為N型擴散區％之位元線。 形成由氧切形成之絕緣層32，以覆蓋擴散區％和閉極 電極16之上表面。透過化學機械研磨（Chemicai: The use of the dummy layer 36 complicates the manufacturing steps. The dummy layer 36 is used to form the upper surface of the insulating film 2]; μL (four) 瞪" ^ thick upper edge 臈 4G. When the tunnel insulating film 21 and the second insulating film 23 are used as shown in the % figure ❹切❹=Formation's insulation (4) has the same thickness as the thickness. Therefore, as the first _ _ ▼ membrane substantial phase 'after removing the dummy layer 36, brother, ', the 邑 film 38 is formed in the second The sulcus cavity is formed by the first (four) m and the upper insulating film 40, the rim film 38 and the second insulating film 23. The 〇 can be made thicker than the associated insulating film 21. The method of making the tunnel is: the requirement is that the thin film is used for thick recording in the following storage layer 26 and the channel region 44. The charge (electron) applied to the upper insulating film 40 is removed. In order to maintain the charge of the charge storage layer 26, the insulation film is required to be thick. In other words, the upper insulating film 4 is required to be thick in order to suppress the migration of charges from the gate electrode 16 to the charge storage layer. The reason why the upper insulating film 40 is made thicker than the tunnel insulating film 21 is '...', and, the first picture shows A semiconductor device having a separate charge storage layer 26 under the gate electrode, the gate electrode being formed by a simple process which allows the tunnel insulating film 21 and the upper insulating film 4 to have an optimum thickness without The dummy layer 36 is used. Further, an embodiment will be described with reference to FIGS. 4A to 7B, and a method of manufacturing the semiconductor device according to the first embodiment will be explained. Figs. 4A to 6 are corresponding to the line AA and A cross-sectional view of BB. Fig. 7A is a diagram corresponding to a section along line AA shown in Fig. j, and Fig. 7B is a diagram corresponding to a section along line BB shown in Fig. i. 4A, the gate insulating film 丨2 formed by the dioxide film is formed on the P-type germanium substrate 1 (or the P-type region in the semiconductor substrate) by a thermal oxidation process. The first insulating film 14 is formed on the gate insulating film 12 by an Atomic Layer Deposition (ALD) process. The gate electrode 16 formed of polycrystalline germanium is formed by a chemical vapor deposition (CVD) process. The first insulating film 14 The thickness of the insulating buffer 12, the first insulating film 14, and the gate electrode 16 can be set to 2 〇 nm, 10 〇 nm, and 150 nm, respectively. Referring to FIG. 4B, the gate electrode 16, the first insulating film 14, and the gate The pole insulating film 12 is removed by anisotropic etching to form a 9 94452 200926420. stripe pattern extending in the direction of the bit line. Referring to FIG. 4c, the gate insulating film 12 is used. For example, an aqueous solution of fluorinated acid is subjected to side etching. Therefore, the undercut portion 18, which is a side etching region, is formed under the gate electrode < Referring to FIG. 5A, an insulating film 20 formed of aluminum oxide is formed through an ALD process to cover an inner surface of the undercut portion 18 (that is, an undercut portion 18 on the semiconductor substrate ί and below the first insulating film 14, and The region of the side surface of the gate insulating film 12) and the gate electrode 16. The thickness 绝缘 of the insulating film 2〇 can be set to 5 nm. The insulating film 20 in the region 2 under the undercut portion on the semiconductor substrate 1 becomes the tunnel insulating film 21. The insulating film 2 〇 under the first insulating film 14 on the region of the undercut portion 18 becomes the second insulating film 22. The first insulating film 14 and the second insulating film 22 form an upper insulating film 24. Referring to the figure, a charge storage layer 26 formed of hafnium oxide is formed through an ALD process to fill the undercut portion 18 and cover the insulating film (9). As a result, an iaminated layer 28 including the tracking insulating film 21, the charge storage layer 26, and the upper insulating film 24 is formed inside the undercut portion 丨8. Referring to Fig. 5C, the gate electrode 16 is used as a mask to name the charge storage layer 26 and the insulating film 2''. Referring to Fig. 6, the special sub-system is implanted in the semiconductor substrate 1G using the closed electrode 16 as a mask to form a bit line which is an N-type diffusion region %. An insulating layer 32 formed by oxygen cutting is formed to cover the diffusion region % and the upper surface of the closed electrode 16. Through chemical mechanical grinding (Chemicai
Polish ’CMP)製程該絕緣層32被研磨以暴露該間極電極 16。此使得可能平坦化閘極電極16和絕緣層之上表面。 94452 10 200926420 參照第7Α和7Β圖，客曰功思上、丄 ㈣声32卜成在閑極電極Μ和 ，絕緣層32上。參照第冗圖，去除對應於預期 ，線之間區域（第1圖中所示線B_ 石 、子疋 16。參昭第7A HI，夕日a 日日a和閘極電極 麥”、、第7A圖，多晶石夕層存在於預 區域，並與閘極電極16電性輕接。成為子70線之 30相交之字元線34。其後，渺忐爲”擴散£ 插塞金屬（Piugmetal)、接飨居$ 、； A & y絕緣膜、 之半導體裝置。層4，以產生根據第—實施例 ο 參照第4A圖，間極絕緣膜12和第一絕緣膜 同的材料形成。參照第4C圖，取決於 不 面蝕刻，使用蝕刻該閘極絕緣 "乎不膜〗2之側 緣膜u之化學物品^門緣==疋4手不麵刻第一絕 於该閘極絕緣膜12由氧化矽膜报忐， 而該第-、絕緣膜U由氧化紹/料成， 液用來側面蝕刻閘極絕緣膜 Χ + 4Β圖中實施，使得門㈣Γ 述步驟巾，韻刻如第 甲只施使仔間極電極16和第一絕緣膜 ο 性方式蝕刻。如第4Γ园 谷向異 圖中之蝕刻允許閘極絕緣膜12使用 間極電極16作為遮罩 把用 中，疊置之間極電極16、第m大側面钱刻。於此方法 被選擇性地去除。第—絕緣膜14和閘極絕緣膜u 如第4C圖中所示，& 18 ±方^ ^ 因為第一絕緣膜Μ存在於底切部 上方，因此第一和 ’ 2心如第5A圖中所-。緣膜14和22形成上絕緣膜 χ 不。絕緣臈20透過ald製程而形成， 以使得隧道絕緣膜21知贫_ , ^ 度。結果，上絕緣膜2t 22具有實質相同的厚 、、、 之厚度（藉由加上第一和第二絕緣 94452 11 200926420 ·: 3厚度所得的膜厚度）㈣製得大㈣ ...度。如此-來，上絕緣膜 膜=1之厚 導體基板i ，+/^ _電極16形成在半 咕Λ 如第7Α圖中所示。來昭坌7Δ 第1圖，閘極絕緣膜12形成 一第Α圖和 0/| 良在閑極電極16之中丰β玄& 線34之延伸方向閘極電極i6之中 、(f子疋 ❹板10上。第一絕緣膜14 i 、方，並於半導體基 膜14破形成從閘極絕緣膜12iFh 伸至閘極電極16之二端（在字 ㈣12上Q域延 16之二端)下方區域。第一，邑緣'膜4延伸方向閘極電極 不同的材料製成。隧道㈣t 由與閘極絕緣膜12 於閑極絕緣形成在半導體基板10上 ㈣和第一絕緣膜14電：儲226插置於隧道絕緣 緣膜-下方並在電荷儲m二^膜22形成在第一絕 ❹絕緣膜21由相同的材料製成。。弟—絕緣膜22和隨道 随道絕緣膜21供使料電賴絲26請道阻障。 孖層26為大。例如，當氫 氧化紹膜用來形成隨道絕緣模21 時，電荷儲存層26可以由氧化銓形成。 參照第5A圖，透過ALD製程形成絕緣膜⑼之前， Ί厚度大約1 nm之薄氧化石夕膜可以形成於半導體基板 上如此可此改進由絕緣膜2〇形成之隧道絕緣膜21之 品質。 94452 12 200926420 一第二實施你丨 ·. 於第二實施例中，上絕緣膜由第一絕緣膜形成。參照 :·.第8A圖，執行根據第4入至4(：圖中所示第一實施例之製 程步驟。參照第8B圖，使用熱氧化作用製程以形成由氧 化矽膜形成之絕緣膜20a，以覆蓋半導體基板1〇和間極電 之上表面。使用熱氧化作用製程不允許絕緣膜；20a 4形成於第-絕緣膜14下方和在難絕緣膜i2側表面 〇二絕緣膜2〇a之厚度例如可設定至5nm。随道絕緣膜… 由底切部18中在半導體基板1〇上之絕緣膜遍形成。 參照第’透過CVD製程形成由氮㈣膜形成之 ^儲存層26a，以便填滿於底切部18中，並覆蓋該絕緣 、因此，第一絕緣膜14直接形成在電荷儲存層施 。且層28a由隧道絕緣膜2U、電荷儲 、 緣層24a形成。'· P上絕 _參…、第9圖，執行根據第一實施例第5C至7B圖中所 ❹不之製程步驟’以產生根據第二實施例之半導體裝置。 帛8B圖中所示’第二實施例取決於形成之隨道絕 、、 不要求待形成之第二絕緣膜。隧道絕緣膜21可 =、形成之第二絕緣膜22同時形成，如根據第 第5八圖中所示。 =第一實施例中’當閘極絕緣膜12由氧化石夕膜形成 2:第—絕緣膜14由氧化銘膜形成，用來獲得第4C圖中 料=選擇性的侧面钕刻。當與由第一絕緣膜㈣同的材 …之膜被要求用來形成上絕緣膜％時’絕緣膜汕(亦 94452 13 200926420 ·: 絕緣膜21)期望由氧化紹膜形成。同時，於第二 :··二 可選擇任意的材料用來形成隨道絕緣膜21a。 :·=终使用能夠形成具有更優越品質之随道絕緣膜之氧化 夕膜’如隧道絕緣膜21a。 + ;第實&例巾’當使甩氧化銘膜作為瞇道絕緣膜21 H八有靶隙小於氧化鋁之能隙之氧化铪被用來形成電$ =2:。於第二實施例中，當氧化賴用來形成 時’使得容易製造之氮切膜能夠用來形成電荷儲 ;第一實施例中，上絕緣膜24a和随道絕緣膜21 a之 各厚度可以個別設定。當第一絕緣膜14之厚度（亦即，上 絕緣膜24a)製得大於隧道絕緣膜21a之厚度時，隧道絕緣 膜21a允許隧道電流流過，而上絕緣膜2牦具有足夠保持 電荷儲存層26a之電荷保持性之厚度。 第二實施你丨 〇 於第三實施例中，第一和第二絕緣膜由不同的材料形 成。參照第10A圖，執行根據第4A至4C圖中所示第一 實施例之製程步驟。參照第10B圖，透過ALD製程形成 由氧化矽形成之絕緣膜20b，以便覆蓋底切部18和閘極電 極W之内表面。絕緣膜20b之厚度可以設定至$ nm。随 道絕緣膜21b由底切部18中半導體基板1〇上之絕緣膜2〇b 形成。該底切部18中第一絕緣膜14下方之絕緣膜2〇b變 成第二絕緣膜22b。上絕緣膜24b由該第一和第二絕緣膜 14和22b形成。透過CVD製程形成由氮化矽膜形成之電 94452 14 200926420 --荷儲存層26b，以便填滿於底切部18並覆蓋該絕緣膜20b。 厂於是，由隧道絕緣膜21b、電荷儲存層26b、和上絕緣膜 ,,24b ^/成之疊層28b形成在底切部18之内侧。參照第1 〇c 圖，執行根據第5C至7B圖中所示之第一實施例之製造步 驟，以產生根據第三實施例之半導體褒置。 於第三實施例中，氧化鋁膜用來形成第一絕緣膜Μ， 而該氧化石夕膜用來形成閘極絕緣膜12 矛口隨道絕緣膜21b。參照第圖，第一絕緣膜14幾乎不 道絕緣膜训可以由具有優越薄膜品質之氧切膜 於第-至第三實施例中’電荷儲存層％可以是孽如 =之導體。當電荷儲存層26藉由導體形成並配置ς字元 向:：：，如第7Β圖中所示時，於擴散區30之延伸方 接4體胞之電荷儲存層26被電㈣合。當你 ❹為電荷儲存層時，執行去除字 用作 驟。於此種方式，氧化銓、氮^何料層26之步 矽臈）任何其中—種、 和矽膜（例如，多晶 π里j用采形成電荷儲在 矽膜為電荷儲存層可使大量 了錯存層26。使用導體 氮化石夕膜之絕緣膜可使用 存。譬如氧化給、 間電荷儲存層之步騍。…°了_子層以省略去除字元線 之較佳實施例，但是本 ’而在本發明之精神和 的，可作各種的修飾和 雖然以上已詳細說明了本發明 =明並不受這些特定實施例之限制 色圍内，#申請專利範圍中所界定 94452 15 200926420 . 改變。 ...【圖式簡單說明】 ,·， 帛1圖為根據比較的範例和本發明之第—至第三實 例之快閃記憶體之平面圖；~ 一第2A至2C圖顯示根據比較的範例對應沿著第】圖中 所示線A-A(部分1)製造快閃記憶體之步驟； 第3A至3C圖顯示根據比較的範例對應沿著第i圖中 所示線A-A(部分2)製造快閃記憶體之步驟； ❹ 第4人至4C圖顯示根據第一實施例對應沿著第i圖中 所示線A-A(部分1)製造快閃記憶體之步驟； 第5A至5C圖顯示根據第一實施例對應沿著第！圖中 所示線A-A(部分2)製造快閃記憶體之步驟； 第6圖為顯示根據第—實施例對應沿著第丨圖中所示 線A-A(部分3)製造快閃記憶體之步.驟之剖面圖； 第7A和7B圖顯示根據第一實施例製造快閃記憶體之 〇步驟，其中，第7A圖為對應沿著第1圖中所示線之 剖面之剖面圖，而第7B圖為對應沿著第1圖中所示線 之剖面之剖面圖； 第8A至8C圖顯示根據第二實施例對應沿著第1圖中 所示線A-A(部分1)製造快閃記憶體之步驟； 弟9圖為顯不根據第二實施例對應沿著第1圖中所矛 線A-A(部分2)製造快閃記憶體之步驟之剖面圖；以及 第10A至l〇C圖顯示根據第三實施例對應沿著第1圖 中所示線A-A製造快閃記憶體之步驟。 16 94452 200926420 【主要元件符號說明】 10 矽基板 12 閘極絕 緣 膜 14 第一絕緣膜 16 閘極電 極 18 底切部 20、 20a、20b 絕 緣 21、 21a 、21b 隧道絕 緣膜 22、 22b 第二絕緣膜 23 第二絕 緣 膜 24、 24a 、24b 上絕緣 膜 26、 26a ' 26b 電荷儲 存層 28、 28a 、28b 疊層 30 擴散區 32 絕緣層 34 字兀線 36 假層 38 第一絕 緣 膜 40 上絕緣膜 44 通道區 Ο 17 94452The Polish 'CMP' process is performed by polishing the insulating layer 32 to expose the interpole electrode 16. This makes it possible to planarize the gate electrode 16 and the upper surface of the insulating layer. 94452 10 200926420 Referring to the 7th and 7th drawings, the guest's gongs, 丄 (4) sound 32 are formed on the idle electrode Μ and the insulating layer 32. Referring to the redundancy diagram, the area corresponding to the expected line is removed (line B_石, 子疋16 shown in Fig. 1; 参第7A HI, 夕日日日日日 a and a gate electrode mai), 7A In the figure, the polycrystalline layer exists in the pre-region and is electrically connected to the gate electrode 16. It becomes the intersection of the word line 34 of the sub-70 line. Thereafter, the crucible is "diffusion £ plug metal" (Piugmetal) And a semiconductor device of the A & y insulating film, the layer 4 is formed to produce the same material as the first insulating film 12 according to the fourth embodiment. Referring to FIG. 4C, depending on the non-face etching, the etched gate insulator "no film" 2 side edge film u of the chemical ^ door edge == 疋 4 hand is not engraved the first is absolutely the gate The insulating film 12 is reported by the yttrium oxide film, and the first and the insulating film U are formed by oxidation, and the liquid is used for side etching of the gate insulating film Χ + 4 Β in the figure, so that the door (four) describes the step towel, the rhyme carving For example, the first electrode is used to etch the electrode between the electrode and the first insulating film. For example, the etching in the 4th Yuangu Valley is allowed to be insulated. 12 using the interpole electrode 16 as a mask for use, stacking between the pole electrode 16 and the mth large side surface. This method is selectively removed. The first insulating film 14 and the gate insulating film u are as described. As shown in Fig. 4C, & 18 ± square ^ ^ Since the first insulating film is present above the undercut, the first and '2 cores are as shown in Fig. 5A. The edge films 14 and 22 form an upper insulating film. χ No. The insulating germanium 20 is formed through the ald process so that the tunnel insulating film 21 is depleted in _, ^ degrees. As a result, the upper insulating film 2t 22 has substantially the same thickness, and thickness (by adding the first sum) The second insulation 94452 11 200926420 ·: 3 thickness of the resulting film thickness) (4) to make a large (four) ... degrees - so, the upper insulating film = 1 thick conductor substrate i, + / ^ _ electrode 16 formed in half咕Λ As shown in Fig. 7. From Fig. 7 Δ, the gate insulating film 12 forms a Α diagram and 0/| Among the gate electrodes i6, on the sub-plate 10, the first insulating film 14i, the square, and the semiconductor base film 14 are formed to extend from the gate insulating film 12iFh to the gate. The lower end of the pole 16 (on the word (four) 12 on the Q-domain extension of the two ends of the 16) lower region. First, the edge of the membrane 4 is made of a different material from the gate electrode. The tunnel (four) t is connected to the gate insulating film 12 The dummy pad is formed on the semiconductor substrate 10 (four) and the first insulating film 14 is electrically: the reservoir 226 is interposed under the tunnel insulating film - and the charge storage m film 22 is formed on the first insulating film 21 by the same The material is made of the mother-insulating film 22 and the on-channel insulating film 21 for the material to be blocked. The layer 26 is large. For example, when a hydrogen oxidizing film is used to form the tracking insulating mold 21, the charge storage layer 26 may be formed of yttrium oxide. Referring to Fig. 5A, before the formation of the insulating film (9) by the ALD process, a thin oxide film having a thickness of about 1 nm can be formed on the semiconductor substrate, so that the quality of the tunnel insulating film 21 formed of the insulating film 2 can be improved. 94452 12 200926420 A second embodiment of the present invention. In the second embodiment, the upper insulating film is formed of a first insulating film. Referring to: Fig. 8A, performing the process steps according to the fourth embodiment to the fourth embodiment (the first embodiment shown in the drawing. Referring to Fig. 8B, the thermal oxidation process is used to form the insulating film 20a formed of the hafnium oxide film. To cover the upper surface of the semiconductor substrate 1 and the interpolar electrode. The thermal oxidation process is not allowed for the insulating film; 20a 4 is formed under the first insulating film 14 and on the side surface of the hard insulating film i2, the insulating film 2〇a The thickness can be set, for example, to 5 nm. The tracking insulating film is formed by the insulating film on the semiconductor substrate 1 in the undercut portion 18. The storage layer 26a formed of the nitrogen (tetra) film is formed by referring to the 'transmission CVD process, so that The undercut portion 18 is filled and covered with the insulating material. Therefore, the first insulating film 14 is directly formed on the charge storage layer, and the layer 28a is formed of the tunnel insulating film 2U and the charge storage layer layer 24a. _ 、 、 、 、 、 、 、 第 第 第 第 第 第 第 第 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 ' ' ' ' ' ' ' ' ' ' ' ' Depends on the formation of the road, does not require the second to be formed The insulating film 21. The tunnel insulating film 21 can be formed at the same time as the second insulating film 22 formed as shown in Fig. 5 = in the first embodiment 'When the gate insulating film 12 is formed of an oxidized oxide film 2: The first insulating film 14 is formed of an oxidized film to obtain a side etching of the material in the drawing of Fig. 4C. When a film of the same material as that of the first insulating film (four) is required to form an upper insulating layer When the film is %, the 'insulating film 汕 (also known as 94452 13 200926420:: insulating film 21) is desirably formed by oxidizing the film. Meanwhile, in the second: □, any material may be selected to form the track insulating film 21a. = End use can form a oxidized film of a superior insulating film such as a tunnel insulating film 21a. +; The actual & 例例" When the 甩 铭 铭 膜 膜 膜 膜 膜 膜 膜 膜Cerium oxide having a gap smaller than the energy gap of alumina is used to form electricity $=2: In the second embodiment, when the oxide is used to form, the nitrogen film which is easy to manufacture can be used to form a charge reservoir; In one embodiment, the thicknesses of the upper insulating film 24a and the tracking insulating film 21a may be individually set. When the thickness of the insulating film 14 (i.e., the upper insulating film 24a) is made larger than the thickness of the tunnel insulating film 21a, the tunnel insulating film 21a allows a tunnel current to flow therethrough, and the upper insulating film 2b has a charge sufficient to hold the charge storage layer 26a. The thickness of the retention. Second Embodiment In the third embodiment, the first and second insulating films are formed of different materials. Referring to FIG. 10A, the first embodiment shown in FIGS. 4A to 4C is performed. Process steps: Referring to Fig. 10B, an insulating film 20b formed of yttrium oxide is formed through an ALD process so as to cover the inner surfaces of the undercut portion 18 and the gate electrode W. The thickness of the insulating film 20b can be set to $ nm. The tracking insulating film 21b is formed of an insulating film 2?b on the semiconductor substrate 1 in the undercut portion 18. The insulating film 2〇b under the first insulating film 14 in the undercut portion 18 becomes the second insulating film 22b. The upper insulating film 24b is formed of the first and second insulating films 14 and 22b. A dielectric layer formed of a tantalum nitride film is formed by a CVD process to fill the undercut portion 18 and cover the insulating film 20b. Then, a laminate 28b of a tunnel insulating film 21b, a charge storage layer 26b, and an upper insulating film, 24b is formed inside the undercut portion 18. Referring to Fig. 1c, the manufacturing steps according to the first embodiment shown in Figs. 5C to 7B are performed to produce the semiconductor device according to the third embodiment. In the third embodiment, the aluminum oxide film is used to form the first insulating film, and the oxidized film is used to form the gate insulating film 12. Referring to the figure, the first insulating film 14 can be made of an oxygen film having superior film quality in the first to third embodiments. The charge storage layer % can be a conductor such as =. When the charge storage layer 26 is formed by a conductor and disposed in the ς character direction :::, as shown in Fig. 7 , the charge storage layer 26 extending from the body cell 4 in the extension of the diffusion region 30 is electrically (tetra). When you become a charge storage layer, perform the remove word as a step. In this way, the ruthenium oxide, the ruthenium layer, and the ruthenium film (for example, polycrystalline π j 用 用 形成 形成 形成 储 储 储 储 储 储 储 储 储 储 储 储 储 储 储 ( ( ( ( ( ( ( The insulating layer 26 is used. The insulating film using the conductor nitride nitride film can be used, for example, by oxidizing the intermediate charge storage layer. The partial layer is omitted to omit the preferred embodiment of the word line, but While the invention is in the spirit of the invention, various modifications may be made and the invention has been described in detail above and is not limited by the specific embodiments of the invention, as defined in the scope of the patent application, the reference number 94452 15 200926420 Change. ... [Simple description of the drawing], ,1 is a plan view of the flash memory according to the comparative example and the first to third examples of the present invention; ~ a 2A to 2C chart is displayed according to The comparative example corresponds to the step of manufacturing the flash memory along the line AA (part 1) shown in the figure; the 3A to 3C diagrams show the line AA along the line i in the figure according to the comparison example (part 2) The steps to make a flash memory; ❹ The 4th to 4C figure shows the root According to the first embodiment, the steps of manufacturing the flash memory along the line AA (part 1) shown in the i-th figure are shown; the 5A to 5C charts show the line AA corresponding to the line shown in the figure according to the first embodiment. (Part 2) a step of manufacturing a flash memory; FIG. 6 is a cross-sectional view showing a step of manufacturing a flash memory according to the line AA (Part 3) shown in the first embodiment according to the first embodiment; 7A and 7B are diagrams showing the steps of manufacturing a flash memory according to the first embodiment, wherein FIG. 7A is a cross-sectional view corresponding to a section along the line shown in FIG. 1, and FIG. 7B is a corresponding section. A cross-sectional view of a cross section of the line shown in Fig. 1; Figs. 8A to 8C show steps of manufacturing a flash memory corresponding to the line AA (part 1) shown in Fig. 1 according to the second embodiment; FIG. 10A to FIG. The step of manufacturing a flash memory by the line AA shown in Fig. 1 16 94452 200926420 [Description of main component symbols] 10 矽 substrate 12 gate insulating film 14 first insulating film 16 gate electrode 18 undercut portion 20, 20a, 20b insulation 21, 21a, 21b tunnel insulating film 22, 22b second insulating film 23 on second insulating film 24, 24a, 24b Insulating film 26, 26a' 26b charge storage layer 28, 28a, 28b laminate 30 diffusion region 32 insulating layer 34 word line 36 dummy layer 38 first insulating film 40 upper insulating film 44 channel region Ο 17 94452