201248855 六、發明說明： 【發明所屬之技術領域】 本發明係關於一種鰭式場效電晶體結構，以及形成多種 鰭式場效電晶體結構的方法。本發明特別是關於一種使用形 成氧化物的不同可能來建構鰭式場效電晶體的方法，用來降 低鰭式場效電晶體漏電流問題，或是增加散熱的解決方案。 【先前技術】 半導體產業持續研發之重要目標，係在於增加半導體元 件的效此’以及減少半導體元件之功率消耗。在增加半導體 元件效能此一途徑上，習知技術已開發出利用有利於電洞或 電子流動的不同晶面定向來提升元件效能。 舉例來說，建構於（1〇〇)矽晶面上的η型通道(n-channel> 金氧半導體(metal-oxide-semicomhictor，MOS)電晶體元件可 獲得較高的載子遷移率；而建構於（110)矽晶面上的p型通道 (p_chaimel)MOS電晶體元件則獲得較高的載子遷移率。因 此習知技術在建構平面式(planar)互補式（c〇mplementary)金 氧半導體電晶體元件(CMOS device)時，曾有利用基板結合 技術等方式，將具有不同晶面定向的矽層製作成基板結構， 並將η型通道MOS電晶體元件成長於（1〇〇)晶面，以及將p 型通道MOS電晶體元件成長於（11〇)晶面，以增進cmos元 201248855 件的電性表現。 然而，隨著元件發展進入65奈米技術世代後，使用傳 統平面式的MOS電晶體製程實難持續微縮。因此，習知技 術係提出以立體多閘極電晶體元件如鰭式場效電晶體(Fin Field effect transistor，FinFET)元件取代平面電晶體元件之解 決途徑。然而，由於鰭式場效電晶體的底部與基材直接相 連，所以在操作時有嚴重漏電流的問題。另一方面，若是想 要解決漏電流的問題而將鰭式場效電晶體建立在絕緣層覆 矽基板（SOI substrate)，則會因為絕緣層覆矽基板（s〇I substrate)的高昂價格增加生產成本。 因此，目前仍需要可解決上述兩難的多閘極電晶體元件 結構及其之製作方法。 【發明内容】 本發明於是提出一種形成多樣鰭式場效電晶體結構的 方法，以得到多種可以滿足不同需求之鰭式場效電晶體結 構。本發明運用形成氧化物的不同可能性，就可以來建構 同結構之鰭式場效電晶體。一方面，本發明方法可以無需使 用昂貴之絕緣層覆矽基板，就可以形成位於絕緣層上之鳍弋 場效電晶體結構，而具有絕緣層之頂面與底面其中之至少二 者不平坦之結構特徵。另一方面，本發明方法還可以形成具 4 201248855 有以瓶頸部而與基材直接相連之鰭式結構。此等瓶頸部既可 以降低鰭式場效電晶體漏電流的問題，同時又不干擾鰭式場 效電晶體的散熱問題。 本發明首先提出一種鰭式場效電晶體結構，其包含基 材、鰭式結構、絕緣層與閘極結構。絕緣層覆蓋基材，並具 有頂面以及與基材直接接觸之底面，其中頂面與底面之至少 一者不平坦。鰭式結構則位於絕緣層上，並包含鰭式導體層 與一組源極/汲極。閘極結構則部分包圍鰭式結構，而包含一 閘極導電層與包圍鰭式結構之一閘極介電層。 在本發明一實施例中，絕緣層包含複數個u形底面，使 得鰭式結構位於相鄰之u形底面之間。在本發明另一實施例 中，鰭式場效電晶體結構更包含覆蓋鰭式導體層之帽蓋層。 在本發明又一實施例中，鰭式結構具有圓鈍化之頂角。在本 發明再一實施例中，絕緣層實質上不含應力。 本發明其次提出一種鰭式場效電晶體結構，其包含基 材、鰭式結構、絕緣層與閘極結構。鰭式結構位於基材上並 與基材直接相連。鰭式結構包含鰭式導體層與瓶頸部。絕緣 層則覆蓋基材，並具有部分圍繞鰭式結構之瓶頸部而形成之 一凸出側面，以及與基材直接接觸之底面。凸出側面延伸至 鰭式結構下方。閘極結構部分包圍鰭式結構，又包含一閘極 201248855 導電層與包圍鰭式結構之一閘極介電層。 在本發明一實施例中，鰭式場效電晶體結構更包含位於 絕緣層下方之淺溝渠隔離。此等淺溝渠隔離具有與絕緣層直 接接觸之頂部，而且絕緣層之底面還大於淺溝渠隔離之頂 部° 本發明又提出一種形成鰭式場效電晶體結構的方法。首 先，提供一基材與位於基材上之鰭式結構。鰭式結構包含遮 罩層、緩衝層、帽蓋層、縛式導體層與環繞遮罩層、緩衝層、 帽蓋層、鰭式導體層之一側壁子。其次，進行包含橫向蝕刻 步驟與縱向蝕刻步驟之基材蝕刻步驟，而在基材中形成第一 凹六以及與第一凹六相連之第二凹穴，第一凹穴與第二凹穴 其中之至少一者具有延伸至鰭式結構下方之一凸出側面。之 後，形成填滿第一凹穴與第二凹穴之氧化層。繼續，形成部 分包圍鰭式結構之閘極結構。 在本發明一實施例中，橫向蝕刻步驟可以在縱向蝕刻步 驟之前或是之後進行。在本發明另一實施例中，係使用爐管 氧化法以氧化基材而形成所需之氧化層。在本發明又一實施 例中，橫向蝕刻步驟會在鰭式結構中形成所需之瓶頸部。在 本發明再一實施例中，瓶頸部之寬度為鰭式結構寬度之40% -60%。 6 201248855 【實施方式】 本發明係提供一種形成多樣鰭式場效電晶體結構的方 法，以得到多種可以滿足不同需求之縛式場效電晶體結構。 在本發明方法中，形成氧化物方式的不同，就可以來建構不 同結構之鰭式場效電晶體。一方面，本發明方法可以無需使 用昂貴之絕緣層覆石夕基板（SOI substrate )，就可以得到位於 絕緣層上之鰭式場效電晶體結構，而具有絕緣層之頂面與底 面其中之至少一者不平坦之結構特徵。另一方面，本發明方 法還可以形成，以瓶頸部而與基材直接相連之鰭式結構，所 以既可以降低鰭式場效電晶體漏電流的問題，同時又不影響 鰭式場效電晶體的散熱問題。 第1圖至第8B圖繪示本發明形成多樣鰭式場效電晶體 結構的方法，以得到多種可以滿足不同需求之縛式場效電晶 體結構。本發明形成鰭式場效電晶體結構的方法，首先，如 第3圖所示，提供基材101與位於基材101上之至少一鰭式 結構110。鰭式結構110包含遮罩層111、緩衝層112、帽蓋 層113、鰭式導體層117與側壁子114。 形成鰭式結構110的方法可以如下所例示。首先，如第 1圖所示，在基材101上提供遮罩層111、緩衝層112與帽 蓋層113。帽蓋層113可以包含氮氧化矽，並使用例如沉積 7 201248855 法，整體性地覆蓋基材101。然後在帽蓋層113上，使用例 如沉積法，形成包含矽氧化物之緩衝層112。接著，在緩衝 層112上形成圖案化之遮罩層111，使得遮罩層111具有定 義鰭式結構110的圖案。遮罩層111可以為硬遮罩，例如包 含氮化矽之硬遮罩。形成圖案化遮罩層111的方法可以是， 使用蝕刻法，將預先圖案化光阻（圖未示）之圖案，轉移至 遮罩層111中。 其次，如第1圖所示，使用圖案化遮罩層111作為一蝕 刻遮罩，而進行一鰭式結構蝕刻步驟。鰭式結構蝕刻步驟會 移除部份之緩衝層112、帽蓋層113與基材101，而界定出 鰭式結構110大致的結構。帽蓋層113下方部份之基材101 於是成為鰭式導體層117。可以使用乾蝕刻法來進行鰭式結 構蝕刻步驟。例如，利用CF4、02與He來對緩衝層112和 帽蓋層113進行乾蝕刻。另外，還可以使用HBr、02與He 對基材101進行乾蝕刻。 然後，如第2圖所示，在遮罩層111、緩衝層112、帽 蓋層111與基材101上全面性地形成一側壁材料層115，以 覆蓋先前所形成之材料層與鰭式導體層117。側壁材料層115 可以包含氮化矽。視情況需要，在沉積側壁材料層115之前， 還可以先形成以氧化物為主之另一緩衝層119，使得緩衝層 119成為第二側壁材料層，而側壁材料層115成為第一側壁 8 201248855 材料層。 • 接下來，就可以如第3圖所示，進行一側壁蝕刻步驟， 而移除部份之側壁材料層115，與視情況需要之緩衝層119。 最後得到可以保護鰭式導體層117之側壁子114，與前述之 鰭式結構110。換言之，側壁子114會包含側壁材料層115 與視情況需要之緩衝層119。另外，側壁子114會環繞遮罩 層111、緩衝層112、帽蓋層113與鰭式導體層117。側壁蝕 刻步驟還可能會移除部份之鰭式結構110，而得到圓鈍化之 頂角（corner-rounded) 116。 繼續，如第4圖與第5圖所示，利用遮罩層111與側壁 子114當作遮罩，進行一基材#刻步驟，而在基材101中形 成一第一凹穴103以及與第一凹穴103相連之第二凹穴 102。第一凹穴103與第二凹穴102之位置係相對的，例如 第二凹穴102會環繞第一凹穴103。形成第一凹穴103與第 二凹穴102基材蝕刻步驟並非單一之蝕刻步驟，通常包含多 次之蝕刻過程，而分別建立所需之第一凹穴103與第二凹穴 102。 例如，基材蝕刻步驟包含至少一次之橫向蝕刻步驟與至 少一次之縱向蝕刻步驟。由於本發明橫向蝕刻步驟與縱向蝕 刻步驟之順序並非關鍵，所以可以視情況需要，先進行橫向 201248855 姓刻步驟或是先進行縱向蝕刻步驟其中之一，再進行另一次 所需之蝕刻步驟。 本較佳實施例可以先進行縱向蝕刻步驟，如第4圖所 示’來建立第一凹六103。例如，使用3卩6與He來對基材 101進行乾蝕刻，移除暴露之基材1〇1，而形成所需尺寸之 第一凹穴103。例如’從侧壁子114往下再移除5nm〜100nm。 隨後，如第5圖所示，使用乾蝕刻法，或是乾蝕刻法配合濕 姓刻法進行橫向触刻步驟，形成所需之第二凹穴102，同時 在鰭式結構110之下方形成瓶頸部1〇4。例如，乾蝕刻法利 用SF$與He來對基材101進行乾蝕刻。或是，濕蝕刻法利 用氨水(NH3)與低濃度雙氧水汨2〇2)來對基材1〇1進行濕蝕 刻。請注意，第二凹穴102較佳為楔形，亦即其係沿者特定 矽晶面進行蝕刻而形成凸出側面1〇5延伸至鰭式結構11〇之 下方。當然亦可以先進行橫向蝕刻步驟，如第5A圖所示可 考慮結合6B。視情況需要，瓶頸部1〇4之寬度可以介於3 微米（μιη)與1〇微米之間，或是瓶頸部1〇4之寬度為鰭式 結構110寬度之40% - 60%。 接下來’要形成填滿第一凹穴1〇3與第二凹六1〇2之氣 化層。可以使用不同的方法來形成氧化層❶使用不同的方 法，所形成的氧化層結構可能不同，使得最終鰭式場效電晶 體的結構亦不同。 201248855 在本發明一第一實施方式中， 110^ ^ jn- m, ^ A 會形成元全支撐鰭式結構 ^之氧化層1參考第6A圖’在完成所需之第一凹穴ι〇3 ==二以使用氣化法來形成完全支輯 。例如’使用爐管氧化法來氧化被曝 露的基材HH，亦即氧化鄰近.鳍式結構ΐι〇、第一凹穴⑻ =二1〇2的基材101中以原子，以形成包含氧化碎 二媒 化層120 ’可以作為隔離基材101與轉 “構m之-場氧化層。氧化層12〇之厚度可以為 l〇nm〜20〇nm。此時，_部1〇4即因氧化法而消失。 由於氧原子被引人的緣故’氧化層120會填滿第二凹六 1〇2’並幾乎占據大部份之第一凹穴1〇3,而僅僅殘留 第一心心另外’因為石夕原子被直接氧化的緣故，氧化 層120曰呈現不甚平坦的頂面121與底面m，而與使用沉 積法來形成的平坦表面（圖未示）有所不同，而且氧化層12〇 實質上不含應力。 由於遮罩層11卜緩衝層112、側壁子114的功能是用 來保護鰭式結構11G，不被_或是氧化步驟所傷害，因此， 在完成上賴刻或是―之後，就可以移除側壁子 114、遮罩層hi與緩衝層112，如第7a圖所示。例如，使 用濕㈣步驟來移_壁子114。如果側壁子ιΐ4包含第一 201248855 側壁材料層與第二側壁材料層，移除側壁子ιΐ4即—併移除 第一側壁材料層與第二側壁材料層。 ’會形成完全覆蓋縛式結構 在完成所需之第一凹穴1〇3 在本發明一第二實施方式中 110之氧化層。請參考第6B圖， 與第二凹穴H)2後，就可以使用沉積法來形成完全覆蓋韓式 結構no、並填滿第一凹穴103與第二凹穴1〇2之氧化層 120，而不氧化基材1 〇 1中之石夕原子。 例如，使用旋轉塗佈法（Spin_〇nDielectric，s〇D)，而 在晶圓表面雜塗佈含二氧切之液藝f，_液體高度 填補縫隙％力’達成良好的覆蓋性。然後在液化狀態與以高 溫退火，即可將液化物質轉變成固態氧化層，也可以使用沉 積法來形成完全覆蓋鰭式結構11〇 '第一凹穴1〇3與第二凹 穴102之氧化層12〇，使得絕緣層12〇可以包含氧化物，例 如一氧化矽或者氧氮化矽。請注意，由於沒有矽原子被氧化 的緣故’鰭式結構11〇仍直接與基材1〇1相連。視情況需要， 在沉積法之前’還可以在第一凹穴103與第二凹穴102之内 壁上’預先形成一襯墊層1〇9。可以經由氧化基材ι〇1而形 成襯墊層109。襯墊層109可以用來弭平因為蝕刻步驟而粗 化之基材101表面，另外還可以修補晶格結構以減少漏電流。 接下來’請參考第7B圖，會進行一化學機械研磨（CMP) 12 201248855 與回钱刻（pull back )步驟’經由製程控制（process contr〇i) 削減掉部份之氧化層120，使得氧化層120之外表面與側壁 子114之底部直接接觸約略切齊。氧化層12〇於是恰好填滿 第-凹穴103與第二凹力1〇2，但是又完全暴露出鰭式結構 110 可以使用之乾㈣條件可以為CF4+02與Ar，濕飯刻 條件可以是稀釋氫1酸，來進行此㈣刻（pullbaek)步驟。 填滿第一凹穴103之氧化層120’因為深入基材中，還可以 視為半導體元件常用之淺溝渠隔離。 由於遮罩層111、緩衝層112、側壁子114的功能是用 來，護鰭式結構11〇,不被_或是氧化步驟所傷害，因此， 在完成上祕刻或是氧化步驟之後，例如氧化層120填滿第 凹八103與第一凹穴102之後，即可以移除遮罩層111、 緩衝層m、側壁子114。如果側壁子114包含第一側壁材 料層與第二側壁材料層’移除側壁子m即-倂移除第一側 壁材料層與第二側壁材料層。 -在、&過上述氧化層形成步驟後，雖然會形成截然不同之 氧化層120 ’但是並不#影_續要進行之閘極結構形成步 驟在移^側壁+ 114之後，就可以形成所需之問極介電層 3先月』第7A圖之結構如今即成為第8A圖所示之結構。 又’視情況需要，也可以移除帽蓋層113，於是第7B圖之 、.口構如”即成為第8B圖所示之結構。間極介電層I”可以 13 201248855 是-般之介電材料，例如高品質之氡化 之介電材料，例如Hf〇2或HfZK)七v次疋…丨電常數 •或或Zr〇2或_或 ⑶之方法，為本技兹人士 2 3二形成所需閉極介電層 ”人士之通常知識，故不多加贅述。 之後，即形成位於鰭式結構U〇 構削之間極結構130。無論是第’而來控制鰭式結 第8B圖所示之結構，都二15所示之結構，或是 偁邵了以形成閘極結構13〇，使 圖之結構如今即成為第9A圖 )ΛΛ , θ ^ 〇 之鰭式％效電晶體結構 ，或疋第8Β圖之結構如今成為第 電晶體結構100。 瑪式场效 例如，先在閘極介電層131之上全面τ 再使用触刻方法來界定閘極材料層m。如果帽蓋層 留下來閉極介電層131即會直接接觸帽蓋層⑴。如 果帽蓋層⑴被移除，閘極介電層131即會直接圍繞鳍式結 構110最後，圖案化閘極介電層131與問極材料層m 一 起成為閘極結構13〇,於是便完成了本發明形成多樣 效電晶體結構的方法。 ％ 本發明方法可以得到至少兩種鰭式場效電晶體的結構。 首先’如第9A圖所示，在本發明—第一實施例中，提 供一種·㈣式場效電晶體結構_。本發明第-實施例之鰭式 201248855 場效電晶體結構100，包含基材101、轉气狂 120與閘極結構130。基材101通常是一Χ、、、。構110、絕緣層 如石夕，並可以在適當之情形下氧化而形半導體基材，例 係由基材1〇1中之矽原子直接氧化而得，因化矽。絕緣層120 的絕緣層120會直接覆蓋基材101。因此，此整片（bulky) 電晶體結構100無需使用成本較高之砂本發明鰭式場效 基板 ’復絕緣（son 而具有生產成本上之優勢。 ^ 絕緣層120本身具有頂面121以及與美从 兴暴材101直接接觸 之底面122。由於絕緣層120係由基材101中之矽原子直接 氧化而得’因此頂面121與底面122之至少一者並不平坦， 例如，絕緣層120包含複數個U形底面122，而與使用沉積 法來形成的平坦表面（圖未示）有所不同。而且，絕緣層12〇 也因此實質上不含應力。 鰭式結構11 〇則位於絕緣層12 0上，並包含鳍式導體層 117與位於鰭式導體層117兩側之一組源極/沒極118。較佳 者’鰭式結構110的上面會有圓純化之頂角（rounded corner) 116。本發明鰭式場效電晶體結構loo中，可以包含不只一 個鰭式結構110，因此鰭式結構11〇還可以位於相鄰之U形 底面122之間。鰭式結構110之鰭式導體層in原本為基材 101之一部份’但是因為絕緣層120的阻隔，而與基材1〇1 完全分開。視情況需要’鰭式結構11 〇之中還可以包含覆蓋 15 201248855 其可以包含氮氧石夕化物。 鰭式導體層117之帽蓋層113， 閘極、，構13G則從二個方向部分包關式結構ιι〇，並 包含包圍鰭式結構之閘極介電層131與閘極材料層⑴。延 申之閘極、'，。構13G通常形成連續之u形，可以同時控制多組 ^讀式結構110 °如果移除帽蓋層113,閘極結構130則會 從一個方向控制鰭式結構UG。如果保留帽蓋層⑴，問極 結構130則從兩個方向控制鰭式結構n〇。 β其次’如第9B圖所示，在本發明—第二實施例中，又 提供另-賴式場效電晶體結構L本發明第二實施例之 鰭式場效電晶體結構1()〇，包含基材1(η、鰭式結構u〇、絕 緣層㈣與閘極結構13〇。基材1〇1通常是一種半導體基材， 例如矽。較佳者’鰭式結構11〇的上面會有圓純化之頂角 ⑽。視情況需要，鰭式結構11G之中還可以包含覆蓋韓式 導體層U7之帽蓋層113，其可以包含氮氧魏物。如果間 極結構13G會從三個方向控制·鰭式結構m，則移除帽蓋層 113。如果閘極結構130從兩個方向控制鰭式結構ιι〇,則保 留帽蓋層113。絕緣層12〇實質上不含應力。 本發明第二實施例與本發明第一實施例之差異在於本 發明第二實施例中之絕緣層12〇係以沉積之方式，填入鰭式 結構110附近，於是位於基材101中之第一凹穴1〇3與第二 16 201248855 凹穴102中，而非整片覆蓋基材101。絕緣層120可以包含 二氧化矽或者氧氮化矽。如第5圖所示，第二凹穴102較佳 為楔形，其凸出側面105延伸至鰭式結構11〇之下方’因此 在鰭式結構110中形成一瓶頸部104。 鰭式結構110即藉由瓶頸部104與基材1〇1直接相連， 咣保留散熱功能，又可以減低漏電流。視情況需要，瓶頸部 1〇4之寬度可以介於3微米（μπ〇與10微米之間，或是瓶 頸部104之寬度為鰭式結構110寬度之40%-60%。還有， 视情況需要，本發明第二實施例之鰭式場效電晶體結構100 還可以包含襯墊層109。襯塾層109即位於淺溝渠隔離122 與基材101之間，以及絕緣層120與鰭式結構110之間。 填滿第一凹穴103與第二凹穴102中之絕緣層120不僅 覆蓋基材101，並具有部分圍繞鰭式結構110之瓶頸部104 而形成之一凸出側面105，以及與基材101直接接觸之底面 122。凸出側面1〇5延伸至鰭式結構11〇下方。 填滿之第一凹穴103因為深入基材中，還可以獨立地視 為位於填滿第二凹穴102之絕緣層120下方，作為半導體元 件常用之淺溝渠隔離122之用。此等淺溝渠隔離122具有與 絕緣層120直接接觸之頂部123,因此絕緣層120之底面121 遨大於淺溝渠隔離122之頂部123。 17 201248855 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍 所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。 【圖式簡單說明】 第1圖至第8B圖繪示本發明形成多樣鰭式場效電晶體 結構的方法。 第9A圖繪示本發明一種鰭式場效電晶體結構。 第9B圖繪示本發明另一種鰭式場效電晶體結構。 【主要元件符號說明】 100鰭式場效電晶體結構 101基材 102第二凹六 103第一凹穴 104瓶頸部 105凸出側面 109襯塾層 110鰭式結構 111遮罩層 112緩衝層 113帽蓋層 114側壁子 18 201248855 115側壁材料層 116頂角 117鰭式導體層 118源極/汲極 119緩衝層 120氧化層 121頂面 122底面 130閘極結構 131閘極介電層 132閘極材料層201248855 VI. Description of the Invention: [Technical Field] The present invention relates to a fin field effect transistor structure and a method of forming a plurality of fin field effect transistor structures. More particularly, the present invention relates to a method of constructing a fin field effect transistor using different possibilities of forming an oxide to reduce the leakage current of the fin field effect transistor or to increase the heat dissipation solution. [Prior Art] The important goal of the continuous development of the semiconductor industry is to increase the efficiency of semiconductor components and to reduce the power consumption of semiconductor components. In a way to increase the performance of semiconductor components, conventional techniques have been developed to enhance component performance by utilizing different plane orientations that favor hole or electron flow. For example, an n-channel (n-channel> metal-oxide-semicomhictor (MOS) transistor component constructed on a (1) tantalum plane can achieve higher carrier mobility; The p-channel (p_chaimel) MOS transistor component constructed on the (110) twin plane achieves higher carrier mobility. Therefore, the conventional technique is to construct a planar complementary (c〇mplementary) gold oxide. In the case of a semiconductor CMOS device, a germanium layer having a different crystal plane orientation is formed into a substrate structure by means of a substrate bonding technique, and an n-type channel MOS transistor element is grown in (1 Å) crystal. And the p-channel MOS transistor element is grown on the (11〇) crystal plane to enhance the electrical performance of the cmos element 201248855. However, as the component develops into the 65nm technology generation, the traditional planar type is used. The MOS transistor process is difficult to continue to shrink. Therefore, the conventional technology proposes a solution to replace the planar transistor component with a three-dimensional multi-gate transistor component such as a Fin Field effect transistor (FinFET) component. Since the bottom of the fin field effect transistor is directly connected to the substrate, there is a problem of serious leakage current during operation. On the other hand, if the problem of leakage current is to be solved, the fin field effect transistor is built on the insulating layer. The substrate (SOI substrate) increases the production cost due to the high price of the insulating layer substrate. Therefore, there is still a need for a multi-gate transistor device structure and a method for fabricating the same. SUMMARY OF THE INVENTION The present invention therefore proposes a method for forming a plurality of fin field effect transistor structures to obtain a plurality of fin field effect transistor structures that can meet different needs. The present invention can be constructed by using different possibilities of forming oxides. The fin field effect transistor of the same structure. On the one hand, the method of the invention can form the fin field effect transistor structure on the insulating layer without using an expensive insulating layer covering the substrate, and has the top surface of the insulating layer and Structural features in which at least two of the bottom surfaces are not flat. On the other hand, the method of the present invention can also be formed with 4 20124885 5 There is a fin structure directly connected to the substrate by the neck portion. These bottle neck portions can reduce the leakage current of the fin field effect transistor without disturbing the heat dissipation problem of the fin field effect transistor. A fin field effect transistor structure comprising a substrate, a fin structure, an insulating layer and a gate structure. The insulating layer covers the substrate and has a top surface and a bottom surface in direct contact with the substrate, wherein at least the top surface and the bottom surface One is not flat. The fin structure is located on the insulating layer and contains a finned conductor layer and a set of source/drain electrodes. The gate structure partially surrounds the fin structure and includes a gate conductive layer and a gate dielectric layer surrounding the fin structure. In an embodiment of the invention, the insulating layer includes a plurality of u-shaped bottom surfaces such that the fin structures are between adjacent U-shaped bottom surfaces. In another embodiment of the invention, the fin field effect transistor structure further comprises a cap layer covering the fin conductor layer. In yet another embodiment of the invention, the fin structure has a rounded passivation apex angle. In still another embodiment of the invention, the insulating layer is substantially free of stress. The present invention secondly proposes a fin field effect transistor structure comprising a substrate, a fin structure, an insulating layer and a gate structure. The fin structure is located on the substrate and is directly connected to the substrate. The fin structure includes a finned conductor layer and a neck portion. The insulating layer covers the substrate and has a convex side formed partially around the neck portion of the fin structure and a bottom surface in direct contact with the substrate. The convex side extends below the fin structure. The gate structure partially surrounds the fin structure and further includes a gate 201248855 conductive layer and a gate dielectric layer surrounding the fin structure. In an embodiment of the invention, the fin field effect transistor structure further comprises shallow trench isolation under the insulating layer. The shallow trench isolation has a top portion in direct contact with the insulating layer, and the bottom surface of the insulating layer is larger than the top portion of the shallow trench isolation. The present invention further provides a method of forming a fin field effect transistor structure. First, a substrate and a fin structure on the substrate are provided. The fin structure includes a mask layer, a buffer layer, a cap layer, a bound conductor layer and a surrounding mask layer, a buffer layer, a cap layer, and a sidewall of the fin conductor layer. Next, performing a substrate etching step including a lateral etching step and a longitudinal etching step, and forming a first concave six in the substrate and a second concave portion connected to the first concave sixth, the first concave portion and the second concave portion At least one of the protrusions extends to a convex side below the fin structure. Thereafter, an oxide layer filling the first recess and the second recess is formed. Continuing, a gate structure partially surrounding the fin structure is formed. In an embodiment of the invention, the lateral etching step can be performed before or after the longitudinal etching step. In another embodiment of the invention, a furnace tube oxidation process is used to oxidize the substrate to form the desired oxide layer. In yet another embodiment of the invention, the lateral etching step forms the desired neck portion in the fin structure. In still another embodiment of the invention, the width of the neck portion is 40% - 60% of the width of the fin structure. 6 201248855 [Embodiment] The present invention provides a method of forming a plurality of fin field effect transistor structures to obtain a plurality of closed field effect transistor structures that can meet different needs. In the method of the present invention, fin-type field effect transistors of different structures can be constructed by different ways of forming oxides. In one aspect, the method of the present invention can obtain a fin field effect transistor structure on the insulating layer without using an expensive SOI substrate, and at least one of a top surface and a bottom surface of the insulating layer. Uneven structural features. On the other hand, the method of the invention can also form a fin structure directly connected to the substrate by the bottle neck portion, so that the problem of leakage current of the fin field effect transistor can be reduced, and the heat dissipation of the fin field effect transistor is not affected. problem. 1 to 8B illustrate a method for forming a multi-fin field effect transistor structure of the present invention to obtain a plurality of bound field effect transistor structures that can meet different needs. The method of forming a fin field effect transistor structure of the present invention, first, as shown in FIG. 3, provides a substrate 101 and at least one fin structure 110 on the substrate 101. The fin structure 110 includes a mask layer 111, a buffer layer 112, a cap layer 113, a fin conductor layer 117, and a sidewall spacer 114. The method of forming the fin structure 110 can be exemplified as follows. First, as shown in Fig. 1, a mask layer 111, a buffer layer 112, and a cap layer 113 are provided on a substrate 101. The cap layer 113 may comprise niobium oxynitride and integrally cover the substrate 101 using, for example, the deposition 7 201248855 method. A buffer layer 112 comprising tantalum oxide is then formed on the cap layer 113 using, for example, a deposition process. Next, a patterned mask layer 111 is formed on the buffer layer 112 such that the mask layer 111 has a pattern defining the fin structure 110. The mask layer 111 can be a hard mask such as a hard mask containing tantalum nitride. The method of forming the patterned mask layer 111 may be to transfer a pattern of a pre-patterned photoresist (not shown) into the mask layer 111 by an etching method. Next, as shown in Fig. 1, a patterned mask layer 111 is used as an etch mask to perform a fin structure etching step. The fin structure etching step removes a portion of the buffer layer 112, the cap layer 113, and the substrate 101 to define the approximate structure of the fin structure 110. The substrate 101 at the lower portion of the cap layer 113 thus becomes the fin conductor layer 117. The dry etching process can be used to perform the fin structure etching step. For example, the buffer layer 112 and the cap layer 113 are dry etched using CF4, 02, and He. Further, the substrate 101 may be dry etched using HBr, 02, and He. Then, as shown in FIG. 2, a sidewall material layer 115 is integrally formed on the mask layer 111, the buffer layer 112, the cap layer 111 and the substrate 101 to cover the previously formed material layer and the fin conductor. Layer 117. The sidewall material layer 115 may comprise tantalum nitride. Optionally, another buffer layer 119 mainly composed of an oxide may be formed before the sidewall material layer 115 is deposited, so that the buffer layer 119 becomes the second sidewall material layer, and the sidewall material layer 115 becomes the first sidewall 8 201248855 Material layer. • Next, as shown in FIG. 3, a sidewall etching step is performed to remove portions of the sidewall material layer 115, and optionally the buffer layer 119. Finally, a sidewall 114 that protects the finned conductor layer 117 is obtained, as well as the fin structure 110 described above. In other words, the sidewall sub-114 will include a sidewall material layer 115 and a buffer layer 119 as desired. In addition, the sidewall spacers 114 surround the mask layer 111, the buffer layer 112, the cap layer 113, and the fin conductor layer 117. The sidewall etching step may also remove portions of the fin structure 110 to obtain a corner-passed corner-rounded 116. Continuing, as shown in FIGS. 4 and 5, a masking step is performed using the mask layer 111 and the sidewall spacers 114 as a mask, and a first recess 103 is formed in the substrate 101 and The second pocket 103 is connected to the first pocket 103. The first pocket 103 is opposite the position of the second pocket 102, for example, the second pocket 102 will surround the first pocket 103. Forming the first recess 103 and the second recess 102 substrate etching step is not a single etching step, and typically involves multiple etching processes to establish the desired first pocket 103 and second pocket 102, respectively. For example, the substrate etching step includes at least one lateral etching step and at least one longitudinal etching step. Since the order of the lateral etching step and the longitudinal etching step of the present invention is not critical, one of the lateral steps of the 201248855 or the first longitudinal etching step may be performed as needed, and another required etching step may be performed. The preferred embodiment may first perform a longitudinal etching step, as shown in Figure 4, to create a first recessed six 103. For example, the substrate 101 is dry etched using 3卩6 and He to remove the exposed substrate 1〇1 to form the first recess 103 of the desired size. For example, '5 nm to 100 nm is removed from the side wall 114 downward. Subsequently, as shown in FIG. 5, a dry etching method or a dry etching method is used in conjunction with the wet etching method to perform a lateral etch step to form a desired second pocket 102 while forming a bottleneck below the fin structure 110. Department 1〇4. For example, the dry etching method uses SF$ and He to dry-etch the substrate 101. Alternatively, the wet etching method uses ammonia water (NH3) and low-concentration hydrogen peroxide 汨2〇2) to wet-etch the substrate 1〇1. It is noted that the second pocket 102 is preferably wedge-shaped, i.e., it is etched along a particular twin plane to form a convex side surface 1〇5 extending below the fin structure 11〇. It is of course also possible to carry out the lateral etching step first, as shown in Fig. 5A. The width of the neck portion 1〇4 may be between 3 μm and 1 μm, or the width of the neck portion 1〇4 may be 40% - 60% of the width of the fin structure 110, as the case requires. Next, a gasification layer filling the first recess 1〇3 and the second recess 6〇2 is formed. Different methods can be used to form the oxide layer. Different methods are used, and the oxide layer structure formed may be different, so that the structure of the final fin field effect transistor is also different. 201248855 In a first embodiment of the present invention, 110^^jn-m, ^ A will form a full-supported fin structure of the oxide layer 1 with reference to Figure 6A' in completing the required first recess ι 3 == two to use gasification to form a complete support. For example, 'the furnace tube oxidation method is used to oxidize the exposed substrate HH, that is, to oxidize the substrate adjacent to the fin structure 第一ι〇, the first recess (8)=2 〇2 to form atoms containing oxidized slag. The second dielectric layer 120' can be used as the isolation substrate 101 and the "oxidation layer". The thickness of the oxide layer 12 can be from 10 nm to 20 nm. At this time, the _ portion 1 〇 4 is oxidized. The law disappears. Because the oxygen atom is attracted, the oxide layer 120 fills the second concave hexa-2' and almost occupies most of the first cavity 1〇3, leaving only the first heart. Because the Shixi atom is directly oxidized, the oxide layer 120曰 exhibits a less flat top surface 121 and a bottom surface m, and is different from a flat surface (not shown) formed by deposition, and the oxide layer 12〇 It is substantially free of stress. Since the function of the mask layer 11 buffer layer 112 and the side wall 114 is to protect the fin structure 11G, it is not damaged by the _ or oxidation step, and therefore, Thereafter, the sidewall sub-114, the mask layer hi, and the buffer layer 112 can be removed, as shown in Figure 7a. For example, a wet (four) step is used to move the wall 114. If the sidewall ι 4 includes the first 201248855 sidewall material layer and the second sidewall material layer, the sidewall ι 4 is removed - and the first sidewall material layer and the second sidewall are removed The material layer 'will form a fully covered structure at the completion of the desired first recess 1 〇 3 in a second embodiment of the invention 110 of the oxide layer. Please refer to Figure 6B, with the second recess H) After 2, the deposition method can be used to form the oxide layer 120 which completely covers the Korean structure no and fills the first cavity 103 and the second cavity 1〇2 without oxidizing the stone atom in the substrate 1 〇1. For example, using a spin coating method (Spin_〇nDielectric, s〇D), a liquid crystal containing a dioxotomy is applied to the surface of the wafer, and the liquid height fills the gap % force to achieve good coverage. Then, in the liquefied state and annealing at a high temperature, the liquefied material can be converted into a solid oxide layer, or the deposition method can be used to form a completely covered fin structure 11 〇 'the first recess 1 〇 3 and the second recess 102 oxidize The layer 12 is such that the insulating layer 12 can contain oxides, for example For example, niobium monoxide or niobium oxynitride. Please note that because there is no niobium atom oxidized, the fin structure 11〇 is still directly connected to the substrate 1〇1. If necessary, before the deposition method, it can also be in the first A liner layer 1〇9 is formed in advance on the inner walls of the recess 103 and the second recess 102. The liner layer 109 may be formed via the oxidized substrate ι〇1. The liner layer 109 may be used for flattening because of the etching step. On the surface of the roughened substrate 101, the lattice structure can be repaired to reduce leakage current. Next, please refer to Fig. 7B for a chemical mechanical polishing (CMP) 12 201248855 and pull back steps. The portion of the oxide layer 120 is cut away by process control so that the outer surface of the oxide layer 120 is in direct contact with the bottom of the sidewall 114. The oxide layer 12 then just fills the first-cavity 103 and the second concave force 1〇2, but completely exposes the fin structure 110. The dry condition can be CF4+02 and Ar, and the wet cooking condition can be It is a dilution of hydrogen 1 acid to carry out this (four) engraving (pullbaek) step. The oxide layer 120' filling the first recess 103 can also be regarded as a shallow trench isolation commonly used for semiconductor devices because it penetrates into the substrate. Since the functions of the mask layer 111, the buffer layer 112, and the side wall sub-114 are used, the fin structure 11 is not damaged by the _ or oxidation step, and therefore, after completing the last etching or oxidation step, for example, After the oxide layer 120 fills the first recessed surface 103 and the first recess 102, the mask layer 111, the buffer layer m, and the sidewall sub-114 may be removed. If the sidewall sub-section 114 includes a first sidewall material layer and a second sidewall material layer, the sidewall spacer m is removed, i.e., the first sidewall material layer and the second sidewall material layer are removed. - After <& after the above oxide layer forming step, although a distinct oxide layer 120' is formed, but the gate structure forming step is not performed after the side wall + 114 is moved, the formation can be formed. It is necessary to ask the structure of the dielectric layer 3 first month, and the structure of the seventh embodiment is now the structure shown in Fig. 8A. In addition, the cap layer 113 can be removed as needed, so that the structure of the mouth is as shown in Fig. 8B. The inter-electrode layer I can be 13 201248855. Dielectric materials, such as high-quality dielectric materials such as Hf〇2 or HfZK) seven v times 丨... 丨 constants or or Zr 〇 2 or _ or (3) methods for the skilled person 2 3 Secondly, the general knowledge of the person who forms the required closed-electrode dielectric layer is not mentioned. After that, the pole structure 130 is formed between the fin structure and the U-shaped structure. The fourth step is to control the fin junction. The structure shown in the figure, the structure shown in Figure 2, or the structure of the gate is 13 〇, so that the structure of the figure is now 9A) ΛΛ , θ ^ 〇 fin type % effect transistor The structure, or the structure of Fig. 8 is now the first transistor structure 100. For example, first, over the gate dielectric layer 131, a etch method is used to define the gate material layer m. The cap layer leaves the closed dielectric layer 131 to directly contact the cap layer (1). If the cap layer (1) is removed, the gate dielectric The layer 131 will directly surround the fin structure 110. Finally, the patterned gate dielectric layer 131 and the gate material layer m become the gate structure 13〇, thus completing the method for forming the multi-effect transistor structure of the present invention. The method of the present invention can obtain the structure of at least two fin field effect transistors. First, as shown in FIG. 9A, in the first embodiment of the present invention, a (4) field effect transistor structure is provided. The Fin 201248855 field effect transistor structure 100 of the embodiment comprises a substrate 101, a gas madness 120 and a gate structure 130. The substrate 101 is generally a ruthenium, a ruthenium, an insulation layer such as Shi Xi, and may The oxidized and shaped semiconductor substrate, as appropriate, is obtained by direct oxidation of germanium atoms in the substrate 1〇1, because the insulating layer 120 of the insulating layer 120 directly covers the substrate 101. Therefore, this The bulky transistor structure 100 does not require the use of a higher cost sand. The fin field effect substrate of the present invention is 'insulated (son has the advantage of production cost. ^ The insulating layer 120 itself has a top surface 121 and is eroded with the US Direct contact with material 101 Face 122. Since the insulating layer 120 is directly oxidized by germanium atoms in the substrate 101, so that at least one of the top surface 121 and the bottom surface 122 is not flat, for example, the insulating layer 120 includes a plurality of U-shaped bottom surfaces 122, and It is different from the flat surface (not shown) formed by the deposition method. Moreover, the insulating layer 12 is thus substantially free of stress. The fin structure 11 is located on the insulating layer 120 and contains the fin conductor. Layer 117 and a set of source/nopoles 118 on either side of finned conductor layer 117. Preferably, there is a rounded corner 116 above the fin structure 110. In the fin field effect transistor structure loo of the present invention, more than one fin structure 110 may be included, so that the fin structure 11〇 may also be located between adjacent U-shaped bottom surfaces 122. The finned conductor layer in the fin structure 110 is originally part of the substrate 101 but is completely separated from the substrate 1〇1 due to the barrier of the insulating layer 120. Depending on the situation, the fin structure 11 may also include a cover 15 201248855 which may contain oxynitride. The cap layer 113 of the fin conductor layer 117, the gate electrode 13C is partially enclosed in two directions, and includes a gate dielectric layer 131 and a gate material layer (1) surrounding the fin structure. Extend the gate of the application, ',. The structure 13G generally forms a continuous u-shape, and can simultaneously control a plurality of sets of read structures 110. If the cap layer 113 is removed, the gate structure 130 controls the fin structure UG from one direction. If the cap layer (1) is retained, the interposer structure 130 controls the fin structure n〇 from both directions.其 Next, as shown in FIG. 9B, in the second embodiment of the present invention, a further field-dependent transistor structure L is provided. The fin field effect transistor structure 1() of the second embodiment of the present invention includes Substrate 1 (n, fin structure u〇, insulating layer (4) and gate structure 13〇. Substrate 1〇1 is usually a semiconductor substrate, such as germanium. Preferably, the 'fin structure 11' will have The apex angle of the round purification (10). If necessary, the fin structure 11G may further include a cap layer 113 covering the Korean conductor layer U7, which may contain oxynitride. If the interpole structure 13G is controlled from three directions The fin structure m removes the cap layer 113. If the gate structure 130 controls the fin structure from both directions, the cap layer 113 is retained. The insulating layer 12 is substantially free of stress. The difference between the second embodiment and the first embodiment of the present invention is that the insulating layer 12 of the second embodiment of the present invention is filled in the vicinity of the fin structure 110 in a deposition manner, so that the first recess is located in the substrate 101. 1〇3 and the second 16 201248855 pocket 102, rather than the entire sheet covering the substrate 101. Insulation 120 may comprise cerium oxide or cerium oxynitride. As shown in Figure 5, the second pocket 102 is preferably wedge-shaped with its convex side 105 extending below the fin structure 11 ' 'and thus in the fin structure 110 A neck portion 104 is formed. The fin structure 110 is directly connected to the substrate 1〇1 by the neck portion 104, and the heat dissipation function is retained, and the leakage current can be reduced. The width of the neck portion 1〇4 can be referred to as the case requires. Between 3 μm (μπ〇 and 10 μm, or the width of the neck portion 104 is 40%-60% of the width of the fin structure 110. Also, as needed, the fin field effect power of the second embodiment of the present invention The crystal structure 100 may further include a liner layer 109. The liner layer 109 is located between the shallow trench isolation 122 and the substrate 101, and between the insulating layer 120 and the fin structure 110. Filling the first recess 103 and the second The insulating layer 120 in the cavity 102 covers not only the substrate 101 but also a convex side surface 105 partially surrounding the neck portion 104 of the fin structure 110, and a bottom surface 122 directly contacting the substrate 101. The convex side 1 〇5 extends below the fin structure 11〇. The first recess 103 is filled In order to penetrate into the substrate, it can also be independently regarded as being under the insulating layer 120 filling the second recess 102 as a shallow trench isolation 122 commonly used for semiconductor components. These shallow trench isolations 122 have direct contact with the insulating layer 120. Contacting the top portion 123, the bottom surface 121 of the insulating layer 120 is greater than the top portion 123 of the shallow trench isolation 122. 17 201248855 The foregoing is merely a preferred embodiment of the present invention, and the equivalent variation of the scope of the patent application of the present invention is Modifications are all within the scope of the present invention. [Simplified Schematic Description] Figs. 1 to 8B illustrate a method of forming a multi-fin field effect transistor structure of the present invention. FIG. 9A illustrates a fin field effect transistor structure of the present invention. FIG. 9B illustrates another fin field effect transistor structure of the present invention. [Main component symbol description] 100 fin field effect transistor structure 101 substrate 102 second concave six 103 first recess 104 neck portion 105 convex side 109 backing layer 110 fin structure 111 mask layer 112 buffer layer 113 cap Cover layer 114 sidewall 18 201248855 115 sidewall material layer 116 apex angle 117 fin conductor layer 118 source/drain 119 buffer layer 120 oxide layer 121 top surface 122 bottom surface 130 gate structure 131 gate dielectric layer 132 gate material Floor