1289344 .lS173twf.doc/r 九、發明說明： 【备明所屬之技術領域】 本發明是有關於—種丰-是有關於—種㈣記的4造方法，且特別 【先前技術】 ° / 在各種非揮發性記憶 之存入、讀取、抹除等動作產;:;:=多次資料 會消失之優點的可雷括 、科在畸電後也不 (EEPROM)，如快閃記憶體結構，二^買記憶體 設儀所廣泛制的-種記憶體元件。，，、、讀和電子 通常快閃記Μ具有兩個閘極，其巾料 (P〇ly-S1lic〇n)所製作用來儲存電荷的浮置’、、、夕日日夕 _以及絲控制資料存取的控 而士為了避免典型的可電抹除且可程式唯讀記憶體在抹)除 奸，因過度抹除現象太過嚴；f，而導致資料之誤判的問題。 所以在控制閘極與浮置閘極側壁、基底上方另設一選擇閘 極(select gate) ’也可稱輔助閘極(assist gate)，以形成 閘極(__gate)結構。 離 如圖1A至圖1D所述，為上述之分離閘極結構的快閃 記憶體之部分製造流程的剖面圖。 首先，請參照圖1A。於基底100上形成一堆疊結構 108。堆疊結構108是從基底1〇〇開始依序是由閘介電層 102、輔助閘極104以及頂蓋層1〇6所组成。而相鄰兩個堆 疊結構108中有一間隙109。然後，進行傾斜角離子植入 1289344 ,18173twf.doc/r 製程110，以形成源極/汲極區114。 調整離子獻製程112，以形成雜區 接著，請參照圖1B。於堆疊結構10 間隙壁⑽。間_118的形成方法从以四基3 (TCOS)為反應氣體源進行化學氣相沈積製程形成的一層 氧化石夕層（未繪示）。接著再對氧化㈣進行回姓刻1289344 .lS173twf.doc/r IX. Description of the invention: [Technical field to which the invention pertains] The present invention relates to a method for producing a species--------------------------- Various non-volatile memory storage, reading, erasing and other action products;:;:=The advantages of multiple data disappearing can be included, the department is not (EEPROM) after the distortion, such as flash memory Structure, two kinds of memory components widely used in memory devices. ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, In order to avoid the typical electric erasable and programmable read-only memory in the wipes, the phenomenon of over-erasing is too strict; f, which leads to misjudgment of data. Therefore, a selective gate (also referred to as a "select gate") can also be referred to as an auxiliary gate on the sidewalls of the control gate and the floating gate and the substrate to form a gate (__gate) structure. 1A to 1D is a cross-sectional view showing a part of the manufacturing process of the flash memory of the above-described split gate structure. First, please refer to FIG. 1A. A stacked structure 108 is formed on the substrate 100. The stack structure 108 is composed of the gate dielectric layer 102, the auxiliary gate 104, and the cap layer 1 依6 in order from the substrate 1 。. There is a gap 109 in the adjacent two stack structures 108. Then, tilt angle ion implantation 1289344, 18173 twf.doc / r process 110 is performed to form source/drain regions 114. The ion contribution process 112 is adjusted to form a miscellaneous region. Next, please refer to FIG. 1B. In the stack structure 10 spacers (10). The method of forming the interlayer _118 is a layer of oxidized stone (not shown) formed by a chemical vapor deposition process using tetrabasic 3 (TCOS) as a reactive gas source. Then go back to the oxidation (four)
得注意的是，此回餘刻過程中，會破壞間隙刚中的基底 100，而使基底1〇〇產生缺陷12〇。 然後，清茶照圖1C。基底1〇〇中有缺陷12〇，為了移 除缺1½ 120錄底⑽平坦彳b，因此對缺陷12Q處的基底 WO進行熱氧化製程，以形成犧牲氧化層（未繪示）。之 後再以/愚式姓刻法移除犧牲氧化層。因此，間隙1〇9中 的基底100表面產生凹面丨22。 、★隨，，請參照圖1D。於間隙109中的基底1〇〇上形 成牙，氧化層128。穿隧氧化層ι28的形成方法是以熱氧 匕法氧化已形成凹面122的基底1〇〇。接著，於穿隧氧化 層128上形成浮置閘極13〇。形成浮置閘極13〇與後續完 成决閃β己憶體的步驟之方法，為此技術領域中具通常知識 者應明瞭，故於此不贅述。 、，斤值得一提的是，上述犧牲氧化層的厚度，同時影響穿 層128的品質以及電荷保留能力。也就是說，為了 維蠖穿隧氧化層128的品質，所以形成並移除犧牲氧化 =，以去除有缺陷120的基底1〇〇表面。而犧牲氧化層越 厚，越能確保基底1〇〇中的缺陷12()移除的越完全，之後 1289344 ， ' 18173twf.doc/r ^化:成的輯氧化層128品質才能越好。而在另—方 犧牲乳化層的厚度越厚，表示凹面122的深戶越、、罙， 彳 處）。如此一來，浮置閘極與源極 的ΐ^ΪΓ。很容易形成漏電流，降低穿隨氧化層⑶ 關鐘縱^所’犧牲氧化層的厚度將成為整個元件良率的 二生存有一個製程裕度，此製程裕度即 事，因此平有必^旱有關。然而此製程裕度的拿捏並非易 【發明内容】 製程方法崎決元件的上述缺點。 的f 此τ本ί明的目的就是在提供—種快閃記憶體 力^ 可以提升穿隨介電層的品質以及電荷保留能 ，發明提出—種㈣記紐的製造方法。首先，提供 ‘二形成多數個堆疊結構，堆疊結構從基底 汗°介電層、第—導體層 兩 Π的堆疊結構之間具有-間隙。接著，：;疊結2 ，的基底中形成源極/沒極㊄。然後，於堆 =;;緣::壁。繼之，於峨構之間的基底上形成 电g °之後’於開介電層上形成辅助閉極。隨後，於 旦間極上形成頂蓋層，頂蓋層填滿 中之罩幕層，形成暴露第一導體層之二=堆 、土氏上喊_介電層。之後，於基底上形成控制閘極， 1289344 .18173twf.doc/r 且控制閘極填滿開口 造方閃記憶體的製 導體層與導體:二成導體間隙壁，第- i方=本r明的一實施例所述，上述之快閃記憶體的製 二=?構之第一侧的基底中形成源極娜： =質為包角離子植入製程。而傾斜角離子崎 造』構實 之步驟後’更包括進行一起始電墨調整料植^^極^ 起始^調整離子植入製程的摻質為氟化賣BF2f 进方：一實施例所述，上述之快閃刪的製 缸巾於^結構的側壁形成絕緣㈣:壁之步， 增犧牲⑽。再進行 。接著以罩幕層 表面。：二c材料細至堆叠結構的 結構的表面，以形‘“二體材料層_至低於堆疊 依知本發明的一實施丫 造方法中，辅助閑極的材料^摻雜=:閃記憶體的製 1289344 , .18173twf.doc/r 依照本發明的-實施例所述，上述之快閃記憶體的製 造方法中，第—導體層的材料包括摻雜多晶石夕。 =本發明的—實施例所述，上述之快閃記憶體的製 以方法中，控制閘極的材料包括摻雜多晶矽。 =本發明的一實施例所述，上述之快閃記憶體的製 ΐη ^ !:壁包括以四乙氧基魏(TEC)S)為反應氣體 源進订化學氣相沈積製程所形成的氧化石夕層。 =本發:月的—實施例所述，上述之：閃記憶體的製 k方法中，頂盍層的材料包括氧化矽。 本ί明的—實施例所述，上述之快閃記憶體的製 化方法中’牙1¾介電層的材料包括氧化石夕。 迕方實施例所述’上述之快閃記憶體的製 化方法中，罩幕層的材料包括氮化石夕。 送方:實施例所述，上述之快閃記憶體的製 k方法中’閘㈣層的材料包括氧化石夕。 造方3本施例所述，上述之㈣記憶體的製 /氧化料包括氧切或氧化魏化石夕 在本發明之快閃記憶體的製造方法中 閘堆疊結構於基底上，因此穿隧介 ；先形成子置 缺陷的基底上，所mm、、/電層成於沒有被侧產生 -來，穿險气介展沾去成亚移除犧牲氧化層的步驟。如此 *牙U化層的品質與電荷保留能力 悲，而不受犧牲氧化層的影響。 順寺在取^土狀 為讓本發明之上述料他目的、特徵和優點能更明顯 10 1289344 • · 18173twf.doc/r 1 易懂，下文特舉較佳實施例，並配合所附圖式，作詳細說 .明如下。 【實施方式】 圖2A至圖2E為本發明之一實施例的快閃記憶體的製 造方法之流程剖面示意圖。圖3為本實施例之上視圖。 首先，請參照圖2A。提供已形成數個堆疊結構2〇8 的基底200。堆疊結構2〇8從基底200開始依序為穿隨介 % 电層202、導體層以及罩幕層206。其中，穿隧介電層 202的材料例如是氧化矽，其形成方法例如是對基底2〇〇 進行熱氧化製程。導體層204的材質例如是摻雜多晶石夕， 其形成方法例如是進行化學氣相沈積法。罩幕層206的材 料例如是氮化矽，其形成方法例如是進行化學氣相沈積 法。而兩個相鄰的堆疊結構2〇8之間具有間隙2〇9。 值传&的疋’本實施例先形成於基底2〇〇上的堆疊 、、才冓208中，^r體層204未來會成為浮置閘，因此基底2〇〇 _ 上百先形成的是穿隧介電層202。此穿隧介電層202形成 於未叉任何蝕刻侵蝕的基底200上，因此穿隧介電層2〇2 的ππ質較為良好，不再如習知一般受到犧牲氧化層的影響。 然後，進行傾斜角離子植入製程21〇，以於堆疊結構 ^〇8之第一侧的基底20〇中形成源極/汲極區212。傾斜角 雒子，入製裎21〇例如是對基底以一傾斜角0進行離子植 ί : Ϊ子植，所使用的摻質例如是坤(As)或其他合適摻 貝/近後，還可以進行起始電壓調整離子植入製程214， 以形成摻雜區216。起始電壓調整離子植入製程2U同樣 1289344 . · 18173twf.doc/r 子植入製程，例如是對基底以-傾斜角- H 入起始電壓調整離子植入製程214的摻質 列0疋氟化硼(BF/)或其他合適摻質。 、 絕緣照的側壁形成 ρ感 隙壁8例如是以四乙氧基石夕烷 +為反應乳脰源進行化學氣相沈積製程形成氧化石夕 再對氧切層進行回㈣，以形成間隙壁218, 亚恭路間隙209中的基底2〇〇。 例中’還可以於堆疊結構208之間的基底_ 乳化層219。犧牲氧化層219的材料與形成方 再：U基底200進行熱氧化法形成的氧化矽層。之後 製程移除犧牲氧化層219。此步驟是因為 隙20: Ϊ的I::成絕緣間隙壁218的步驟中，會使間 ,, 〇 土底200產生凹凸不平的缺陷211，所以者形 2lf。移除犧牲氧化層之後，可以消除基底表面的:陷 料。門入220的材料例如是氧化麥或其他合適材 220 202戽，不办ϋ二 、、閘介電層220較穿隧介電層 合迭成卩夂低备彳4 °自知所述裸露源極/汲極區212，所以不 成牛低70件的電荷保留能力。因此也可以省略上述先 1289344 * ·〗8]73twf.doc/r 形成犧牲氧化層219，然後再移除之的步驟。 輔助於間隙209中形成輔助閘極222。 I ‘ _㈣例％是先以化學氣相沈積法於基 間隙2〇/ίΪ體材料層（未繪示），且導體材料層填滿 枯粗。妓1 '中丄導體材料例如是摻雜多晶石夕或其他合適 列1以者’進行化學機械研磨製程，以罩幕層206為餘 二^ s ’將導體材料層侧至堆疊結構施表面。繼之， 程’將導體材料層钱刻至低於堆疊結構_ 隨後’於輔助閘極222上形成頂蓋層224，頂蓋 二上填滿間咏209。頂蓋層224的材料例如是氧化石夕或 /5適材料。頂蓋層224的形成方法例如是先以四乙氧 ^石夕^反絲贿進行化學氣相沈㈣㈣成氧化石夕 以罩幕層施為钱刻終止層，對氧化韻進行 ^匕干機械研磨製程，將氧切層_至堆疊結構施 面，以形成頂蓋層224。 繼之，請參照圖2D。移除置篡爲…l曰_ * 層204之Η口州罢苴/罩幕層 形成暴露導體 刻本」 。罩幕層爛的移除方法例如是濕式钱 2。然後，於導體層綱上形成導體間隙壁a6，導體 ^壁22=形成方法例如是先沈積—層導體材料層（未 再對導體材料層進行贿刻製程。導體材料例如 2:7二^其他合適材料。導體層2〇4與導體間隙壁 =228。$體層228的表面積較導體層2〇4 ，也就是使其成為浮置閑（如圖2E與圖3所示） 表面積增加，進而增加與後續形成的控制閘極的輕合率。 13 1289344 . · 18173twf.doc/r 之後’請芩, 一 肩2E，並同時參照圖3。圖3為快閃記 、巧不。於基底上形成閘間介電層230。閘間介電層23〇 的材料例如是氧化石夕或其他合適材 曰 上形成控制閑極232，且控制閣極肋真滿開口 底: 開極m的形成方法例如是以化學氣 體材料層，導體材料層例如是換雜多晶石夕或=人^ ^接著再錢學機械研磨法平域導體材 ^ 字元線的區域形成長條狀的光阻 ^^胃不），長㈣的光阻層與長條狀的導體層228成 二父錯湖。繼之，移除未被光阻層覆蓋的部分導體材 ，綱體層228，以形成長條狀的控制閑極232與 塊狀的浮置閘極234。 上述所有構件中，基底綱、穿隨介電層202、源極/ 汲極區212、摻雜區216、絕緣間隙壁218、閘介電層220、 輔助問極222、頂蓋層224、浮置閘極m、閘間介電層23〇 以及控制閘極232組成-快閃記憶胞24〇。 綜上所述，本發明之快閃記憶體的製造流程，是先形成 =置閉堆疊結構於基底上姻親介電層形成於沒有被^ 生夫1¾的基底上’所以3去形成並移除犧牲氧化層的步驟。 如，來’牙1¾介電層的品質與電荷保留能力皆可保持在最佳 狀4，進而提升元件的良率與可靠度。 —雖本赉明已以較佳實施例揭露如上，然其並非用以 ΙΨ疋本叙月任何热習此技藝者，在不脫離本發明之精神 14 1289344 • 18]73twf.doc/r 和範圍内，當可作些許之更動與潤飾，因 範圍當視後附之申請專利範圍所界定者為準。發明之保護 【圖式簡單說明】 ’、、、° 圖1A至圖1D為依照習知的快閃記憶體所緣示之 造剖面流程圖。 &It should be noted that during this rewinding process, the substrate 100 in the gap is destroyed, and the substrate 1 has a defect of 12 〇. Then, the tea is shown in Figure 1C. The substrate 1 has a defect of 12 Å. In order to remove the bottom (10) flat 彳b, the substrate WO at the defect 12Q is subjected to a thermal oxidation process to form a sacrificial oxide layer (not shown). The sacrificial oxide layer is then removed by the /foss name. Therefore, the surface of the substrate 100 in the gap 1〇9 produces a concave surface 22 . , ★,, please refer to Figure 1D. A tooth, oxide layer 128 is formed on the substrate 1 in the gap 109. The formation of the tunnel oxide layer ι28 is performed by a thermal enthalpy method to oxidize the substrate 1 having the concave surface 122 formed. Next, a floating gate 13A is formed on the tunnel oxide layer 128. The method of forming the floating gate 13A and the subsequent step of completing the flashback beta memory is well known to those skilled in the art and will not be described herein. It is worth mentioning that the thickness of the sacrificial oxide layer described above affects both the quality of the layer 128 and the charge retention capability. That is, in order to maintain the quality of the tunnel oxide layer 128, sacrificial oxidation = is formed and removed to remove the surface of the substrate 1 having the defect 120. The thicker the sacrificial oxide layer, the more complete the defect 12() removal in the substrate can be ensured. After 1289344, '18173twf.doc/r^: the quality of the formed oxide layer 128 is better. On the other hand, the thicker the thickness of the emulsion layer is, the deeper the surface of the concave surface 122, the 罙, 彳, 彳). In this way, the floating gate and the source are ΐ^ΪΓ. It is easy to form a leakage current, and reduce the thickness of the oxide layer (3). The thickness of the sacrificial oxide layer will become a process margin for the survival of the entire component yield. This process margin is a matter of course, so it is necessary to . However, this process margin is not easy to handle. [Invention] The above disadvantages of the process method are the components of the chip. The purpose of this τ ί ί 就是 is to provide a kind of flash memory force ^ can improve the quality of the dielectric layer and the charge retention energy, the invention proposes a kind of (four) note manufacturing method. First, it is provided that 'two forms a plurality of stacked structures having a gap between the stacked structures of the base sweat dielectric layer and the first conductor layer. Next, a source/no pole five is formed in the substrate of the stack 2; Then, on the heap =;; edge:: wall. Subsequently, an auxiliary closed-pole is formed on the open dielectric layer after forming an electrical g ° on the substrate between the structures. Subsequently, a cap layer is formed on the poles, and the cap layer is filled with the cap layer to form a second layer of the first conductor layer exposed, and a dielectric layer on the soil. Then, a control gate is formed on the substrate, 1289344.18173twf.doc/r and the control gate fills the conductor layer and the conductor of the open square flash memory: two conductor gaps, the -i side = the present In one embodiment, the source of the first side of the flash memory is formed in the substrate on the first side: the quality is a wrap angle ion implantation process. After the step of constructing the tilting angle ionization, the method further includes performing an initial ink adjusting material, and initializing the dopant of the ion implantation process to be fluorinated and selling BF2f. As described above, the above-mentioned flash-flashing cylinder towel forms insulation (4) on the side wall of the structure: the step of the wall, and the sacrifice (10). Go ahead. Then cover the surface of the curtain layer. : The material of the second c material is as thin as the surface of the structure of the stacked structure, and the material of the auxiliary idler is doped in the shape of the 'two-body material layer _ to the lower one of the implementation method of the present invention. 1289344, .18173twf.doc/r According to the embodiment of the present invention, in the method for manufacturing a flash memory, the material of the first conductor layer includes doped polycrystalline stone. - In the above-described method for manufacturing a flash memory, the material for controlling the gate includes doped polysilicon. = According to an embodiment of the present invention, the above-described flash memory is made of ΐ η ^!: The wall comprises a layer of oxidized stone formed by a chemical vapor deposition process using tetraethoxy Wei (TEC) S) as a reactive gas source. The present invention is as described in the embodiment, the above: flash memory In the method of making k, the material of the top layer includes yttrium oxide. In the above-described method of flash memory, the material of the dielectric layer includes the oxidized stone 。. In the method for manufacturing a flash memory as described in the above embodiments, the material layer of the mask layer In the above-mentioned method of manufacturing the flash memory, the material of the 'gate (four) layer includes the oxidized stone eve. The third embodiment of the method, the above-mentioned (four) memory system The oxidized material comprises oxygen-cut or oxidized Weihuahua. In the method for manufacturing the flash memory of the present invention, the gate stack structure is on the substrate, so that the tunneling is performed; firstly, the sub-defective substrate is formed, and the mm, // The layer is formed without being side-produced, and the step of removing the sacrificial oxide layer by the smear is carried out. Thus, the quality and charge retention of the toothed layer are sorrowful without being affected by the sacrificial oxide layer. The purpose of the above-mentioned materials in the present invention is to make the object, features and advantages of the present invention more obvious. 10 1289344 • · 18173 twf.doc/r 1 is easy to understand, the preferred embodiment is exemplified below, and the drawings are combined with the drawings. 2A to 2E are schematic cross-sectional views showing a method of manufacturing a flash memory according to an embodiment of the present invention. Fig. 3 is a top view of the embodiment. Referring to Fig. 2A, a base having a plurality of stacked structures 2〇8 is formed. 200. The stacked structure 2〇8 is sequentially followed by the dielectric layer 202, the conductor layer, and the mask layer 206 from the substrate 200. The material of the tunneling dielectric layer 202 is, for example, hafnium oxide, and the forming method thereof is, for example, The substrate 2 is subjected to a thermal oxidation process. The material of the conductor layer 204 is, for example, doped polycrystalline stone, and the formation method thereof is, for example, chemical vapor deposition. The material of the mask layer 206 is, for example, tantalum nitride, which is formed. The method is, for example, a chemical vapor deposition method, and a gap between two adjacent stacked structures 2〇8 is 2〇9. The value of the present embodiment is first formed on the stack of the substrate 2〇〇, In the case of the 208, the body layer 204 will become a floating gate in the future, so that the substrate 2 〇〇 _ is formed by the tunnel dielectric layer 202. The tunneling dielectric layer 202 is formed on the substrate 200 which is not etched by any etching, so that the ππ quality of the tunneling dielectric layer 2〇2 is relatively good and is no longer affected by the sacrificial oxide layer as is conventional. Then, a tilt angle ion implantation process 21 is performed to form a source/drain region 212 in the substrate 20A on the first side of the stacked structure ^8. Tilting angle dice, such as 裎 21〇, for example, ion implantation of the substrate at an oblique angle of 0: Ϊ子植, using the dopant such as Kun (As) or other suitable doping / near, can also A starting voltage adjustment ion implantation process 214 is performed to form doped regions 216. The initial voltage adjustment ion implantation process 2U is also the same 1289344. · 18173twf.doc / r sub-implantation process, for example, the substrate is tilted at an angle - H into the starting voltage to adjust the dopant column of the ion implantation process 214 Boron (BF/) or other suitable dopants. The insulating sidewalls form a p-gap wall 8 for example, by using a tetraethoxy oxane+ as a reactive chyle source for a chemical vapor deposition process to form an oxidized oxide and then returning the oxygen-cut layer (IV) to form a spacer 218. , the substrate 2 in the gap 209 of the Agong Road. In the example, the substrate _ emulsified layer 219 between the stacked structures 208 can also be used. The material of the sacrificial oxide layer 219 is formed and the U-base 200 is subjected to a thermal oxidation method to form a hafnium oxide layer. The process then removes the sacrificial oxide layer 219. This step is because the gap 20: I I:: in the step of forming the insulating spacer 218 causes the unevenness 211 of the sinter bottom 200 to be uneven, so that 2f is formed. After the sacrificial oxide layer is removed, the surface of the substrate can be eliminated: trapping. The material of the gate 220 is, for example, oxidized wheat or other suitable material 220 202 戽, and the gate dielectric layer 220 is stacked with the tunnel dielectric layer to form a low 彳 4 ° self-known bare source. The pole/bungee zone 212, so it does not have a charge retention capacity of 70 pieces. Therefore, it is also possible to omit the step of forming the sacrificial oxide layer 219 by the first 1289344 * · 8] 73 twf.doc / r and then removing it. Auxiliary gate 222 is formed in the gap 209. I ‘ _ (4)% is first chemical vapor deposition in the base gap 2 〇 / Ϊ Ϊ body material layer (not shown), and the conductor material layer is filled with thick.妓1 'the mid-turn conductor material is, for example, doped polycrystalline or other suitable column 1 'to perform a chemical mechanical polishing process, with the mask layer 206 as the remaining layer s 'the side of the conductor material layer to the stacked structure surface . Next, the process of engraving the conductor material layer below the stacked structure _ subsequently forms a cap layer 224 on the auxiliary gate 222, and the cap 2 is filled with the interstitial 209. The material of the cap layer 224 is, for example, a oxidized stone or a /5-suitable material. The method for forming the top cover layer 224 is, for example, first performing chemical vapor deposition (IV) (4) into an oxidized stone by means of tetraethoxy oxime, and then applying a mask layer as a molybdenum stop layer. The polishing process applies the oxygen cut layer to the stacked structure to form the cap layer 224. Next, please refer to Figure 2D. Remove the 曰 州 * * * 层 层 层 层 层 层 204 204 204 204 204 204 204 204 204 204 204 204 204 204 形成 形成 形成 形成 形成 形成 形成The method of removing the mask layer is, for example, wet money 2. Then, a conductor spacer a6 is formed on the conductor layer, and the conductor wall 22 is formed by, for example, depositing a layer of a conductor material layer (the conductor material layer is not subjected to a briber process). The conductor material is, for example, 2:7 Suitable material. Conductor layer 2〇4 and conductor spacer = 228. The surface area of body layer 228 is 2〇4 than that of conductor layer, that is, it makes it float free (as shown in Figure 2E and Figure 3). The rate of coincidence with the control gate formed later. 13 1289344 . · 18173twf.doc/r After 'please 芩, one shoulder 2E, and also refer to Figure 3. Figure 3 is flash, not good. Form a gate on the substrate The dielectric layer 230. The material of the inter-gate dielectric layer 23〇 is, for example, a oxidized stone or other suitable material, forming a control idle pole 232, and controlling the pole ribs to be fully open. The formation method of the open pole m is, for example, In the chemical gas material layer, the conductor material layer is, for example, a polycrystalline spine or a person ^ ^ and then the mechanical polishing method of the flat domain conductor material ^ word line to form a long strip of photoresist ^ ^ stomach not The long (four) photoresist layer and the long strip conductor layer 228 form a parental lake. Next, a portion of the conductor material, which is not covered by the photoresist layer, is removed to form a strip-shaped control stub 232 and a bulk floating gate 234. Among all the above components, the substrate, the dielectric layer 202, the source/drain region 212, the doped region 216, the insulating spacer 218, the gate dielectric layer 220, the auxiliary gate 222, the cap layer 224, and the floating layer The gate m, the inter-gate dielectric layer 23, and the control gate 232 are formed - a flash memory cell 24 〇. In summary, the flash memory of the present invention is formed by first forming a closed-package structure on the substrate, and forming an auricular dielectric layer on the substrate that is not being cured. The step of sacrificing the oxide layer. For example, the quality and charge retention of the dielectric layer can be maintained in an optimum shape, thereby improving component yield and reliability. - Although this has been disclosed above in the preferred embodiment, it is not intended to be used by anyone skilled in the art, without departing from the spirit of the invention. 14 1289344 • 18] 73twf.doc/r and scope In the meantime, some changes and refinements may be made, as defined in the scope of the patent application. [Brief Description of the Invention] FIG. 1A to FIG. 1D are flow charts showing the structure of a conventional flash memory. &
圖2A至圖2E為本發明之一實施例的快閃記憶體之警 造剖面流程圖。 I 圖3為本喬明之上視圖。圖中，連線之剖面圖即為 圖 2E。 、 【主要元件符號說明】 100、200 :基底 102 :閘介電層 104、222 :輔助閘極 106、224 :頂蓋層 108、 208 :堆疊結構 109、 209 :間隙 110、 210 :傾斜角離子植入製程 112、214 :起始電壓調整離子植入製程 114、212 :源極汲極區 116、216 :摻雜區 118 :間隙壁 120 :缺陷 122 :凹面 124 :角落 15 1289344 .18173twf.doc/r 128 :穿隧氧化層 130、234 :浮置閘極 202 :穿隧介電層 204、228 :導體層 206 :罩幕層 218 :絕緣間隙壁 219 :犧牲氧化層 220 :閘介電層 221 :缺陷 225 :開口 226 :導體間隙壁 230 :閘間介電層 232 :控制閘極 240 :快閃記憶胞 Θ :傾斜角 A-A’ ：連線2A to 2E are flowcharts showing an alarm profile of a flash memory according to an embodiment of the present invention. I Figure 3 is a top view of this Qiao Ming. In the figure, the cross-sectional view of the line is shown in Figure 2E. [Main component symbol description] 100, 200: substrate 102: gate dielectric layer 104, 222: auxiliary gate 106, 224: cap layer 108, 208: stacked structure 109, 209: gap 110, 210: tilt angle ion Implantation process 112, 214: initial voltage adjustment ion implantation process 114, 212: source drain region 116, 216: doped region 118: spacer 120: defect 122: concave surface 124: corner 15 1289344 .18173twf.doc /r 128 : Tunneling oxide layer 130, 234: floating gate 202: tunneling dielectric layer 204, 228: conductor layer 206: mask layer 218: insulating spacer 219: sacrificial oxide layer 220: gate dielectric layer 221: Defect 225: Opening 226: Conductor spacer 230: Inter-gate dielectric layer 232: Control gate 240: Flash memory cell: Tilt angle A-A': Connection