!281232 九、發明說明： 【發明所屬之技術領域】 本發明有關於—種非揮發性記憶體的f造方法，特财關-種改盖非 揮發性記__可靠㈣製造方法。 ° 【先前技術】 氣抹除式可編程唯讀記憶體（EEpR〇M)為現今資訊電子產品所廣泛 Μ的記憶元件，原本有存取速度較慢的缺點，然磁製程技術的進步， 鲁近年來已開發出存取速度較快的腿⑽，_般稱之為快閃記憶細她 roemory)。 傳統之快閃記憶體結構係為一堆疊閘極式快閃記憶體，具有一控制閑 極與-浮置閘極(n〇ating gate)堆疊於元件通道上方，並藉由熱載子_ 咖扛）由祕端注人浮置的形式，_程式化(卿^丨呢)之目 的。但因熱載子(hot carrier)注入的效率不高，加上隨元件尺寸之縮小， 除了通韻度會隨之驗以外，堆疊於通道±方的浮置閘與控綱之製作 面積也必然會同時縮減，以致浮置閘與控制閘之間的電容值降低，造成操 作電壓的增加。 木 於是’為了提升熱載子注入效率，大多會採用增設閘極單元的方式來 軸。例如-種分離閘極式的快閃記體結構，其係在浮置閘之側增設間極， 藉由控制閘尺寸之增加，而足以同時提升控制閘與浮置間之電麵合率 (c_lng涵。)以及熱載子注人效率，進而達到降低操作電_效果。 然而，在製造分離閘極式的,_記結構崎程麵產生的缺陷 ㈣ect)，可能使得後續形成之位元線接觸窗與字元線接觸而=短路。281232 IX. Description of the Invention: [Technical Field of the Invention] The present invention relates to a method for manufacturing a non-volatile memory, and a method for manufacturing a non-volatile memory. ° [Prior Art] Gas erasing programmable read-only memory (EEpR〇M) is a widely used memory component of today's information electronics products. It has the disadvantage of slow access speed, and the progress of magnetic process technology. In recent years, the leg (10) with faster access speed has been developed, which is called "flash memory fine". The conventional flash memory structure is a stacked gate type flash memory having a control idler and a floating gate stacked above the component channel and by a hot carrier.扛) by the secret end of the form of floating, _ stylized (clear). However, due to the low efficiency of hot carrier injection, and the reduction of the size of the components, in addition to the rhyme will follow, the production area of the floating gate and the control unit stacked on the channel ± square is also inevitable. At the same time, the capacitance is reduced, so that the capacitance between the floating gate and the control gate is lowered, resulting in an increase in the operating voltage. Therefore, in order to improve the efficiency of hot carrier injection, most of them use the method of adding a gate unit to the shaft. For example, a kind of separation gate type flash flash structure is added to the side of the floating gate to increase the electric gate ratio between the control gate and the floating layer by increasing the size of the control gate (c_lng Han.) and the efficiency of the hot carrier injection, which in turn reduces the operating power. However, in the fabrication of a separate gate type, the defect (4) ect generated by the surface of the structure may cause the subsequently formed bit line contact window to be in contact with the word line = short circuit.
0593-A40569TWF 5 1281232 尤有甚者，會惡化P型井區漏電流之問題，並且當快閃記憶體在進行抹除 等動作時，會導致記憶胞或整個晶粒失效。 ^ 【發明内容】 ^ 有鑑於此，本發明的目的就在於提供一種非揮發性記憶體陣列的製造 方式，以解決因製程缺陷造成字元線與位元線接觸窗發生短路的問題。 為達成上述目的，本發明提供一種非揮發性記憶體陣列的 製造方法，至少包括下列步驟：提供一具有至少一對閘極結構 • 之基底，其中每一閘極結構包括一控制閘極置於一浮置閘極之 上；於閘極結構間之側壁上形成一導電間隙壁；形成一遮罩， 覆蓋閘極結構和導電間隙壁，並露出閘極結構間之位元線接觸 區域；以及進行一蝕刻製程，清除位元線接觸區域上基底以外 的缺陷。 為了讓本發明之上述和其他目的、特徵、和優點能更明顯 易懂，下文特舉一較佳實施例，並配合所附圖示，作詳細說明 如下： 【實施方式】 第1至第8圖繪示本發明一實施例中製作非揮發性快閃記 憶體陣列的流程圖，其中第1-6圖與第8圖為沿字元線（word line ; WL)方向的剖面圖，第7圖則為第6圖形成遮罩後之上視 圖。如第1圖所示，提供一半導體基底10，將基底10表面以一 熱氧化法形成一氧化層12，例如二氧化矽，又稱為穿隧介電層 0593-A40569TWF 6 a^1232 (tu她ldleleetrie);於氧化層 例如摻雜多晶石夕層，作ϋ-導電層14’ 作為C憶體結構 叫）；在第-導電層u , (floating 考在結構上形成遮罩17， 孔化石夕，接 〜導電層14、氧务 、 幵口依序蝕刻絕緣層16、第 € 12以及基底1 2〇,如第2圖所示 -乂在基底1〇中形成溝槽 …、佼移除遮罩17。 如第3圖所示，以一介雷好 成的方法例如是進行高峨=侧㈣並覆蓋整 心為研祕止撕峨細咖觀康·軸絕緣 形成如第4 _之έ 製程(CMP)來平坦化介電材料22，而 似弟4圖所述之結構。再以 餘刻至低於第-導電芦u抑 刻製程將介電材料22的頂部表面 B 了屬面，接著移除絕緣層16,如第5圖所示。 第_ ^ 序_—叫如8.崎電堆疊層、- 電層24，例如摻雜多晶石夕 一 及一、、、巴緣層26，例如氮化矽。在上述 隹暨結構上形成圖案化之遮罩1〇卜 、 一 ^ 弟7圖之上視圖所示。遮罩;八著 子元線方向延伸橫跨基底10上的 射 σ 犠、第二導電層24、職介糾/再猎=靖程圖案化絕 μ 軍層18及弟一導電層μ，形成閑極堆疊 、··。構。如第δ圖所示，在基底10上第—導電層14_移除的表面會因 製程綠而在其上殘留缺陷11G，或是在酵化第—導電層μ時，㈣將 基㈣與糊22相咖上的第—輸14清除乾淨，造成在形成字 讀後’無法明確絲出位元線觸區域，即字元線會覆蓋.元線接觸 區域’造成在形成位元線接觸‘窗時，會與字元線產生短路，而降低元件的0593-A40569TWF 5 1281232 In particular, it will aggravate the leakage current in the P-type well region, and when the flash memory is erased, it will cause the memory cell or the entire die to fail. SUMMARY OF THE INVENTION In view of the above, it is an object of the present invention to provide a method of fabricating a non-volatile memory array to solve the problem of short-circuiting between a word line and a bit line contact window due to process defects. To achieve the above object, the present invention provides a method of fabricating a non-volatile memory array comprising at least the steps of: providing a substrate having at least one pair of gate structures, wherein each gate structure includes a control gate disposed a floating gate; forming a conductive spacer on a sidewall between the gate structures; forming a mask covering the gate structure and the conductive spacer and exposing a bit line contact region between the gate structures; An etching process is performed to remove defects other than the substrate on the contact area of the bit line. The above and other objects, features, and advantages of the present invention will become more apparent and understood. The figure shows a flow chart for fabricating a non-volatile flash memory array according to an embodiment of the present invention, wherein the first to sixth figures and the eighth figure are cross-sectional views along the line of the word line (WL line), the seventh The plan is a top view after forming a mask in Figure 6. As shown in FIG. 1, a semiconductor substrate 10 is provided, and an oxide layer 12 is formed on the surface of the substrate 10 by a thermal oxidation method, such as ruthenium dioxide, which is also called a tunnel dielectric layer 0593-A40569TWF 6 a^1232 (tu She ldleleetrie); in the oxide layer, for example, doped polycrystalline layer, as the ϋ-conducting layer 14' as a C-memory structure); in the first-conducting layer u, (floating to form a mask 17, a hole in the structure Fossil eve, the conductive layer 14, the oxygen, the sputum sequentially etch the insulating layer 16, the -12th and the substrate 1 〇, as shown in Fig. 2 - 乂 forming a trench in the substrate 1 佼, shifting In addition to the mask 17. As shown in Fig. 3, a method of facilitating the formation of a ridge is, for example, performing sorghum=side (four) and covering the whole heart for the research and the tearing of the ruthenium and the formation of the shaft insulation as in the fourth _ έ Process (CMP) to planarize the dielectric material 22, which is similar to the structure described in Figure 4. The top surface B of the dielectric material 22 is then etched from the etch to the lower than the first conductive etch process. Then, the insulating layer 16 is removed, as shown in Fig. 5. The first _ ^ order _ - is called 8. the sacrificial stacked layer, the - electric layer 24, such as doped polycrystalline slabs and one, one, a rim layer 26, such as tantalum nitride. A patterned mask is formed on the 隹 隹 structure, as shown in the upper view of the figure. The mask; the octagonal element extends across the substrate. 10 σ 犠, second conductive layer 24, job correction / re-hunting = Jing Cheng patterning μ μ military layer 18 and brother a conductive layer μ, forming a stack of idle poles, · · ·. It is shown that the surface on which the first conductive layer 14_ is removed on the substrate 10 may have defects 11G remaining thereon due to the process green, or when the first conductive layer μ is activated, (4) the base (four) and the paste 22 are on the coffee. The first-transmission 14 is cleaned up, causing it to be unable to clear the bit line contact area after the word is formed, that is, the word line will cover. The element line contact area will cause the contact in the formation of the bit line to be The word line is shorted and the component is lowered
0593-A40569TWF 1281232 可靠度。 第9圖至第14圖為延續第8圖之製程步驟，顯示本發明一實施例之非 揮發性記憶體陣列相鄰溝槽20間沿位元線方向（沿第7圖虛線A_A，）之截面 圖。如第9圖所示，經目案化並移除上述之遮罩1〇1後，形成堆疊結構91〇。 接著氧化整個基底10及§己憶體陣列.，例如進行快速熱氧化法(mpid0593-A40569TWF 1281232 Reliability. 9 to 14 are process steps of the continuation of FIG. 8 showing the direction along the bit line (along the broken line A_A of FIG. 7) between the adjacent trenches 20 of the non-volatile memory array according to an embodiment of the present invention. Sectional view. As shown in Fig. 9, after the above-described mask 1〇1 is visualized and removed, a stacked structure 91 is formed. Then oxidizing the entire substrate 10 and the XX array, for example, performing rapid thermal oxidation (mpid
thermal oxidation，RTO) ’以在基底10露出的表面形成一氧化層94，與 在第-導電層14及第二導電層24露出的繼上形成氧化層⑽。在另一實 施例中，可先圖案化第二導電層24和於第二導電層24側壁形成氧化層9〇， 再圖案化第—導電層14、於第—導電層14側郷成氧化層⑽及於基㈣ 表面形成氧化層94，同樣能得到堆疊結構_。此外，在製作堆疊結構_ 的過程中，可能會因製程控制不佳而產生不必要的缺陷ιι〇。 如第！_示，在堆疊結構91〇的側壁上形成絕緣間隙壁犯。其形成 方法例如是細___触賴切，鱗物_製程， 如反應式離子侧來移除基底1G上的氮切。上述非等向性侧步驟也會 將基底1G上的氧化層94移除，因此可利用乾式氧化製程於基底上重新 形成-氧化層94。如第1G圖所示，氧化層94可作為選擇閘極_介電 層0 分第三導電層’而在堆疊結構_側壁的間隙 接著參照第11圖，形成導_㈣1。其形成方法輕基底10上、、户 積-毯覆性的第三導電層，例如以低觀學氣相沈積法沈積_多_尤匕 覆蓋堆疊結構•再以_非#向性侧製程，例如反應式離子侧卿 壁取上形成導電間隙壁961，Thermal oxidation (RTO) ' forms an oxide layer 94 on the exposed surface of the substrate 10, and an oxide layer (10) on the exposed first conductive layer 14 and second conductive layer 24. In another embodiment, the second conductive layer 24 may be patterned first, and the oxide layer 9 is formed on the sidewall of the second conductive layer 24, and then the first conductive layer 14 is patterned and the oxide layer is formed on the side of the first conductive layer 14. (10) and forming an oxide layer 94 on the surface of the base (4), a stacked structure is also obtained. In addition, in the process of making the stacked structure _, unnecessary defects may occur due to poor process control. As the first! _ shows that an insulating spacer is formed on the sidewall of the stacked structure 91A. The method of formation is, for example, a fine ___touch, a scale process, such as a reactive ion side to remove the nitrogen cut on the substrate 1G. The above anisotropic side step also removes the oxide layer 94 on the substrate 1G, so that the oxide layer 94 can be reformed on the substrate by a dry oxidation process. As shown in Fig. 1G, the oxide layer 94 can be used as the selection gate _ dielectric layer 0 for the third conductive layer ′ in the gap of the stacked structure _ sidewall. Referring to Fig. 11, a guide _(4) 1 is formed. The forming method is a light-substrate 10, and a third conductive layer of a blanket-type blanket, for example, deposited by a low-profile vapor deposition method, and the _ non-# directional side process is further performed. For example, the reactive ion side wall is taken up to form a conductive spacer 961,
0593-A40569TWF 8 1281232 以作為非揮發性記憶體的選擇閑極(select她）。另外，在移除第三導電 料，亦會编1G與蝴22相繼地物乾細陷(參照 弟8圖），而造成在形成位元線接觸窗後，與字元線產生短路。如第η圖 所示，若細上有殘㈣缺陷將會_軸壁的形成位 置與形狀。 如第12圖所示，形成—遮罩12〇，將堆疊結細側壁上用來當作選 擇間極的導電間隙壁％1覆蓋，然後以一_程，例如非等向性侧製 程，麵祕輯124啦結構_ _上咖瞻961移除， 在源極線區域m中只留下絕緣間隙壁92。在移除導電間隙籠後，可 將遮㈣爾作細_時嫩。如目巾崎物所示，進行 一接雜製程，蝴邮刚伽輯底”，戦第-接雜區 =，當推雜物進入基底1〇後會向兩邊擴散，而與氧化層12間形成適當 重璺。 如第13圖所示，移除遮罩丨2 將另—縣鞋於周邊電路區（圖 未％不）亚進仃一全面性摻雜，以在 二摻雜請。 間的基底H)中形成第 參照第13圖，若在兩堆疊結軸間的位元線接觸區域122上，殘留 有先前製程所產生的缺陷110 上以 雪姑㈣減鐘h , 疋如弟8圖所不，有殘留在基底10與介 電材料22相接轉角上之導電層14(第—導電 形成導電間隙壁961時，在缺陷 、“ 1)，將會造成在 在編山上沈積較厚的導電層 性侧製絲成之導電_ % αυ手白 61會延伸至仅元線接觸區域122,而與0593-A40569TWF 8 1281232 Select the idler as a non-volatile memory (select her). In addition, in the removal of the third conductive material, the 1G and the butterfly 22 are successively finely shattered (refer to the figure 8), which causes a short circuit with the word line after forming the contact line of the bit line. As shown in the figure η, if there is a residual (four) defect on the fine, the position and shape of the _axis wall will be formed. As shown in Fig. 12, the mask 12 is formed, and the conductive spacers %1 on the thin sidewalls of the stacked junctions are used as the selected interpoles, and then processed by a process such as an anisotropic side. The secret 124 structure _ _ 上 瞻 961 removed, leaving only the insulating spacer 92 in the source line region m. After removing the conductive gap cage, the cover can be made fine. As shown by the Miyazaki object, a mixed process is carried out, and the 邮 刚 伽 辑 ” ” 戦 戦 戦 戦 接 接 , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Form the appropriate weight. As shown in Figure 13, remove the mask 丨 2 will be another - county shoes in the peripheral circuit area (Figure is not%) sub-integrated a comprehensive doping, in the two doping please In the substrate H), a reference numeral 13 is formed. If the bit line contact region 122 between the two stacked junction axes is left, the defect 110 generated by the previous process remains on the snow abundance (four) minus the clock h, such as the younger brother 8 In the figure, there is a conductive layer 14 remaining on the corner of the substrate 10 and the dielectric material 22 (the first conductive formation of the conductive spacer 961, in the defect, "1), will result in thicker deposition on the mountain The conductive layered side wire is made of conductive _% α υ hand white 61 will extend to only the element line contact area 122, and
0593-A40569TWF 9 1281232 後續形成之I - μ t 70線接觸（bitline contact)產生短路。 口此’在本翻健實施射，移除遮罩i2G後，會再 如第13圖所+产 …轉⑽«基底1G上财結構，只露出所f的位 接觸區域122。盆士 ^ /、，遮罩140的開口大於後續位元線接觸的尺寸，以確保 4立元線接觸 θ4電層接觸。接著進行-働彳步驟，例如反應式離子餘 刻或電漿蝕刻口你人 移除位雜域上導電間_ 961延伸至位元接觸 吐域122的部八 、， 、 77 "月確疋義出位兀線接觸區域122、以及其餘缺陷，如基 與介電材料22 層15〇之 ^角上之w物貝。如此一來，後續在層間介電 51中形成位元線接觸152時，便不會與導電間隙壁961 如第14輪）。另外，目㈣墙陷已經繼 免由此產生漏電的問題。 ^ 、生除’利用本發明之非揮發性記憶體陣列的製造方法，可有效 免字位元線接觸而產生短路，並 象。再者，#記憶_在進行抹除時，可避免發生錯 決判己憶胞失效的問題。 雖然本發明⑽錄實補_ 亚非用以限定本發明，任 ^白此賴者，林_本發批輯和範_， 潤部，因此她觸顧當視版懈物所&者為Γ、 【圖式簡單說明】 彳界疋者為準。 第1圖至第6 ®為本發·佳實 造 元線方向的製程剖關； a非揮發性記憶體陣列沿字 第7圖為第6 _成遮罩後之上視圖；0593-A40569TWF 9 1281232 Subsequent formation of I - μ t 70 line contact produces a short circuit. After the mask is removed, the mask i2G is removed, and as shown in Fig. 13, the (10) «base 1G structure is exposed, and only the bit contact area 122 of the f is exposed. The basin ^ /, the opening of the mask 140 is larger than the size of the subsequent bit line contact to ensure that the 4 vertical line contacts the θ4 electrical layer contact. Then, a -働彳 step, such as reactive ion remneration or plasma etching, is performed. You remove the conductive region _ 961 and extend to the position of the bit contact with the spit domain 122, , , 77 " The germanium contact area 122, and the remaining defects, such as the base and the dielectric material 22, are at the corners of the layer. As a result, subsequent formation of the bit line contact 152 in the interlayer dielectric 51 does not occur with the conductive spacer 961 as in the 14th round. In addition, the wall (4) wall trap has already avoided the problem of leakage. By using the non-volatile memory array manufacturing method of the present invention, it is possible to effectively avoid short-circuiting by the word bit line contact. Furthermore, #记忆_ can avoid the problem of erroneously judging the cell failure when erasing. Although the invention (10) is recorded to supplement the invention, it is used to define the invention, and the person who is the person of the white body, Lin _ this batch and Fan _, Run Department, so she touched the view of the plucked object & [Simplified description of the schema] The leader of the circle shall prevail. Fig. 1 to Fig. 6 are the process sections of the direction of the hairline of the hair of the hair; a non-volatile memory array along the word Fig. 7 is the sixth view after the mask;
0593-A40569TWF 10 1281232 第8圖為本發明較佳實施例中製造非揮發性記憶體陣列沿字元線方向 的製程剖面圖；以及 ^ 第9圖至第14圖為本發明較佳實施例中製造非揮發性記憶體陣列沿位 • 元線方向的製程截面圖。 【主要元件符號說明】 基底〜10 ;介電層〜22 ;氧化層〜12 ;第一導電層〜14 ;絕緣層〜16 ; 遮罩〜17;閘極介電層〜18;第二導電層層〜24;絕緣層〜26;遮罩〜101 ; φ 堆疊結構〜910 ;氧化層〜90 ;絕緣間隙壁〜92 ;氧化層〜94 ;遮罩〜120 ; 遮罩〜94 ;缺陷〜110 ;位元線接觸區域〜122 ;導電間隙壁〜961 ;源極線 區域〜124 ;第一摻雜區〜1241 ;第二摻雜區〜134 ;位元線〜160 ;層間介 電層〜150 ;接觸窗〜151 ;位元線接觸〜152 0593-A40569TWF 110593-A40569TWF 10 1281232 FIG. 8 is a cross-sectional view of a process for fabricating a non-volatile memory array along a word line direction in accordance with a preferred embodiment of the present invention; and FIGS. 9 through 14 are preferred embodiments of the present invention A process cross-section of the non-volatile memory array along the direction of the meta-line. [Major component symbol description] Substrate ~10; Dielectric layer ~22; Oxide layer ~12; First conductive layer ~14; Insulation layer ~16; Mask ~17; Gate dielectric layer ~18; Second conductive layer Layer ~ 24; insulating layer ~ 26; mask ~ 101; φ stacked structure ~ 910; oxide layer ~ 90; insulating spacer ~ 92; oxide layer ~ 94; mask ~ 120; mask ~ 94; defect ~ 110; Bit line contact area ~ 122; conductive spacer ~ 961; source line area ~ 124; first doped area ~ 1241; second doped area ~ 134; bit line ~ 160; interlayer dielectric layer ~ 150; Contact window ~ 151; bit line contact ~ 152 0593-A40569TWF 11