TW200816391A - Method of manufacturing split gate flash device - Google Patents

Method of manufacturing split gate flash device Download PDF

Info

Publication number
TW200816391A
TW200816391A TW95136200A TW95136200A TW200816391A TW 200816391 A TW200816391 A TW 200816391A TW 95136200 A TW95136200 A TW 95136200A TW 95136200 A TW95136200 A TW 95136200A TW 200816391 A TW200816391 A TW 200816391A
Authority
TW
Taiwan
Prior art keywords
layer
gate
forming
circuit region
oxide layer
Prior art date
Application number
TW95136200A
Other languages
Chinese (zh)
Inventor
Chin-Chung Wang
Houng-Chi Wei
Original Assignee
Powerchip Semiconductor Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Powerchip Semiconductor Corp filed Critical Powerchip Semiconductor Corp
Priority to TW95136200A priority Critical patent/TW200816391A/en
Publication of TW200816391A publication Critical patent/TW200816391A/en

Links

Landscapes

  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)

Abstract

A method for fabricating a split gate flash device is described. A substrate includes a memory cell region, a high voltage circuit region and a low voltage circuit region is provided. A first oxide layer is formed on the substrate in the high voltage circuit region. A second oxide layer is formed on the substrate in the low voltage circuit region. A first conductive layer is formed on the first and second oxide layers. A tunneling oxide layer is formed on the substrate in the memory cell region. Stack gate structures are formed on the tunneling oxide layer. A conformal third oxide layer is formed on the substrate in the memory cell region. A second conductive layer is formed on the third oxide layer. A portion of the second conductive layer is removed. The first conductive layer is patterned to form gates of the high/low voltage devices.

Description

200816391200816391

Pt.ap653 21245twf.doc/t 九、發明說明: 【發明所屬之技術領域】 β 暇有關於—種半導體元件的製造方法,且特別 =有關於-種分離閘極快閃記憶體的製造方法。 【先前技術】 用於HVt/,體(nonvoIatile mem〇ry)現今被應 -子m,如用於儲存結構資料、程式 〇 二:44。快閃記憶體是-種非揮發性記憶體,由 I、可以進行多次資料存人、讀取與清除等的動 作’因此成為半導體市場中成長頗為快速的產品。 近來為了降低半導體元件的製造成本並簡化製 程’將記憶體的記憶胞區(mem〇ry cell)與週邊電路區 (P:hery circuit)的元件整合在同一晶片上已逐漸 種赵勢。舉例來說,將快閃記憶體與週邊電路 广件整合在同一晶片上,則稱之為喪入式快閃記憶體 edded fiash memory)。另外,在考慮到記憶胞區 I ·中的凡件^求可靠度(reliability)、週邊電路區中的元 件則追求高效能(high perf〇rmance)以及元件施加電 壓的高低等條件下,需要對應記憶胞區與週邊電路區 之70件特性,而於閘極或堆疊閘極結構與基底之間設 置不同厚度的氧化層,以使元件在操作上可以達到要 求。 舉例來說,圖1所繪示為習知之快閃記憶體結構 勺nj面圖此結構包括基底100、穿隨介電層11〇、 6 200816391 pt.ap653 21245twf.doc/t 高溫氧化層112、閘氧化層114、堆疊閘極結構120、 抹除閘極140、選擇閘極142、高壓元件之閘極144 與低壓元件之閘極146。基底100包括記憶胞區 102、高壓電路區104與低壓電路區106。上述各區 域由隔離結構108隔離,而高壓電路區104與低壓 電路區106組合即為週邊電路區。堆疊閘極結構120 包括由穿隧介電層開始依序為浮置閘極122、閘間 介電層124、控制閘極126與頂蓋層130。其中,控 制閘極126包括摻雜多晶石夕層126a與金屬石夕化物層 126b 〇 值得注意的是,記憶胞區102中的選擇閘極142 與浮置閘極122之間的多晶石夕層間氧化層(Internal poly oxidation,IPO)是由高溫氧化層112與閘氧化層114所構 成。高壓電路區104中的高壓元件之閘極144與基底100 之間的閘氧化層以及記憶胞區102中的選擇閘極142 與基底100之間的閘氧化層同樣是由穿隧介電層110、高 溫氧化層112與閘氧化層114所構成。低壓電路區106 中的低壓元件之閘極146與基底100之間設置一層閘 氧化層114。 為了增加記憶體抹除的速度,會減少記憶胞區中之多 晶石夕層間氧化層的厚度。然而,在習知的快閃記憶體中, 記憶胞區102中的多晶矽層間氧化層與高壓元件的閘氧 化層具有相同的高溫氧化層112與閘氧化層114,在減少 記憶胞區102中之多晶矽層間氧化層的厚度的同時,高壓 7 200816391 pt.ap653 21245twf.doc/t 元件之閘氧化層的厚度也隨之減少,會降低「時依性介電 朋潰(Time_Dependent Dielectric Breakdown ; TDDB ) 的測试值,而造成高壓元件的壽命縮短,使得高壓元件 可靠度降低。 ' 此外’位於高壓電路區1〇4及低壓電路區1〇6中之隔 _ 離結構108邊緣的閘氧化層會因為在製造過程中進行清洗 ' 製程而變薄,而降低高壓元件及低壓元件的電性。 【發明内容】 有鑑於此,本發明的目的就是在提供一種分離閘極快 閃記憶體的製造方法,能增加高壓元件之閘氧化層的厚度。 制1本發明的再一目的是提供一種分離閘極快閃記憶體的 製造方法,可解決高壓電路區及低壓電路區中之隔離結構 邊緣的閘氧化層變薄的問題。 曰本發明提出一種分離閘極快閃記憶體的製造方法,首 先提供-基底,包括記憶胞區、高壓電路區及低壓電路區, {;且基底中已形成有多個隔離結構。接著,於高壓電路區中 的基底亡开1第一氧化層。然後,於低壓電路區中的基底 上形成第二氧化層。接下來,於高壓電路區中的第一氧化 層與低壓電路區中的第二氧化層上形成第—導體層。之 ί,於記憶胞區中的基底上形成穿隧氧化層。隨後,於記 心胞區中的牙隧介電層上形成多個堆疊閘極結構。繼之, 於^I胞區中的基底上形成共形的第三氧化層。再者,於 胞區中的弟三氧化層上形成第二導體層。隨後,移除 。己區中的分第二導體層。接著,圖案化第一導體層, 8 200816391 pt.ap653 21245twf.doc/t 以於高壓電路區中形成多個高壓元件 路區中形成多個低壓元件之閘極。 依:本發明的:較佳實施例所述,在上述之分離間極 !·、I己fe體的製邊方法中’堆疊閘極結構包括從穿随 層開始依序為第,閘極、閘間介電層、第二閘極、項蓋層。 依照本發明的一較佳實施例所述,在上述之u 體的Ϊ造方法中,堆疊閘極結構更包括間隙i: c t;: ;、盖層與第二閘極兩側,且位於閘間介電層上。 依照本發明的-較佳實施例所述二 :閃記憶體的製造方法中,第-閘極的材料 快閃記恃方、所述’在上述之分離鬧極 或氧化中’嶋電層的材料包括氧切 依照本發明的一較佳實施 快閃記憶體的製造方法中,第一丄二,刀離閘極 或多晶石夕化金屬。 閘極的材料為摻雜多晶石夕 =本發明的—較佳實施例所述,在才 決閃处體的製造方法中,頂+去 刀離間極 依照本發明的一較佳ς ^化括乳化石夕。 快閃記憶體的製造方法中,於心=在上述之*離閘極 於高厂堅電路區中3^成第—氡化層。接箸, 然後,移除未被第成第-圖案化罩幕層。 固木化罩幕層覆i住的第一氧化層。 cPt.ap653 21245twf.doc/t IX. Description of the Invention: [Technical Fields of the Invention] β 暇 relates to a method of manufacturing a semiconductor device, and particularly to a method for manufacturing a separated gate flash memory. [Prior Art] For HVt/, the body (nonvoIatile mem〇ry) is now used to store structure data, program 〇 2:44. Flash memory is a kind of non-volatile memory. It can perform multiple data storage, reading and erasure operations. It has become a fast-growing product in the semiconductor market. Recently, in order to reduce the manufacturing cost of a semiconductor element and simplify the process, it has been gradually developed to integrate the memory cell of the memory with the components of the peripheral circuit (P:hery circuit) on the same wafer. For example, if the flash memory and the peripheral circuit are integrated on the same chip, it is called edded fiash memory. In addition, in consideration of the reliability in the memory cell area I, the components in the peripheral circuit area are required to be high-performance (high perf〇rmance) and the voltage applied to the device, etc. There are 70 characteristics of the memory cell area and the peripheral circuit area, and oxide layers of different thicknesses are disposed between the gate or the stacked gate structure and the substrate, so that the components can be operated in operation. For example, FIG. 1 is a schematic view of a conventional flash memory structure. The structure includes a substrate 100, a dielectric layer 11 〇, a 611016 pt.ap653 21245 twf.doc/t high temperature oxide layer 112, The gate oxide layer 114, the stacked gate structure 120, the erase gate 140, the select gate 142, the gate 144 of the high voltage component, and the gate 146 of the low voltage component. The substrate 100 includes a memory cell region 102, a high voltage circuit region 104, and a low voltage circuit region 106. Each of the above regions is isolated by an isolation structure 108, and the high voltage circuit region 104 is combined with the low voltage circuit region 106 to be a peripheral circuit region. The stacked gate structure 120 includes a floating gate 122, an inter-gate dielectric layer 124, a control gate 126 and a cap layer 130, starting from the tunneling dielectric layer. The control gate 126 includes a doped polysilicon layer 126a and a metallization layer 126b. It is noted that the polycrystalline stone between the selective gate 142 and the floating gate 122 in the memory cell region 102. The internal polyoxidation (IPO) is composed of a high temperature oxide layer 112 and a gate oxide layer 114. The gate oxide layer between the gate 144 of the high voltage device and the substrate 100 in the high voltage circuit region 104 and the gate oxide layer between the gate 142 and the substrate 100 in the memory cell region 102 are also tunneled dielectric layer 110. The high temperature oxide layer 112 and the gate oxide layer 114 are formed. A gate oxide layer 114 is disposed between the gate 146 of the low voltage component in the low voltage circuit region 106 and the substrate 100. In order to increase the speed of memory erasing, the thickness of the polycrystalline oxide layer in the memory cell region is reduced. However, in the conventional flash memory, the polysilicon interlayer oxide layer in the memory cell region 102 has the same high temperature oxide layer 112 and gate oxide layer 114 as the gate oxide layer of the high voltage device, and is reduced in the memory cell region 102. At the same time as the thickness of the polycrystalline tantalum oxide layer, the thickness of the gate oxide layer of the high voltage 7 200816391 pt.ap653 21245twf.doc/t element is also reduced, which reduces the "Time_Dependent Dielectric Breakdown (TDDB)". The test value causes the life of the high voltage component to be shortened, so that the reliability of the high voltage component is lowered. 'In addition, the gate oxide layer in the high voltage circuit region 1〇4 and the low voltage circuit region 1〇6 is separated from the edge of the structure 108. In the manufacturing process, the cleaning process is thinned to reduce the electrical properties of the high voltage component and the low voltage component. SUMMARY OF THE INVENTION In view of the above, it is an object of the present invention to provide a method for fabricating a split gate flash memory. The thickness of the gate oxide layer of the high voltage component can be increased. A further object of the present invention is to provide a method for manufacturing a split gate flash memory, which can solve the high voltage. The problem of thinning the gate oxide layer at the edge of the isolation structure in the road area and the low voltage circuit area. The present invention provides a method for manufacturing a separated gate flash memory, which first provides a substrate including a memory cell region, a high voltage circuit region, and a low voltage circuit region, {; and a plurality of isolation structures have been formed in the substrate. Then, the substrate in the high voltage circuit region is depleted of a first oxide layer. Then, a second oxide layer is formed on the substrate in the low voltage circuit region. Next, a first conductor layer is formed on the first oxide layer in the high voltage circuit region and the second oxide layer in the low voltage circuit region, and a tunneling oxide layer is formed on the substrate in the memory cell region. Subsequently, A plurality of stacked gate structures are formed on the tunnel dielectric layer in the cell region. Subsequently, a conformal third oxide layer is formed on the substrate in the cell region. Furthermore, the brother in the cell region Forming a second conductor layer on the trioxide layer. Subsequently, the second conductor layer in the region is removed. Then, the first conductor layer is patterned, 8 200816391 pt.ap653 21245twf.doc/t in the high voltage circuit region Forming a plurality of high-voltage component road regions The gate of a plurality of low voltage components. According to the preferred embodiment of the present invention, in the method of edge separation of the above-mentioned separated interpoles, the stacking gate structure includes starting from the crossing layer. In order to be the first, the gate, the inter-gate dielectric layer, the second gate, and the cap layer. According to a preferred embodiment of the present invention, in the method of manufacturing the u body, the stacked gate structure Furthermore, the gap i: ct;:;, the cover layer and the second gate are both sides, and are located on the inter-gate dielectric layer. In the method for manufacturing the flash memory according to the preferred embodiment of the present invention, The material of the first gate is flashed, and the material of the 'electrode layer in the above-mentioned isolated or oxidized layer' includes the oxygen-cutting method in the flash memory according to a preferred embodiment of the present invention. One or two, the knife is away from the gate or polycrystalline stone. The material of the gate is doped polycrystalline as in the preferred embodiment of the present invention. In the manufacturing method of the flashing body, the top + stripping pole is in accordance with a preferred embodiment of the present invention. Including emulsifying stone eve. In the manufacturing method of the flash memory, Yu Xin = in the above-mentioned * off gate in the Gaochangjian circuit area 3^ into the first 氡 layer. Then, the removed first-patterned mask layer is removed. The solidified cover layer covers the first oxide layer. c

L 200816391 pt.ap653 21245twf.doc/t 接下來,移除第一圖案化罩幕層。 依照本發明的-較佳實施例所述,在上述之分離閑極 =記憶體的製造方法中,第—導體層的形成方法為先於 土底上形成第-導體材料層。接著,於高壓電路區及低壓 祕區中的導體材料層上形成第二圖案化罩幕層。然後, 移除未被第二圖案化罩幕層覆蓋住的第一導體材料層。接 下來,移除第二圖案化罩幕層。 依照本發明的一較佳實施例所述,在上述之分離問極 快閃記憶體的製造方法中,記憶胞區中的部份第二導體層 的移除方法包括回蝕刻法。 β本發明提出一種分離閘極快閃記憶體的製造方法,首 ,,仏基底,包括記憶胞區、高壓電路區及低壓電路區。 ^於基底上形成第—氧化層。再者,於基底中形成多 固隔離結構。繼之,移除記憶胞區與低壓電路區中的第一 然後,於低壓電路區中的基底上形成第二氧化層。 ^下來’於南㈣路區中的第一氧化層與低壓電路區中的 匕層上形成第一導體層。接下來,於記憶胞區中的 匕:„化層。之後’於記憶胞區中的穿隧介電 二成共結構。繼之’於記憶胞區中的基底 化#上开^第化層。再者’於記憶胞區中的第三氧 層:接著,圖案化第一導體層,以於高壓電路區二 壓元件之間極’且於低壓電路區中形成多個低 10 200816391 pt.ap653 21245twf.d〇c/t 依照本發明的—I 、 快閃記憶體的芒方只細W所述,在上述之分離閘極 二一除路 形成第一圖宰化置墓a ^甲的弗一虱化層上 層覆蓋住的第=著,移除未被第-圖案化罩幕 層'然後,移除第—圖案化罩幕層。 體的ί造方法中,所提出的分離間極快間記憶 o 擇閘極的閘氧化層—钯报士、&3彳s隹衣釭上亚非與逬 地捭加-丄成而是個別形成,因此可以有效 曰:土牛之閘乳化層的厚度,以提高TDDB的測試 值,可以延長高屢元件的壽命,提升高壓元件的可靠度。 /此外,由於在形成高麼元件與低壓元件的閘氧化層又之 後,就直接,閘氧化層上形成用以形成閉極的導體層:因 此y以改善南愿電路區及低壓電路區中之隔離結構邊緣的 間氧化層因清洗製程而變薄的問題,以提升高 壓元件的電性。 低 “為讓本發明之上述和其他目的'特徵和優點能更明顯 易懂,下文特舉較佳實施例,並配合所附圖式,作詳細說 明如下。 、ϋ 【實施方式】 圖2Α至圖2Η所緣示為本發明一實施例之分離閘極快 閃記憶體的製造流程剖面圖。 首先,請參照圖2Α。提供基底200,基底200例如是 矽基底。基底200包括記憶胞區202、高壓電路區2〇4與 低壓電路區206,且基底200中已形成有隔離結構2〇8, 200816391 pt.ap653 21245twf.doc/t 各區域皆由隔離結構208隔離,而高壓電路區204與 低壓電路區206組合即為週邊電路區。 此外,還可以分別對記憶胞區2〇2、高壓元件區2〇4 與低壓元件區206中的基底200進行離子植入製程,以於 記憶胞區202、高壓元件區2G4與低壓元件區施的基底 200中形成#雜井區及其它摻雜區。其巾,離子植入的材 貝可以是η型或p型,將視其元件之設計而定。且其製程L 200816391 pt.ap653 21245twf.doc/t Next, remove the first patterned mask layer. According to a preferred embodiment of the present invention, in the above method of manufacturing the separation of the dummy/memory, the first conductor layer is formed by forming a first conductor material layer on the soil floor. Next, a second patterned mask layer is formed over the layer of conductive material in the high voltage circuit region and the low voltage secret region. Then, the first layer of conductor material not covered by the second patterned mask layer is removed. Next, the second patterned mask layer is removed. According to a preferred embodiment of the present invention, in the above method of fabricating a separate flash memory, a method of removing a portion of the second conductor layer in the memory cell region includes an etch back method. The present invention provides a method for fabricating a split gate flash memory, the first, and the germanium substrate, including a memory cell region, a high voltage circuit region, and a low voltage circuit region. ^ Forming a first oxide layer on the substrate. Furthermore, a multi-separation structure is formed in the substrate. Next, the first of the memory cell region and the low voltage circuit region is removed. Then, a second oxide layer is formed on the substrate in the low voltage circuit region. The first conductor layer is formed on the first oxide layer in the south (four) road region and the germanium layer in the low voltage circuit region. Next, the 匕 in the memory cell: 化化. After the tunneling dielectric in the memory cell two-co-structure. Following the 'basicization in the memory cell area' Furthermore, the third oxygen layer in the memory cell region: then, the first conductor layer is patterned to form a plurality of low voltages between the two voltage elements in the high voltage circuit region and in the low voltage circuit region 10 200816391 pt. Ap653 21245twf.d〇c/t In accordance with the present invention, the smear of the flash memory is only described by the fine W, and the first gate of the separation gate is formed by the above-mentioned separation gate to form the first map. The upper layer covered by the upper layer is removed, the first layer is not patterned, and then the first patterned layer is removed. Then, the proposed separation layer is removed. Quick memory o Selective gate gate oxide layer - palladium reporter, & 3 彳 隹 釭 釭 亚 亚 亚 釭 釭 釭 釭 釭 釭 釭 釭 釭 釭 釭 釭 釭 釭 釭 釭 釭 釭 釭 釭 釭 釭 釭 釭 釭 釭 釭 釭 釭 釭 釭 土 土 土The thickness to increase the test value of TDDB can prolong the life of high-order components and improve the reliability of high-voltage components. After the gate oxide layer of the device and the low voltage component, the conductor layer for forming the closed electrode is formed directly on the gate oxide layer: thus y is used to improve the interlayer oxide layer at the edge of the isolation structure in the south and low voltage circuit regions. The problem of thinning due to the cleaning process is to improve the electrical properties of the high-voltage component. The features and advantages of the above-mentioned and other objects of the present invention are more clearly understood, and the preferred embodiments are exemplified below. The drawings are described in detail below. [Embodiment] FIG. 2A to FIG. 2B are cross-sectional views showing a manufacturing process of a split gate flash memory according to an embodiment of the present invention. First, please refer to Figure 2Α. A substrate 200 is provided, such as a tantalum substrate. The substrate 200 includes a memory cell region 202, a high voltage circuit region 2〇4 and a low voltage circuit region 206, and an isolation structure 2〇8 has been formed in the substrate 200, and each region is isolated by the isolation structure 208. The combination of the high voltage circuit region 204 and the low voltage circuit region 206 is a peripheral circuit region. In addition, the ion implantation process can be performed on the memory cell 2〇2, the high voltage device region 2〇4, and the substrate 200 in the low voltage device region 206, respectively, for the memory cell region 202, the high voltage device region 2G4, and the low voltage device region. The #well zone and other doped zones are formed in the substrate 200. For the towel, the ion implanted material may be either n-type or p-type, depending on the design of the component. And its process

c 方法應為此技術領域中具有通常知識者所熟知,故於此不 再贅述。 接著,於基底200上形成氧化層21〇。氧化層21〇的 材料例如是氧化㊉,其形成方法例如是熱氧化法。 在本實施例是先於基底200中形成隔離結構2〇8,再 於基底200上形成氧化層21G,但並不用以限制本發明。 在另-實施例中’可先於基底·上形成氧化層21〇,再 於基底200中形成隔離結構2〇8,而隔離結構施例 淺溝渠隔離結構,其軸方法為於此技術賴具有通常知 識者所周知,故於此不再贅述。 、、’k之’杯照圖2B,於記憶胞區2〇2與麵電 2〇4中的氧化層210上形成圖案化草幕層212。电路[ 然^ ’移除未被目帛化罩幕j 212覆蓋絲氧化 210’而南壓電路區204 Φ辦® πτ十Λ γ p 元件之門d 下來的氧化層210作為高壓 兀件之閘魏層,其移除方法例如是乾式_法。 202 ^此^例中,轉化罩幕層212是形成在記憶胞區 搬與碰電路區綱中的氧化層21()上,所 12 200816391 pt.ap653 21245twf.doc/t 化罩幕層212作為罩幕時,只移除了低壓電路區2〇6中的 氧化層210,而記憶胞區2〇2中的氧化層21〇會於後續製 程中移除。在另一實施例中,可將圖案化罩幕層212只形 成於咼壓電路區204中的氧化層21〇上,因此在以圖案化 =層212作為罩幕時,會同時移除未被圖案化罩幕層 復盍住之位於記憶胞區202及低壓電路區2〇6中的氧化層 〇 接下來,請參照圖2C,移除圖案化罩幕層212,其移 除方法例如疋灰化或鍅刻法。然後,於低壓電路區2⑽中 / 土底,上形成氧化層214,其形成方法例如是乾式氧 、=法或疋原位洛汽生成(m situ ste_卿⑽廿〇n,ISSG) #舜請參照圖2D,於基底200上形成導體層216, 、’设瓜;氣化層;21〇與氧化層214上。導體声 例如是摻雜吝曰於 ^ V體層216的材料 積法其形成綠例如是先以化學氣相沈 u I細化^雜多㈣層’接著再進行摻雜製程,或者是 - 予軋相沈積法形成臨場摻雜多晶矽層。 .層電路區204及低壓電路區206中的導體 1成圖案化罩幕層218。 蓋住的''導4體圖f,移除未被圖案化罩幕層218覆 化芦210、,而留下形成於高壓電路區204中之氧 216。其中=區206中之氧化層214上的導體層 216的方法化罩幕層218覆蓋住的導體層 疋乾式钱刻法。接下來,移除圖案化罩幕 13 200816391 pt.ap653 21245twf.d〇c/t 層218 其移除方法例如是灰化或侧法。 之後翏照圖2F,移除位於記憶胞區2〇2中之基底 200上的氧化層21〇,其移除方法例如是乾式侧法。 a ^妾者^記憶胞區2〇2中的基底200上形成穿隧氧化 層220。牙隨介電層22〇的材料例如是氧化石夕,其形成方 法例如是熱氧化法。之後,於記憶胞區2〇2中的穿隨介電 層220上形成堆疊閘極結構222。 o 堆閘極結構222從穿隧介電層22〇開始例如是依序 為第一,極224、閑間介電層226、第二閑極228、頂蓋層 23=堆豐閘極結構222還包括間隙壁加,位於頂蓋層^ 與第二間極,兩侧壁,且位於閘間介電層226二曰 、〔、中第閘極224的材料例如是摻雜多晶石夕,其形 f方法例如是先化學氣相沈積法形成未摻雜多㈣層Ϊ接 雜製程;或者是直接以化學氣相沈積法开;成臨 矽層。閘間介電層]的材料例如是氧化矽或 =化^/鼠切/氧切,其形成方法例如是化學氣相沈積 /夕。弟一閘極228的材料例如是導體層,如摻雜多晶石夕或 二=8a與金屬石夕化物層島所組成。其中換雜多晶石夕 成方法與第—閘極224相同,而金屬石夕化物層 的材料例如是魏鶴、魏欽、魏钻、魏知 如是如是作為浮置閘極;第™ 14 200816391 ptap653 21245twf.doc/t 另外,頂蓋層230例如是單層結 2施與頂蓋層现所組成的兩層如=者是由頂蓋層 的材料例如是氧化石夕、氣化石夕、氣氧化H。單層頂蓋層 其形成方法例如是先形成頂蓋材料層,^其他合適材料, 蝕刻法移除部分頂蓋材料層。另外,者再以非等向性 層230a的材料例如是氮化石夕、氮氧化叠結構之頂蓋 而頂蓋層230b的材料例如是四乙声 ^其他合適材料。The method should be well known to those of ordinary skill in the art and will not be described again. Next, an oxide layer 21 is formed on the substrate 200. The material of the oxide layer 21 is, for example, oxidized ten, and its formation method is, for example, a thermal oxidation method. In the present embodiment, the isolation structure 2〇8 is formed in the substrate 200, and the oxide layer 21G is formed on the substrate 200, but is not intended to limit the present invention. In another embodiment, an oxide layer 21〇 may be formed on the substrate, and an isolation structure 2〇8 may be formed in the substrate 200, and the isolation structure is applied to the shallow trench isolation structure, and the axis method is It is generally known to the person skilled in the art, so it will not be repeated here. The 'k' cup is shown in Fig. 2B, and a patterned grass layer 212 is formed on the oxide layer 210 in the memory cell 2〇2 and the surface electrode 2〇4. The circuit [ 然 ^ ' removes the unmasked mask j 212 covering the wire oxide 210 ' and the south voltage circuit region 204 Φ ® π Λ Λ γ p 元件 p element gate d down the oxide layer 210 as a high voltage component The gate layer, the removal method is, for example, a dry method. 202 ^ In this example, the conversion mask layer 212 is formed on the oxide layer 21 () in the memory cell area and the touch circuit area, and 12 12,216,391 pt.ap653 21245 twf.doc/t mask layer 212 is used as In the case of the mask, only the oxide layer 210 in the low voltage circuit region 2〇6 is removed, and the oxide layer 21〇 in the memory cell region 2〇2 is removed in the subsequent process. In another embodiment, the patterned mask layer 212 can be formed only on the oxide layer 21〇 in the stamping circuit region 204, so that when the pattern=layer 212 is used as a mask, the unmasked layer is simultaneously removed. The oxide layer in the memory cell region 202 and the low voltage circuit region 2〇6 is rewritten by the patterned mask layer. Next, referring to FIG. 2C, the patterned mask layer 212 is removed, and the removal method is, for example, ash. Or engraving. Then, an oxide layer 214 is formed on the low-voltage circuit region 2 (10) / soil bottom, and the formation method thereof is, for example, dry oxygen, = method or 疋 in situ vapor generation (m situ ste_qing (10) 廿〇 n, ISSG) #舜Referring to FIG. 2D, a conductor layer 216, a melon, a gasification layer, and a ruthenium layer 214 are formed on the substrate 200. The conductor sound is, for example, a material solution method of doping the V body layer 216 to form a green color, for example, first chemical vapor deposition, refining the poly(four) layer, and then performing a doping process, or - pre-rolling The phase deposition method forms a field-doped polysilicon layer. The conductors 1 in the layer circuit region 204 and the low voltage circuit region 206 are patterned to form a mask layer 218. The covered 'body 4' is removed, and the unmasked mask layer 218 is removed to cover the reed 210, leaving the oxygen 216 formed in the high voltage circuit region 204. Wherein the conductor layer 218 of the conductor layer 216 on the oxide layer 214 in the region 206 is covered by the conductor layer. Next, the patterned mask is removed 13 200816391 pt.ap653 21245twf.d〇c/t Layer 218 The removal method is, for example, ashing or side method. Next, referring to Fig. 2F, the oxide layer 21A on the substrate 200 in the memory cell region 2'2 is removed, and the removal method is, for example, a dry side method. A tunneling oxide layer 220 is formed on the substrate 200 in the memory cell region 2〇2. The material of the teeth with the dielectric layer 22 is, for example, oxidized stone, and the method of forming it is, for example, a thermal oxidation method. Thereafter, a stacked gate structure 222 is formed on the pass-through dielectric layer 220 in the memory cell region 2〇2. The stack gate structure 222 is, for example, sequentially first from the tunnel dielectric layer 22, the pole 224, the idle dielectric layer 226, the second idle pole 228, and the cap layer 23 = the stack gate structure 222 The utility model further includes a spacer layer, a top cover layer and a second interpole, and two side walls, and the material of the dielectric layer 226 of the gate is 226, and the material of the middle gate 224 is, for example, doped polycrystalline stone. The shape f method is, for example, a chemical vapor deposition method to form an undoped multi-(four) layer tantalum bonding process; or a direct chemical vapor deposition method; The material of the inter-gate dielectric layer is, for example, yttrium oxide or yttrium/mouse/oxygen cutting, and the formation method thereof is, for example, chemical vapor deposition. The material of the gate 228 is, for example, a conductor layer, such as doped polycrystalline stone or bis = 8a and a metal ceramsite island. The method for changing the polycrystalline spine is the same as that of the first gate 224, and the materials of the metallization layer are, for example, Wei He, Wei Qin, Wei D, and Wei Zhi as the floating gate; TM 14 200816391 Ptap653 21245twf.doc/t In addition, the top cover layer 230 is, for example, a single layer of the junction 2 and the top cover layer is composed of two layers, such as the material of the top cover layer, such as oxidized stone, gasification, and gas. Oxidize H. The single-layer cap layer is formed by, for example, forming a cap material layer, other suitable materials, and removing a portion of the cap material layer by etching. Further, the material of the anisotropic layer 230a is, for example, a top cover of a nitride nitride or oxynitride structure, and the material of the cap layer 230b is, for example, a tetra-bright material.

O 材料。頂蓋層2施與頂蓋層2鳥:^層或其他合適 基底2〇0上依序形成頂蓋層2地的材^方^例如是先於 的材料層,接著再以轉向性勤 “ ^蓋層2施 堆疊間極結構奶的形成方法例如= 刀上述材料層。 f層的材料層,再圖案化上述所有卵其中所有 220的表面。 、曰直至牙隧介電層 隨後,請參照圖2G,於基 層234。氧化層234的形成方法例 形成共形的氧化 ϋ 物的沈積製程。 疋進仃一個高溫氧化 繼之’於氧化層说上形 的材料例如是摻雜 =㈣。導體層 氣相沈積法形成未摻雜多曰糾If法例如是先以化學 ί構Γ2中的部份導體層,“堆叠 構222中最外側一閑極236,以及於堆疊閘極結 形成第四構222之其中之-的鞭 亚可同衿移除高壓電路區204與低壓 15 200816391 pt.ap653 21245twf.doc/t 祕區,的導體層,其移除的方法例如是 再者,言月麥照圖2H,圖案化導體層2]6 = 路區204中形成縫元件之間極細,且於健電 中形成健元件之間極242,而在圖案化導體/^\206 時,會-併圖案化高壓電路區2〇4及低屡電路^^ 穿隧介電層220及氧化層234。 — 。口 勺 甶於 e ㈣㈣元件之職化層的氧化層別在O material. The top cover layer 2 is applied to the top cover layer 2 to form a layer of the top cover layer 2 on the layer of the bird layer or the other suitable substrate 2〇0, for example, the material layer before the substrate layer, and then the steering property is diligently ^The cover layer 2 is formed by stacking the structure milk of the stack, for example, the above-mentioned material layer of the knife. The material layer of the f layer, and then patterning all the surfaces of all the above-mentioned eggs, 曰, until the tunnel dielectric layer, please refer to 2G, in the base layer 234. The formation method of the oxide layer 234 is a deposition process for forming a conformal cerium oxide. A high temperature oxidation followed by a material in the oxide layer is, for example, doping = (4). The layered vapor deposition method forms an undoped multi-turn correction method, for example, by chemically constructing a portion of the conductor layer in the Γ2, "the outermost one of the stacks 222, 236, and the stacking gate junction forming a fourth The whip of the structure 222 can remove the high voltage circuit region 204 and the low voltage 15 200816391 pt.ap653 21245twf.doc/t secret area, the method of removing the conductor layer, for example, is again According to Figure 2H, the patterned conductor layer 2]6 = very fine between the seam elements formed in the road zone 204, The pole 242 between the health components is formed in the power grid, and when the conductor /^\206 is patterned, the high voltage circuit region 2〇4 and the low voltage circuit tunneling dielectric layer 220 and the oxide layer 234 are patterned and patterned. . — . The oxidized layer of the occupational layer of the e (four) (four) component

上是個別形成,並非與第四· 238(選擇 = (由穿遂氧化層220及氧化層234 以個別控制祕層21〇的厚度,因此能有效地增加高廢元 件之閘氧化層的厚度。此外,由於高壓元件之職化層 厚度增加,因此能提高TDDB的測試值,且可以二 元件的壽命,提升高壓元件的可靠度。 之長冋反The above is formed separately, not with the fourth 238 (select = (by the thickness of the gate layer 21 by the tantalum oxide layer 220 and the oxide layer 234), so that the thickness of the gate oxide layer of the high-depletion element can be effectively increased. In addition, since the thickness of the service layer of the high-voltage component is increased, the test value of the TDDB can be improved, and the life of the two components can be improved, and the reliability of the high-voltage component can be improved.

此外,由於在形成高壓電路區204及低壓電路區2〇6 中的氧化層21Q及氧化層214之後,就直接在氧化層21〇 及氧化層214上形成用以形成閘極的導體層216,因此可 以改善高壓電路區204及低壓電路區施中之隔離結構 邊緣的氧化層210及氧化層214因清洗製程而變g的 問題,以提升高壓元件及低壓元件的電性。 綜上所述,本發明至少具有下列優點·· 1·由於在本發明所提出的分離閘極快閃記憶體的製造 方法中’而墨元件的閘氧化層在製程上是個別形成,因此 可以有效地增加高壓元件之閘氧化層的厚度。 2·依照本發明所提出的分離閘極快閃記憶體的製造方 16 200816391 pt.ap653 21245twf.doc/t 法所製造的高壓元件具有較高的TDDB測試值、較長的使 用壽命及較高的可靠度。 3·本發明所提出的分離閘極快閃記憶體的裂造方法能 改善咼壓電路區及低壓電路區中之隔離結構邊緣的閘氧化 層因清洗製程而變薄的問題,因此可以所形成的高壓元件 及低Μ元件具有較佳的電性。 o 雖然本發明已以較佳實施例揭露如上,然其並非用以 限疋本發明,任何熟習此技藝者,在不脫 t範圍内,當可作些許之更動朗飾,因此本發明== 摩巳圍當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 # 圖1所繪示為習知之分離閘極快閃記憶體結構的剖面 一實施例之分離閘極快 圖2A至圖2H所緣示為本發明 閃記憶體的製造流程剖面圖。 【主要元件符號說明】In addition, since the oxide layer 21Q and the oxide layer 214 in the high voltage circuit region 204 and the low voltage circuit region 2〇6 are formed, the conductor layer 216 for forming the gate is directly formed on the oxide layer 21 and the oxide layer 214. Therefore, the problem that the oxide layer 210 and the oxide layer 214 at the edge of the isolation structure in the high-voltage circuit region 204 and the low-voltage circuit region are changed by the cleaning process can be improved to improve the electrical properties of the high-voltage component and the low-voltage component. In summary, the present invention has at least the following advantages: 1. In the manufacturing method of the split gate flash memory proposed by the present invention, the gate oxide layer of the ink element is formed separately in the process, and thus Effectively increase the thickness of the gate oxide layer of the high voltage component. 2. The manufacturer of the split gate flash memory according to the present invention 16 200816391 pt.ap653 21245twf.doc/t The high voltage component manufactured by the method has a high TDDB test value, a long service life and a high Reliability. 3. The method for cracking the split gate flash memory proposed by the present invention can improve the problem that the gate oxide layer at the edge of the isolation structure in the rolling circuit region and the low voltage circuit region is thinned by the cleaning process, so The formed high voltage component and low voltage component have better electrical properties. Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the present invention, and anyone skilled in the art can make some modifications when not in the range of t, so the present invention == Capricorn is subject to the definition of the patent application scope attached to it. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a cross-sectional view of a conventional split gate flash memory structure. FIG. 1 is a schematic diagram showing the manufacturing process of the flash memory of the present invention. FIG. Sectional view. [Main component symbol description]

100、200 :基底 102、202 :記憶胞區 104、204 :高壓電路區 106、206 :低壓電路區 108、208 ··隔離結構 110、220 ·穿隨介電層 112 ·南溫氧化層 114 :閘氧化層 17 200816391 pt.ap653 21245twf.doc/t 120、222 :堆疊閘極結構 122 :浮置閘極 124、226 :閘間介電層 126 :控制閘極 126a、228a :摻雜多晶矽層 126b、228b :金屬矽化物層 130、130a、130b、230、230a、230b :頂蓋層 132、232 :間隙壁 140 :抹除閘極 142 :選擇閘極 144、240 :高壓元件之閘極 146、242 :低壓元件之閘極 210、214、234 :氧化層 212、218 :圖案化罩幕層 216 :導體層 224 :第一閘極 228 :第二閘極 236 :第三閘極 238 :第四閘極 18100, 200: substrate 102, 202: memory cell region 104, 204: high voltage circuit region 106, 206: low voltage circuit region 108, 208 · isolation structure 110, 220 · dielectric layer 112 · south temperature oxide layer 114: Gate oxide layer 17 200816391 pt.ap653 21245twf.doc/t 120, 222: stacked gate structure 122: floating gate 124, 226: gate dielectric layer 126: control gate 126a, 228a: doped polysilicon layer 126b 228b: metal telluride layer 130, 130a, 130b, 230, 230a, 230b: cap layer 132, 232: spacer 140: erase gate 142: select gate 144, 240: gate 146 of high voltage component, 242: gates 210, 214, 234 of low voltage components: oxide layers 212, 218: patterned mask layer 216: conductor layer 224: first gate 228: second gate 236: third gate 238: fourth Gate 18

Claims (1)

200816391 pt.ap653 21245twf.doc/t 十、申請專利範圍·· 1·一種分離閘極快閃記憶體的製造方法,包括·· 提供一基底,包括一記憶胞區、一高壓電路區及一低 壓電路區,且該基底中已形成有多個隔離結構; 於該高壓電路區中的該基底上形成一第一氧化層; 於该低廢電路區中的該基底上形成一第二氧化層; 於高壓電路區中的該第一氧化層與該低壓電路區中的 o 遠弟一氧化層上形成一第一導體層; 於該記憶胞區中的該基底上形成一穿隧氧化層; 於該記憶胞區中的該穿隧介電層上形成多個堆疊閘極 結構; 於記憶胞區中的該基底上形成共形的一第三氧化層; 於該記憶胞區中的該第三氧化層上形成一第二導體 層, (j 中的部份該第二導體層;以及 高壓一:體層’以於該高壓電路區中形成多個 之閘極。f…㈣低壓電路區中形成多個低摩元件 2. 如申請專利範圍第 項所述之分離閘極快閃記 憶體 始依第堆疊閘極結構包括從賴介電層開 閘極 蓋層 閘間介電層、一第二閘極 頂 19 200816391 pt.ap653 21245twf.doc/t 的製造方法,其中該第-閘』體 的43請2?第2項所述之分心.々。 5·如申請專利範圍第2 心竹巴帅雜多晶‘ Mi w 項所述之分離閘極 以方法,其中該閘間介雷届ό6从土^ 、网記憶> 石夕/氮化石夕/氧化石夕 o 的制!^申1^專亀圍第2項所述之分離閑極伊門▲ 白衣㈣,其中該第二問極的材料為 曰、::憶體 矽化金屬。 _石夕或多晶 7.如中請專利範圍第2項所述之分離閘極 的^造方法」其中該縣層的材料包括氮切。、體 制A申#專W範圍第1項所述之分離閑極快閃記情奸 W造方法,其巾闕縫電魏巾賴基底上形成· 一氧化層的方法包括: 昂 於该基底上形成該第一氧化層; 安介^壓電路區中的該第」氧化層上形成-第-圖 案化罩幕層; Θ 移除未被該第-_化罩幕層覆蓋住㈣第化 層;以及 移除該第一圖案化罩幕層。 的制9=请2範圍第1項所述之分離閘極快閃記憶體 的錢方法,其中該第—導體層的形成方法包括: 於該基底上形成一第一導體材料層; 於。亥冋[私路區及該低壓電路區中的該導體材料層 20 200816391 pt.ap653 21245twf.doc/t 上形成一第二圖案化罩幕層; 移除未被該第二圖案化罩幕層覆蓋住的該第一導體 材料層,以及 移除該第二圖案化罩幕層。 1(λ如申請專利範圍第1項所述之分離閘極快閃記憶 體的製造方法,其中該記憶胞區中的部份該第二導體層的 移除方法包括回ϋ刻法。 11.一種分離閘極快閃記憶體的製造方法,包括: 提供一基底,包括一記憶胞區、一高壓電路區及一低 壓電路區; 於該基底上形成一第一氧化層; 於該基底中形成多個隔離結構; 移除該記憶胞區與該低壓電路區中的該第一氧化層; 於該低壓電路區中的該基底上形成一第二氧化層; 於高壓電路區中的該第一氧化層與該低壓電路區中的 該第二氧化層上形成一第一導體層; 於該記憶胞區中的該基底上形成一穿隧氧化層; 於該記憶胞區中的該穿隧介電層上形成多個堆疊閘極 結構, 於記憶胞區中的該基底上形成共形的一第三氧化層; 於該記憶胞區中的該第三氧化層上形成一第二導體 層; 移除該記憶胞區中的部份該第二導體層;以及 圖案化該第一導體層,以於該高壓電路區中形成多個 21 200816391 pt.ap653 21245twf.doc/t 南壓7L件之閘極,且於該低壓電路區巾形成多個低壓元件 之閘極。 _ 申請專利範圍第11項所述之分離閘極快閃記憶 體的製造方法’其中該些堆疊閘極結構包括從穿随介電層 開^依序為-第—閘極、一閘間介電層、一第二問極、一 頂蓋層。 體的方申^專圍第12項所述之分離閘極快閃記憶 一、f —法,〃、中該些堆疊閘極結構更包括一間隙壁, 位於,頂1層與該第二閘極兩側,且位於該閘間介電層上。 體的製造所述之分_酬記憶 1 5如由β *、中5亥 閘極的材料包括摻雜多晶矽。 15·如申#專利範圍第12 體的製造方法,其中人之刀離閑極快閃記憶 化石夕/氮切/氧_巾為㈣1電層㈣料包域切或氧 i; 體的12項繼_極快閃記憶 晶石夕化金屬。/' M極的材料為推雜多晶石夕或多 17. 如申睛專利範圍第12項 體的製造方法,t中 、I之刀每隹閘極快閃記憶 18. 如申請翻/jr層的㈣包括氮化石夕。 體的製造方法,”;二11項所述之分離閘極快閃記憶 一氧化層的移除胞區與該低電路區中的該第 於該高壓電路區中 案化罩幕層; 中的遠弟—軋化層上形成—第一圖 22 200816391 pt.ap653 21245twf.doc/t 移除未被該第一圖案化罩幕層覆蓋住的該第一氧化 層;以及 移除該第一圖案化罩幕層。 19. 如申請專利範圍第11項所述之分離閘極快閃記憶 體的製造方法,其中該第一導體層的形成方法包括: 於該基底上形成一第一導體材料層; 於該南壓電路區及該低壓電路區中的該導體材料層 上形成一第二圖案化罩幕層; 移除未被該第二圖案化罩幕層覆蓋住的該第一導體 材料層;以及 移除該第二圖案化罩幕層。 20. 如申請專利範圍第11項所述之分離閘極快閃記憶 體的製造方法,其中該記憶胞區中的部份該第二導體層的 移除方法包括回餘刻法。 C 23200816391 pt.ap653 21245twf.doc/t X. Patent Application Scope 1. A method for manufacturing a separated gate flash memory, comprising: providing a substrate including a memory cell region, a high voltage circuit region and a low voltage a circuit region, and a plurality of isolation structures are formed in the substrate; a first oxide layer is formed on the substrate in the high voltage circuit region; and a second oxide layer is formed on the substrate in the low waste circuit region; Forming a first conductor layer on the first oxide layer in the high voltage circuit region and the far oxide layer in the low voltage circuit region; forming a tunneling oxide layer on the substrate in the memory cell region; Forming a plurality of stacked gate structures on the tunneling dielectric layer in the memory cell region; forming a conformal third oxide layer on the substrate in the memory cell region; and the third in the memory cell region Forming a second conductor layer on the oxide layer, (part of the second conductor layer in j; and a high voltage one: body layer) to form a plurality of gates in the high voltage circuit region. f... (4) forming in the low voltage circuit region Multiple low friction components 2. If applied The split gate flash memory according to the first item of the first aspect of the present invention comprises: a gate dielectric layer and a second gate top 19 from a dielectric layer, and a second gate top 19 200816391 pt.ap653 21245twf. The manufacturing method of doc/t, in which the 43th of the first gate body is 2, the distraction described in the second item. 5 5. If the patent application scope is 2nd, the heart of the bamboo, the handsome polycrystalline 'Mi w item The method for separating the gates is described in which the gates of the gates are 从6 from the soil ^, the net memory > the stone eve / the nitrite eve / the oxidized stone eve o system ^ ^ 1 1 Isolation of the Yimen ▲ White (4), the material of the second questioning pole is: :::Recalling the body of the metal. _ Shi Xi or polycrystalline 7. The separation gate described in the second paragraph of the patent scope The method of the method of manufacturing, wherein the material of the county layer includes nitrogen cutting, and the method of separating the idle flash and the traitor, as described in Item 1 of the system A, the quilting of the electric towel on the substrate. The method of forming an oxide layer includes: forming the first oxide layer on the substrate; and forming the first oxide layer in the circuit region a grading-patterned mask layer; 移除 removing the quaternary layer that is not covered by the first _ mask layer; and removing the first patterned mask layer. The method for separating a gate flash memory according to any one of the preceding claims, wherein the method for forming the first conductor layer comprises: forming a first conductor material layer on the substrate; Forming a second patterned mask layer on the conductive material layer 20 in the circuit region 20 200816391 pt.ap653 21245twf.doc/t; removing the first conductive material layer not covered by the second patterned mask layer And removing the second patterned mask layer. A method for manufacturing a split gate flash memory according to claim 1, wherein a portion of the second cell layer in the memory cell region is removed by a retrace method. A method for fabricating a split gate flash memory, comprising: providing a substrate comprising a memory cell region, a high voltage circuit region and a low voltage circuit region; forming a first oxide layer on the substrate; forming in the substrate a plurality of isolation structures; removing the memory cell region and the first oxide layer in the low voltage circuit region; forming a second oxide layer on the substrate in the low voltage circuit region; the first in the high voltage circuit region Forming a first conductor layer on the second oxide layer in the oxide layer and the low voltage circuit region; forming a tunneling oxide layer on the substrate in the memory cell region; and forming the tunneling layer in the memory cell region Forming a plurality of stacked gate structures on the electrical layer, forming a conformal third oxide layer on the substrate in the memory cell region; forming a second conductor layer on the third oxide layer in the memory cell region; Remove part of the memory cell a second conductor layer; and patterning the first conductor layer to form a plurality of gates of the 21L 161816 pt.ap653 21245 twf.doc/t south voltage 7L in the high voltage circuit region, and forming the low voltage circuit region The gate of a plurality of low-voltage components. _ The method for manufacturing a split gate flash memory according to claim 11 wherein the stacked gate structures comprise from the pass-through dielectric layer —The gate, the dielectric layer of a gate, the second pole, and the top layer. The square gate of the body is the flashing memory of the separation gate described in item 12, f—method, 〃, middle The stacked gate structure further includes a spacer wall located on the two sides of the top layer and the second gate, and located on the dielectric layer of the gate. The manufacturing of the body is as described above. The materials of β* and Zhongwuhai gates include doped polysilicon. 15·The manufacturing method of the 12th body of the patent scope of the patent, in which the knife of the human body is very fast flash memory fossil eve / nitrogen cut / oxygen _ towel is (four) 1 The electric layer (4) is covered by the material or the oxygen is i; the 12 items of the body are _ extremely fast flash memory crystal slabs of metal. / ' M pole material is a push晶石夕或多 17. As in the manufacturing method of the 12th item of the scope of the patent application, the knife in t, I has a flash flash memory. 18. If the application of the /jr layer (4) includes nitriding eve. a manufacturing method, wherein; the separation gate of the separated gate flash memory layer and the low-circuit area of the low-voltage circuit region in the high-voltage circuit region; - forming on the rolled layer - first Figure 22 200816391 pt.ap653 21245twf.doc / t removing the first oxide layer not covered by the first patterned mask layer; and removing the first patterned mask 19. The method of manufacturing the split gate flash memory of claim 11, wherein the method of forming the first conductor layer comprises: forming a first conductor material layer on the substrate; Forming a second patterned mask layer on the conductive material layer in the south voltage circuit region and the low voltage circuit region; removing the first conductive material layer not covered by the second patterned mask layer; And removing the second patterned mask layer. 20. The method of fabricating a split gate flash memory according to claim 11, wherein a portion of the second cell layer in the memory cell region is removed by a re-etching method. C 23
TW95136200A 2006-09-29 2006-09-29 Method of manufacturing split gate flash device TW200816391A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW95136200A TW200816391A (en) 2006-09-29 2006-09-29 Method of manufacturing split gate flash device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW95136200A TW200816391A (en) 2006-09-29 2006-09-29 Method of manufacturing split gate flash device

Publications (1)

Publication Number Publication Date
TW200816391A true TW200816391A (en) 2008-04-01

Family

ID=44769078

Family Applications (1)

Application Number Title Priority Date Filing Date
TW95136200A TW200816391A (en) 2006-09-29 2006-09-29 Method of manufacturing split gate flash device

Country Status (1)

Country Link
TW (1) TW200816391A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103325737A (en) * 2012-03-21 2013-09-25 瑞萨电子株式会社 Method of manufacturing semiconductor device
US10325918B2 (en) 2016-11-29 2019-06-18 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof
US10943996B2 (en) 2016-11-29 2021-03-09 Taiwan Semiconductor Manufacturing Co., Ltd. Method of manufacturing semiconductor device including non-volatile memories and logic devices
US10950611B2 (en) 2016-11-29 2021-03-16 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103325737A (en) * 2012-03-21 2013-09-25 瑞萨电子株式会社 Method of manufacturing semiconductor device
US9391178B2 (en) 2012-03-21 2016-07-12 Renesas Electronics Corporation Method of manufacturing semiconductor device
TWI557808B (en) * 2012-03-21 2016-11-11 瑞薩電子股份有限公司 Method of manufacturing semiconductor device
US10325918B2 (en) 2016-11-29 2019-06-18 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof
US10879253B2 (en) 2016-11-29 2020-12-29 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof
US10943996B2 (en) 2016-11-29 2021-03-09 Taiwan Semiconductor Manufacturing Co., Ltd. Method of manufacturing semiconductor device including non-volatile memories and logic devices
US10950715B2 (en) 2016-11-29 2021-03-16 Taiwan Semiconductor Manufacturing Co., Ltd. Method of manufacturing semiconductor device including non-volatile memories and logic devices
US10950611B2 (en) 2016-11-29 2021-03-16 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof
US11594620B2 (en) 2016-11-29 2023-02-28 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof
US11825651B2 (en) 2016-11-29 2023-11-21 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and manufacturing method thereof

Similar Documents

Publication Publication Date Title
TWI259585B (en) Split gate flash memory and manufacturing method thereof
TWI596774B (en) Semiconductor devices and methods of manufacturing the same
TWI249241B (en) Nonvolatile memory cell with multiple floating gates formed after the select gate
TWI289930B (en) Method for fabricating semiconductor devices
TWI284963B (en) Method of fabricating non-volatile memory
TW493212B (en) Semiconductor device and its manufacture method
TW201112315A (en) Direct contact in trench with three-mask shield gate process
CN105009286B (en) Non-volatile memory cells with enhanced channel region effective width, and method of making same
KR101923874B1 (en) Method for forming memory arrays and logic devices
TW201106397A (en) Capacitor structures, methods of manufacturing the same, semiconductor devices including the capacitor structures and methods of manufacturing the same
TW200842988A (en) Semiconductor device and method for manufacturing semiconductor device
JP2011049395A (en) Nonvolatile semiconductor memory device, and method of manufacturing nonvolatile semiconductor memory device
TWI288460B (en) Floating gate memory structures and fabrication methods
TW200832620A (en) Semiconductor device and method of manufacturing the same
TW200915568A (en) Semiconductor device and method of manufacturing the same
TWI360203B (en) Non-volatile memory and method of manufacturing th
TW529134B (en) Method of forming an NROM embedded with mixed-signal circuits
TWI338947B (en) Semiconductor device and method of fabricating the same
TW200812012A (en) Fabrication of semiconductor device exhibiting reduced dielectric loss in isolation trenches
TW200905807A (en) Memory and method for fabricating the same
TW200816391A (en) Method of manufacturing split gate flash device
TWI253747B (en) Nonvolatile semiconductor memory device
JP2010123721A (en) Semiconductor device
TWI269411B (en) Fabricating method of flash memory
TWI539520B (en) Memory device and methods of forming memory device and semiconductor device