TW201242033A - Semiconductor device and method of fabricating the same - Google Patents

Abstract

A semiconductor device is provided. The semiconductor device includes a first doped region of a first conductivity type, a second doped region of a second conductivity type, a gate and a dielectric layer. The first doped region having a trench therein is located in a substrate. The second doped region is located under the trench to separate the first doped region so as to form two source or drain doped regions separated each other. A channel region is located between the source doped region and the drain doped region. The gate is deposited in the trench. The dielectric layer covers a sidewall and a bottom of the trench to insulate the gate and the substrate.

Description

201242033 1. Description of the Invention: TECHNICAL FIELD OF THE INVENTION [0001] The present invention relates to semiconductor devices and methods of fabricating the same, and more particularly to non-volatile memory and methods of fabricating the same. [Prior Art] [0002] A non-volatile memory is, for example, a memory that can erase a programmable read-only memory (EEPROM) without causing the data stored therein to disappear due to a power supply interruption, which can be performed multiple times. The stylization, reading, erasing, etc. of the data are widely used in various personal computers and electronic devices.

L0003J

With the rapid development of the integrated circuit, the requirements of the component product (4) are getting higher and higher, and as the line width is reduced, the influence of the short channel effect will be more significant. In order to avoid the occurrence of short channel effects, it is necessary to reduce the depth and concentration of the source and drain doping regions, that is, the gap junction depth. However, in this case, the source and the immersion doped region are too high in resistance, resulting in a small read current of the memory device, which affects its performance. In addition, for 'logic elements', the source and the doping region resistance value is too high, which will detract from its driving current. [0004] The present invention provides several material elements that can avoid short channel effects and can be reduced Generation of Resistance of Source and Deuterium Doped Regions [0005] 100112123 The present invention provides a semiconductor device comprising a substrate, a first doped region, a second having a second conductivity type, and a dielectric layer. The first doped region having the first conductivity type has a trench therein. The first form number Α0101, page 3/75 has a first conductive doping region, and the open doping region is located at a second conductivity type in the substrate. Doping 1002020232-0 201242033, located at the bottom of the trench, separating the first doped region into two separated source or drain doped regions, between the source doped region and the drain doped region The gate region is located in the trench. The dielectric layer is located between the gate and the substrate of the trench. [0006] According to an embodiment of the invention, the source or drain doping region From the bottom of the above ditch Adjacent to the bottom corner, the sidewall extends to the surface of the substrate. [0007] According to an embodiment of the invention, the second doped region includes two first regions and a second region having different depths, wherein the distance from the second region The area of the second region at the bottom of the trench is larger than the area of the first region near the bottom of the trench, so that the source or drain doping region is stepped. [0008] According to an embodiment of the invention, the above The semiconductor device further includes a spacer between the dielectric layer on the sidewall of the trench and the substrate. [0009] According to an embodiment of the invention, the second doped region extends from the bottom of the trench to the trench Where the sidewalls are near the bottom corner, the source or drain doped regions are not covered by the bottom and bottom corners of the trench and extend from the sidewall of the trench to the surface of the substrate. [0010] In accordance with an embodiment of the present invention For example, the semiconductor device further includes a semiconductor layer completely covering and contacting the source or drain doped region. [0011] According to an embodiment of the invention, the The bulk layer includes a doped single crystal germanium layer, a doped poly germanium layer, a doped epitaxial germanium layer, a doped germanium germanium layer, or a combination thereof. 100112123 Form No. A0101 Page 4 of 75 1002020232-0 201242033 • 1 [0012] [0014] [0019] [0019] [0019] [0019]

According to an embodiment of the invention, the semiconductor device further includes a metal halide layer on the semiconductor layer. According to an embodiment of the invention, the semiconductor device further includes a hard mask layer on the semiconductor layer. According to an embodiment of the invention, the method further includes a hard mask layer on the source or drain doping region. According to an embodiment of the invention, the dielectric layer is further extended on the source or drain doping region. According to an embodiment of the invention, the gate further extends over the source or drain doping region. According to an embodiment of the invention, the semiconductor element is a MOS transistor, and the dielectric layer is a thyristor layer. According to an embodiment of the invention, the semiconductor component is a non-volatile memory cell, and the dielectric layer is a tunneling dielectric layer. According to an embodiment of the invention, the gate is a floating gate, and further includes a control gate and a gate dielectric layer. The control gate is located above the floating gate. The inter-gate dielectric layer is located between the floating gate and the control gate. According to an embodiment of the invention, the floating gate protrudes from the surface of the substrate. According to an embodiment of the invention, the floating gate, the inter-gate dielectric layer and the control gate extend above the source or drain doping region 〇100112123 Form No. 1010101 Page 5 / Total 75 Page 1002020232 [0021] 201242033 [0022] According to an embodiment of the invention, the surface of the floating gate is a flat surface or a surface having a groove. According to an embodiment of the invention, the semiconductor device further includes a charge storage dielectric layer between the tunneling dielectric layer and the gate. [0024] According to an embodiment of the invention, the charge storage dielectric layer extends over the source or drain doping region. According to an embodiment of the invention, the semiconductor device further includes a top dielectric layer between the charge storage dielectric layer and the gate. The present invention also provides a method of fabricating a semiconductor device, comprising: providing a substrate, forming a first doped region having a first conductivity type in the substrate, and then removing a portion of the first doped region to A trench is formed in the first doped region. A second doped region having a second conductivity type is formed at the bottom of the trench, and the first doped region is divided into two source or drain doped regions. A gate is formed in the trench, and a dielectric layer is formed between the gate and the substrate of the trench. According to an embodiment of the invention, the method for fabricating the semiconductor device further includes forming a spacer on a sidewall of the trench. According to an embodiment of the invention, the method for forming the second doped region includes performing a single ion implantation process with the spacer as a mask to separate the source or drain doping regions. From the surface of the substrate, along the side walls, extend to the bottom of the trench near the bottom corner. According to an embodiment of the invention, the method for forming the second doped region includes performing a first ion implantation process with the spacer as a mask and a 100112123 form number A0101, page 6 of 75 1002020232-0 201242033 [0030] [0033] [0033]

[0036] [0036] a second ion implantation process, wherein the energy of the second ion implantation process is higher than the energy of the first ion implantation process, so that the second ion implantation process forms a The area of the area away from the bottom of the trench is larger than the area of the area formed by the first ion implantation process close to the bottom of the trench. According to an embodiment of the invention, before the forming the second doping region and forming the dielectric layer, the spacer layer is further removed. According to an embodiment of the present invention, the method for forming the second doped region includes performing an ion implantation process using the trench as a mask to extend the second doped region from the bottom of the trench to the sidewall. According to an embodiment of the invention, the method of fabricating the semiconductor device further includes forming a semiconductor layer on the substrate before the trench is formed, and the semiconductor layer is in contact with the first doped region. According to an embodiment of the invention, the method of fabricating the semiconductor device further includes forming a hard mask layer on the semiconductor layer after forming the semiconductor layer and forming the trench. According to an embodiment of the invention, the method of fabricating the semiconductor device further includes removing the hard mask layer after forming the trench and before forming the dielectric layer. According to an embodiment of the invention, the method of fabricating the semiconductor device further includes removing the hard mask layer after forming the gate. According to an embodiment of the present invention, the method for manufacturing the above-mentioned semiconductor device 100112123, the form number Α0101, the seventh page, the total of 75 pages, the 2020, the 2020, the 2020, the 420 Metal layer. According to an embodiment of the invention, the method of fabricating the semiconductor device further includes forming a hard mask layer on the substrate before forming the trench. According to an embodiment of the invention, the method of fabricating the semiconductor device further includes removing the hard mask layer before forming the dielectric layer. According to an embodiment of the invention, the semiconductor component is a MOS transistor, and the dielectric layer is a thyristor layer. According to an embodiment of the invention, the semiconductor component is a non-volatile memory cell, and the dielectric layer is a tunneling dielectric layer. [0041] According to an embodiment of the invention, the gate is a floating gate, and the method further includes forming a control gate on the floating gate, and forming a gate between the floating gate and the control gate. Electrical layer. According to an embodiment of the invention, the method for fabricating the semiconductor device further includes forming a hard mask layer on the substrate before forming the trench, such that an upper surface of the gate in the trench is lower than The upper surface of the hard mask layer is exposed on the sidewall of the hard mask layer. A gate material layer is formed on the sidewall of the hard mask layer and the gate to form a floating gate having a grooved surface. A control gate is formed on the floating gate, and a dielectric layer between the gate is formed between the floating gate and the control gate. According to an embodiment of the invention, the floating gate, the inter-gate dielectric layer and the control gate extend over the source or drain doping region 100112123. Form No. A0101 Page 8 of 75 According to an embodiment of the invention, the method for fabricating the semiconductor device further includes forming a charge-dependent dielectric layer between the pass-through dielectric layer and the idle electrode. [0046] In accordance with embodiments of the invention, the charge dielectric layer extends further above the source or electrodeless doped regions. According to the invention, the method of fabricating the semiconductor device further includes forming a top dielectric layer between the charge storage dielectric layer and the gate. [0049] The half-element of the present invention can (4) avoid the generation of the filament and can reduce the resistance of the source and the drain doping region. In order to make the above features and advantages of the present invention more specific, the following embodiments are described in detail with reference to the accompanying drawings. [Embodiment] FIG. 1 is a view showing a prototype of a semiconductor element of the present invention. 100112123^ Referring to FIG. 1A, the semiconductor element prototype of the present invention includes a substrate 10 and has a first-doped region 14 of a first conductivity type, and a k = 22-W (a) hetero region u having a second conductivity type is located at a base; The cover has a ditch 32 in the #1 & The second doped region 22 is located at the bottom 32c of the trench 32. The first doped region 14 is separated to form a separate source source doped region l4am4b, and the source doped region is doped regions 14a and 14b. The "" is the channel region 34. The gate 30 is located in the trench 32 " the electrical layer 24 covers the sidewall 32a and the bottom 32c of the trench 32. The gate is separated from the substrate 1 and the substrate 1 〇. Form bat A0101 ί Page 5 of 1002002020232-0 201242033 [0054] [0054] In the present invention, the actual side-side gate is formed by the change of the position of the gate 3〇 in the vertical direction. The source doping region 14a and the electrodeless doping region 14b of the lifting effect. Since the source doping region-the portion of the gate doping region Ub under the gate 3〇 is relatively shallow, it may have a shallow junction The effect is as follows: since the source doped region 14a and the drain doped region (10) also extend upwardly around the sidewall of the gate 30, it has a raised source. The pole and the drain can reduce the resistance. The above semiconductor component can be a gold oxide semi-transistor non-volatile memory cell such as fast The memory cell or the nitrogen cut only reads the memory, etc. When the semiconductor component is a gold oxide semi-transistor, the dielectric layer 24 is a gate dielectric layer. When the semiconductor component is a non-volatile memory cell, the dielectric layer 24 is a tunneling dielectric. The gate 30 may be located only in the trench 32, or may extend upwardly and protrude from the surface of the substrate ί to extend over the substrate 1 。. When the above semiconductor component is a flash memory material, the above The gate 3〇 is floating idle. When the semiconductor component is a nitride-only read memory, the gate 30 is connected to the word line. The outline of each source or electrodeless doping region l4am4b may be The bottom portion 32c of the trench 32 extends along the side wall 32a near the bottom corner 32b to the surface of the substrate 1's. Alternatively, the source or drain doping regions 14& and 1413 may also be the bottom portion 32c of the uncovered trench 32 and The bottom corner 32b extends from the side wall 32a of the trench 32 to the surface of the substrate 10. The following embodiments are described, however, it is not intended to limit the invention. 100112123 Form No. A0101 Page 10 of 75 1002020232 -0 [0055] 201242033 ' . [0056] 2A to 2D-1 are flow cross-sectional views showing a method of manufacturing a tantalum nitride read-only memory according to a first embodiment of the present invention. [0057] Referring to FIG. 2A, a well region 12 is formed in the substrate 10 and A first doped region 14 is formed in the well region 12. The substrate 10 is, for example, a semiconductor substrate 10 as a whole, a semiconductor compound substrate 10 as a whole, or a semiconductor substrate I0 (semiconduc 1; or over insulator (SOI)). The semiconductor is, for example, an atom of Group IV A such as Shi Xi or Lu. In the case of Shi Xi, it can be a Shi Xi wafer or an epitaxial wafer. The semiconductor compound is, for example, a semiconductor compound formed of atoms of Group IVA, such as ruthenium carbide or ruthenium telluride. The substrate 10 may have a doping, and the doping of the substrate 10 may be a second conductivity type. The second conductivity type is, for example, a P type or an N type. The P-type doping may be a Group IIIA ion, such as a boron ion. The N-type doping may be a VA group ion such as arsenic or phosphorus. [0058] The well region 12 is implemented by a single ion implantation process or a multiple ion implantation process, and then subjected to a tempering process. The doping used to form the well region 12 is different from the conductivity type of the flash memory cell to be formed. When the conductivity type of the channel of the flash memory cell is the first conductivity type, the well region 12 is doped. The impurity is a second conductivity type ion. That is, the flash memory cell is a P-type channel, and the well region 12 is an N-type; the flash memory cell is an N-type channel, and the well region 12 is a P-type. In one embodiment, the well region 12 is P-type, the implanted ions are boron, and the energy of the ion implantation process is, for example, 50 to 500 K e V, and the dose is, for example, 1×10 12 to 3×l013/cm 2 . In one embodiment, the first doped region 14 is formed by the ion implantation process 36, after which the tempering process is performed. The doping used to form the first doping region 14 is, for example, a first conductivity type ion. First conductivity type 100112123 Form number A0101 Page 11 of 75 1002020232-0 201242033 Unlike the second conductivity type, for example, type or P type. The first doped region 14 can be formed by an ion implantation process. The number of times the ion implantation process 36 is performed and the concentration of the source or electrodeless doping regions 14a and 14b (Fig. 2C) and the junction depth «' which are to be formed may be single or multiple. In the present embodiment, the semiconductor layer 4G described in the following embodiments is not additionally formed on the substrate 1G to reduce the contact resistance. Therefore, multiple ion implantation processes can be used to form the layers having different depths and concentrations. - Doped region 14 In a practical example, the first doped region 14 is N-type and is formed by a single ion implantation process 36, such as arsenic implanted, and the energy of the ion implantation process is, for example, 15 to 4 〇 KeV, the dose is for example 1) <1〇15 to 4>< i〇15/cm2. In another embodiment, the first doped region 14 is of the ~-type and is formed by two ion implantation processes 36, both of which are, for example, arsenic. The energy of the first ion implantation process is, for example, 5i15KeV, and the dose is, for example, lxl〇15 to 4xl〇15/cm2. The energy of the second ion implantation process is, for example, 15 to 50 KeV, and the dose is, for example, 3 χΐ〇 14 to 2 χ lOis/cin ' such that the formed source or electrodeless doping regions 143 and 14|:) are close to the surface of the substrate 10 The doping concentration is higher than that of the trench 32, thereby simultaneously reducing the contact resistance and the effect of the shallow junction. [0061] Thereafter, a hard mask layer 16 is formed on the substrate 10 with reference to FIG. 2B'. The hard mask layer 16 can be a single material layer, a dual material layer, or a plurality of layers of material. The material of the hard mask layer 16 is, for example, bismuth fossil, nitriding; E eve, oxynitride or a combination thereof. The formation method of the hard mask layer 16 is, for example, physical vapor deposition (PVD) or chemical vapor deposition (CVD). The thickness of the hard mask layer 16 is, for example, 300 angstroms to 1 angstrom. A photoresist layer 38 having an opening 42 is then formed on the hard mask layer 16. Light 100112123 Form Number A0101 Page 12 of 75 1002020232-0 201242033 The resist layer 38 can be either positive or negative. The opening 42 of the photoresist layer 38 exposes the underlying hard mask layer 16. The width w1 of the opening 42 is slightly larger than the width w2 of the gate 30 (Fig. 2D-1) which is to be formed. In an embodiment, the width w1 of the opening 42 is, for example, 550 angstroms to 1,500 angstroms. [0062] Thereafter, referring to FIG. 2C, the photoresist layer 38 is used as a mask to remove the hard mask layer 16 exposed by the opening 42 and then remove a portion of the substrate 10 under the hard mask layer 16 to In the hard mask layer 16 and the first doping region 14 of the substrate 1 升, the trench 32 is formed, and then the photoresist layer 38 is removed. The method of removing the hard mask layer 16 and a portion of the substrate 1 下方 below it may be an etching process such as a dry etching process. The side wall 32a of the formed trench 32 may be a vertical surface, an inclined surface or a curved surface. The bottom corner 32b of the trench 32 may be a vertical angle, but is not limited to a vertical angle 'or a round corner' or a polygon (p〇iyg0nai c〇rner). The depth hi of the trench 32 located in the substrate 1 is, for example, 4 angstroms to 700 angstroms. [0063] Thereafter, the spacers 18 are formed in the side walls 32a of the trenches 32. The spacer 18 is formed by, for example, forming a layer of spacer material on the surface of the hard mask layer 16 and the trench 32, and then passing through an anisotropic etching process to remove a portion of the spacer material layer. The spacer 18 may be a single material layer, a double material layer or a plurality of layers of material. The material of the spacers 18 is, for example, ruthenium oxide, tantalum nitride, ruthenium oxynitride or a combination thereof. Then, at the bottom 32c of the trench 32, a second doped region is formed in the exposed substrate 1 () of the spacer 18, and the second doped region 22 extends downward from the first doped region 14 to the well region. The first doped region 14 is separated into two separate source or drain doped regions 14a and 14b. The wheel temple of the formed source or electrodeless doping regions Ua and Ub extends from the bottom portion 32c of the trench 32 to the bottom corner 32b, and extends along the sidewall 仏 to 100112123. Form No. A0101 Page 13 of 75 2020 2020232-0 201242033 The surface of the substrate 10. Between the source doped region 14a and the drain doped region i4b is a channel region 34. The width of the channel region 34 formed is related to the width of the spacer 18. When the width w3 of the spacer 18 is smaller/larger, the width W4 of the channel region 34 formed is larger/smaller. In one embodiment, the second doped region 22 can be formed by a hard mask layer 16 and a spacer 18 as a mask through the ion implantation process 20. The doping used to form the second doping region 22 is, for example, a second conductivity type ion ◊ second conductivity type, for example, a p-type or an N-type. In one embodiment, the first doped region 14 is N-type and the second doped region is 22!p-type. The ions implanted in the second doping region 22 are, for example, π, and the energy of the ion implantation process is, for example, 1 to 15 KeV, and the dose is, for example, 5 χ 1 〇ΐ 3 to 9 χ 1014 / cm 2 . [0065] Thereafter, please refer to FIG. 2D to remove the spacers 18. The method of removing the spacers may be an etching process such as a wet etching process or a dry process. Next, the hard mask layer 16 is removed. The method of removing the hard mask can be done by etching, for example, wet #刻 (4) is a dry etching process. Thereafter, tunneling dielectric layers 24, 28 are formed on the surface of the substrate and trench 32. The tunneling dielectric layer 24 may be formed of a charge storage dielectric layer 26 and a top dielectric layer. The single material layer is, for example, a low dielectric constant material or a high dielectric constant material. A low dielectric constant material refers to a dielectric material having a dielectric constant of less than 4, such as dioxo or gas oxidized oxide (Sl〇xNy), where χ and y are any possible values. The dielectric constant material refers to a dielectric material having a dielectric constant higher than 4, such as ΜΑΙΟHf〇2, Al2〇3 or . The wearable dielectric layer 24 can also be based on the energy gap engineering theory (band_gap call-call (10)) 100112123 Form number A0101 Page 4 / Total 75 pages 1002020232-0 201242033 〇α) Select readable high-note structure or multi-layer stack structure. Faster double-layer stacking material and high dielectric constant material: 4 structure is, for example, low dielectric constant constant material / high dielectric constant; double layer stacked structure (with low dielectric HfSi 〇, oxidation Shi Xi / _ or yttrium oxide - for example, oxidized stone / / structure, for example, low dielectric constant 矽. Multi-layer stacked Ο constant constant village material composed of multi-layer stack junction; (constant _ electric material and low dielectric Electro-constant material / low dielectric constant material sheet (dry 乂 ^ electric constant material / high fossil oxime / oxygen cut or oxidized stone eve / A1 〇 / oxygen, for example, oxygen cut / nitrogen layer 26 such as nitrite Or a 介ί〇2 = fossil eve ° charge-discharge dielectric layer. A single material layer such as β2 low-eight dielectric layer 28 is made of a single material: a number of materials. A low dielectric constant material is a high dielectric material. For example, it is a dioxotomy or a oxynitride. The dielectric material refers to a dielectric material that is the same as the dielectric constant material. The electrical constant material is a dielectric material of s• constant 4, such as coffee 0, Αί 〇ο 2 = Second: the electric layer 28 can also be based on the energy gap _ structure or multi-layer stack:: structure ==== discussion::::: constant material composed of double-layer structure: high: several electricity. Most materials indicate that 'for example, nitrite/oxidized stone: two structures such as a low dielectric constant material, a high dielectric constant material, and a multi-layer stacked structure composed of several materials (low dielectric β) Long electric constant material / low dielectric constant material), such as emulsified eve / dream / oxidized dream or oxidized nightmare oxidized stone eve. f material such as doped polysilicon, metal or doped poly 100112123 form number A0101 1002020232-0 Page 15 of 75 [0066] 201242033 Stacked structure formed of tantalum and metal. The gate 3 is formed by, for example, forming a material layer of gate 30 on the substrate 10 to cover the top dielectric layer. 28, sub-filling the trench 32. Then, the material layer of the idler 30 outside the trench 32 and above the top dielectric layer 28 is removed, and the removal method may be an etching process or a chemical mechanical polishing process (CMP). [0068] In the above embodiment of the present invention, the tempering process of the source doping region 14a and the drain doping region 14b (the first doping region 14) is in the tunneling dielectric layer 24 and the gate 30 is formed before formation, thus ensuring tunneling dielectric layer (especially the tunneling dielectric layer of the dielectric constant material) and the stability of the material such as the gate 3 (especially the metal gate) are not affected by the source doping region 14a and the drain doping region 14b (the The effect of the tempering process of a doped region η). The tantalum nitride read-only memory shown in FIG. 2D-1 includes a substrate 1 , a well region 12 , a first doped region 14 having a first conductivity type, and a second doped region 22 of the second conductivity type, a gate 30, a tunneling dielectric layer 24, a charge storage dielectric layer 26, and a top dielectric layer 28. The well region 12 and the first doped region 丨4 are located on the substrate 1 In the crucible, the first doped region 14 has a trench 32 therein. The second doped region 22 is located at the bottom 32c of the trench 32 such that the first doped region 14 is separated to form separate source or drain doped regions 14a and 14b. Between the source doped region 14a and the electrodeless doped region 14b is a channel region 34. The gate 3 is buried in the trench 32 of the substrate 1 and has a thickness t1 which is substantially equivalent to the depth hl of the trench 32 in the substrate. The thickness t1 of the gate 30 is, for example, about 400 to 7 angstroms. The side wall 32a of the gate 3〇 may be a vertical surface, an inclined surface or a curved surface. The bottom corner 32b of the gate 3〇 may be a vertical angle, but is not limited to a vertical angle, and may be a rounded corner or a multi-angle (p〇iyg0nai corner). The tunneling dielectric layer 24, the charge storage dielectric layer 26, and the top dielectric layer 28 cover 100112123. Form No. A0101 Page 16 of 75 1002020232-0 201242033 The sidewall 32a and the bottom 32c of the trench 32 are separated from each other. 3〇 and the substrate ίο' and extend over and in direct contact with the source doping region 14a and the drain doping region 14b. [0069] The present invention allows the source doping region 14a and the gate doping region i4b not only to be located below the gate 30 but also to embed the gate 30 in the trench 32 of the substrate 1' The cover is wrapped around the side wall 32a of the gate 3〇. Since the portion of the source doping region 14a and the drain doping region 141} under the gate electrode 3 is relatively shallow 'hence', it is possible to have a shallow junction effect for the purpose of avoiding the short channel effect. On the other hand, since the source doping region 14a and the gate doping region 14b also extend around the sidewall 32a of the gate 3A, it has the advantage that the raised source and the drain can lower the resistance. It is worth mentioning that 'the embodiment of the invention embeds the gate 3〇 in the substrate 1' and the source doped region 14& and the drain doped region i4b are also fabricated in the substrate 10, through the gate The change of the position of the pole 3 in the vertical direction is performed to produce the source doped region 14a and the drain doped region 14b having the lift effect, and the gate 30 is not directly formed on the surface of the substrate 10, and is additionally formed. The epitaxial layer is formed to raise the source and the drain. Therefore, the source doping region 14a and the drain doping region 14b of the present invention having the lifting effect are completely doped by the substrate 10 and are located under the gate 30. The portion and the portion wrapped around the gate 3〇 are of the same material and there is no interface between the two portions. [0070] FIG. 2D is a cross-sectional view of a nitride-free read memory of the second embodiment. . 100112123 Referring to FIG. 2D and FIG. 2, after the fabrication of the tantalum nitride read-only memory corresponding to the manufacturing method of FIG. 2A to FIG. 2 is completed, the spacer form number A0101 is also removed. Page 17 of 75 pages 1002020232 -0 [0071] 201242033 18. Next, however, the hard mask layer 16 is not removed, but the tunneling dielectric layer 24, the charge storage dielectric layer 26, and the top dielectric are formed directly on the hard mask layer 16. Layer 28. Thereafter, in accordance with the above method, a gate 30 connecting the word lines is formed in the remaining space of the trench 32. [0072] The structure of the tantalum nitride read-only memory shown in FIG. 2D-2 and FIG. 2D-1 The nitrided germanium read only memory is similar, but the tunnel dielectric layer 24, the charge storage dielectric layer 26, and the top dielectric layer 28 cover the sidewalls 32a and 32c of the trench 32, separating the gate 30 from the substrate. 10, and extending to the hard mask layer 16 above the source doping region 14a and the drain doping region 14b. The gate 30 is located in the trench 32 of the substrate 10 and the hard mask layer 16, if the hard mask The thickness of the tunneling dielectric layer 24, the charge storage dielectric layer 26, and the top dielectric layer 28 on the layer 16 is the same as the bottom 32c of the trench 32. The thickness of the tunnel dielectric layer 24, the charge storage dielectric layer 26, and the top dielectric layer 28 are comparable, and the thickness of the gate 30 is substantially equivalent to the depth hl+h2 of the trench 32 in the substrate 10 and the hard mask layer 16. 2D-1 and 2D-2, the depth 32 of the trench 32 in the substrate 10 is the same, since the trench 32 of the tantalum nitride read-only memory shown in FIG. 2D-2 also extends upward to the hard mask layer 16, The depth is hl+h2, which is larger than the depth of the trench 32 in FIG. 2D-1. Therefore, the thickness t2 of the gate 30 of the tantalum nitride read-only memory shown by 2D-2 is greater than that of FIG. 2D-1. The thickness of the gate 30 of the silicon nitride read-only memory is t1. In other words, if the thickness t2 of the gate 30 in Fig. 2D-2 is equivalent to the thickness t1 of the gate 30 in Fig. 2D-1, it is located in Fig. 2D-2. The depth of the trench 32 of the substrate 10 can be made shallower than the depth of the trench 32 of the substrate 10 in Fig. 2D-1. [0073] FIG. 2D-3 illustrates a tantalum nitride read-only memory of the third embodiment. Sectional view: 100112123 Form No. A0101 Page 18 of 75 1002020232-0 201242033 '[0074] Please refer to FIG. 2D-3, in accordance with the above-mentioned manufacturing method corresponding to FIG. 2A to FIG. 2C. After the morphological read-only memory is fabricated, the spacers 18 are also removed, and the hard mask layer 16 is not removed, but is formed directly on the hard mask layer 16 and on the surfaces of the sidewalls 32a and 32c of the trench 32. Tunneling dielectric layer '24, charge storage dielectric layer 26 and top dielectric layer 28. Thereafter, a tunneling dielectric layer 24 is also formed on the hard mask layer 16 and on the surfaces of the sidewalls 32a and 32c of the trench 32, The charge storage dielectric layer 26 and the top dielectric layer 28, and the gates 30 connecting the word lines are formed in the remaining space of the trenches 32. However, the tunneling dielectric Q layer 24, the charge storage dielectric layer 26, and the top dielectric layer 28 on the hard mask layer 16 are removed prior to forming the gate 30, such as a hard mask. The curtain layer 16 is an etch stop layer, which is achieved by an etching process or a chemical mechanical polishing process. [0075] The structure of the tantalum nitride read-only memory shown in FIG. 2D-3 is similar to that of the tantalum nitride read-only memory shown in FIG. 2D-2, but the tunnel dielectric layer 24 and the charge storage dielectric layer 26 are formed. And the top dielectric layer 28 covers only the sidewalls 32a and 32b of the trench 32, separating the gate 30 from the substrate 10, and does not extend to the source doped region 14& and the hard mask over the drain doped region 14b. On the layer 16, therefore, the surface of the hard mask layer 16 of this structure will be exposed. The thickness t3 of the gate 30 is approximately the thickness hl+h2 of the trench 32 in the substrate 10 and the hard mask layer 16 minus the thickness of the tunneling dielectric layer 24, the charge storage dielectric layer 26, and the top dielectric layer 28. In other words, if the thickness t3 of the gate 30 in FIG. 2D-3 is equivalent to the thickness t1 of the gate 30 in FIG. 2D-1, the depth hi of the trench 32 in the substrate 10 in FIG. 2D-3 can be made slightly shallower than that in FIG. 2D. The depth of the trench 32 in the substrate 10 is -hi. 3A to 3D-1 are diagrams showing a nitridation according to a fourth embodiment of the present invention. 100112123 Form No. A0101 Page 19/75. 1002020232-0 201242033: Flow profile of a manufacturing method of read-only memory The fifth embodiment of the present invention - the nitrogen cut only read memory ~ 2 draws the 3D '3 green shows the sixth embodiment of the present invention. i side view. Figure Sectional view.矽 read-only memory [0077] = according to Figures 3A to 3D], according to the above figure (4) 蜕 蜕 矽 read-only memory, but the internal method is formed in the well zone 12 to form the first pine _ 〇 形成After the first doped region 14 is formed in the well region 12 and U, the semiconductor layer 40 is formed on the substrate 10 before the immersion. The mask layer 16 is patterned during the continuation of the trench 32, and the semiconductor layer 40 is removed as the source layer 4 is doped, as doping in the patterned semiconductor (10). Semiconductor (four);; ^ contact area. The region Ha and the immersed doped region (4) have the same conductivity. The doping concentration of the ruins of the ruins is greater than or close to the source. The semiconductor layer can be called (10) (10); the doping region reduces the contact resistance. The semiconductor germanium layer is doped with a polycrystalline germanium layer, doped with a doped early or germanium layer, and doped with a (tetra) germanium layer. +¥Doping in the bulk layer 4〇 can be ln-situdoped during deposition, or after the semiconductor deposition is performed by the ion implantation process, the source doping region 14a and The doping in the electrodeless doping region 14b is an N-type semiconductor layer core, which can be doped with N-type ions, and the N-type ions can be mixed with n-type ions. An ionic phosphatite layer, or a sputum of a N-type ion or a combination thereof. In another embodiment, the doping in the source doping region 14a and the drain doping region 14b is p-type, and the semiconductor layer 4〇 may be a doped single crystal germanium layer with field doped P-type ions.矽 梨 梨 梨 锗 锗 112 112 112 112 112 112 112 112 112 112 112 112 112 112 112 112 112 112 112 112 112 112 112 112 112 112 112 112 112 112 112 112 112 112 112 112 112 112 112 112 112 112 112 112 112 112 112 112 112 112 112 112 112 112 112 112 112 112 100112123 The polycrystalline germanium or a combination thereof is related to the depth hl of the thick mMAn collection channel 32 of the substrate temperature property layer 40. Also #θ The existence of the body layer 4〇 can be self-contained and the semi-conducting Μ is reduced. In - true ^. The depth hl of the second ^ _ 32 is, for example, about paste to 5 _,; the depth of _ 嶋 32 is about 3 〇〇 to 5 〇〇, and the thickness of θ 40 is, for example, Γ. . . ^ but not limited thereto. The camper adjusts the source and the doped region of the trench formed in the substrate 10 according to the depth at which the material can be transferred, and the semiconductor layer 4G can be regarded as the rising doping region 14a and The source doped region (10) located below the trench 32 can be made shallower junctions. , moxibustion, in accordance with the above-mentioned nitrogen-cut only read memory (four). The processing method of Bu 1 is completed by V. The read-only memory includes the substrate 1 (), the well region 12 has the first conductivity type - the doping region 14 M2' is doped with F99 Ba, has the first The conductivity type: '——the gate 30, the dielectric layer 24, the charge storage M and the top dielectric layer 28, and the semiconductor layer 4G. The first _# miscellaneous ^ 14 is located in the base illusion. In the middle of the semiconductor layer 4 and the first impurity-changing region, there is a trench 32. The trench 32 has a depth h3 at the semiconductor layer 4, and the trench 3/the depth of the first doped region 14 is separated from the second doped region 22 at the trench 32 such as the portion 32c', and the first doped region 14 is separated to form a separate trench. Two source or electrodeless doped regions 14a and i4b. Between the source doped region 14a and the drain doped region Ub is a channel region 34. The source doped region 14a and the drain doped region 14b extend from the bottom portion 32c of the trench 32 along the bottom corner 32b to the sidewall 32a of the trench 32 to be wrapped around the sidewall of the gate 3. The semiconductor layer 4 is located on the source doping region 14a and the non-polar doping region 14b, and is wrapped around the sidewall of the gate 3A. Form No. A0101 Page 21 of 75 1002020232-0 201242033. In other words, the gate 30 is located in the trench 32 of the semiconductor layer 40 and the substrate ι. The thickness of the gate 30 is substantially equivalent to the depth hl+h3 of the substrate 1〇 and the trench 32 in the semiconductor layer 4〇 (if the thickness of the tunneling dielectric layer 24, the charge storage dielectric layer 26, and the top dielectric layer 28 is negligible) The tunneling dielectric layer 24, the charge storage dielectric layer 26, and the top dielectric layer 28 cover the sidewalls 32a and 32c of the trench 32, separating the gate 30 from the substrate 1 and extending to the source doping The region 143 is on and in direct contact with the semiconductor layer 40 above the drain doped region 14b. If the depth of the trench 32 in the substrate 1A of FIG. 3D-1 and FIG. 2D-1 is the same as the depth hi, the trench 32 of the nitride-only read memory shown in FIG. 3D-1 also extends upward to the semiconductor layer 4? The depth is hl+h3. Therefore, the thickness of the gate 3〇 of the tantalum nitride read-only memory shown by 3D-1 is greater than the thickness of the gate 30 of the tantalum nitride read-only memory shown in FIG. 2D-1. [_] Similarly, FIGS. 3D-2 and 3D-3 are similar to FIG. 2D-2 and FIG. 2D-3 respectively, the difference is also that the well region 12 is formed in the substrate 10 and the first blend is formed in the well region 12. After the impurity region 14 is formed, a semiconductor layer 40 is formed on the substrate 10 as a source-drain contact region before the hard mask layer 16 is formed. [ΟΟδΙ] Figs. 4A to 4D-1 are cross-sectional views showing the flow of a method for manufacturing a nitride-reading memory according to a seventh embodiment of the present invention. 4D-2 is a cross-sectional view showing a tantalum nitride read only memory according to an eighth embodiment of the present invention. 4D-3 is a cross-sectional view showing a tantalum nitride read only memory according to a ninth embodiment of the present invention. 5A to 5D-1 are cross-sectional views showing the flow of a method for fabricating a tantalum nitride read-only memory according to a tenth embodiment of the present invention. Fig. 5D-2 is a cross-sectional view showing a tantalum nitride read only memory according to an eleventh embodiment of the present invention. Figure 5D-3 is a cross-sectional view showing a tantalum nitride read only memory according to a twelfth embodiment of the present invention. 100112123 Form No. 101 0101 Page 22 / Total 75 Pages 10020202324 201242033 [0082] FIGS. 4A to 4D-1 and FIGS. 4D-2, 4D-u, and a manufacturing method of the mouse-only read-only memory of FIG. The manufacturing method of the fossilized fossil memory of the heart and the m3 is similar, and the manufacturing method of the nitrided read-only memory of FIG. 5D_2 and 5D-3 respectively and the above-mentioned FIG. 3A to 3D-1 and FIG. 3D- 2. The manufacturing method of the nitrided germanium read-only memory of 3D-3 is similar. However, referring to Figures 4C, 5C, and 6C, after the trench 32 is formed in the hard mask layer 16 and the substrate 10, the spacers 18 are not formed in the side walls 32a of the trench 32 (Figs. 2C and 3C). The second doping region 22 is directly coated with a hard mask layer 16 (with no spacers 18) as an mask for performing an ion implantation process, such as a vertical ion implantation process, but under the trench 32. The first doped region 14 extends downwardly into the well region 12 and extends laterally to the bottom corner 32b of the trench 32 and extends upwardly to the lower sidewall 32a of the trench 32. The second doped region 22 extends from the first doped region 14 into the well region 12, separating the first doped region 14 into separate source or electrodeless doped regions 14a and 14b. The second doped region 22 extends from the bottom portion 32c of the trench 32 along the bottom corner 32b of the trench 32 to the lower portion of the sidewall 32a of the trench 32, so that the formed source or drain doped regions 14a and 14b are not covered with trenches. The bottom portion 32c of the 32 and the bottom corner 32b'' extend from the upper portion of the side wall 32a of the trench 32 to the surface of the substrate 10. In other words, the channel region 34 between the source doped region 14a and the drain doped region 14b extends not only at the bottom 32c of the trench 32 but also along the bottom corner 32b of the trench 32 to the lower portion of the sidewall 32a of the trench 32, such that the channel The length of 34 becomes larger. In addition, since the source or drain doping regions 14a and 14b do not cover the bottom portion 32c and the bottom corner 32b of the trench 32, a high electric field is present at the exposed bottom corner 32b when the device is operated. The injection efficiency of the carrier. 100112123 Form No. A0101 Page 23 of 75 1002020232-0 201242033 [0083] After forming the source or drain doped regions 14a and 14b, according to Figures 2D-1, 2D-2, 2D_3, 3D-1, The method of 3D-2 and 3D_3 completes the manufacture of the gasification stone read-only memory, and the formed silicon nitride read-only memory is as shown in Figs. 4D-1, 4D-2, 4D-3, 5D-1, 5D-2, 5D-3 households show. In the above embodiment, referring to FIGS. 4C and 5C, the second doping region 22 is formed after the trench 32 is formed, after the tunneling dielectric layer 24 is formed, and is formed by an ion implantation process. However, the invention is not limited thereto. In one implementation, the second doped region 22 may also be formed by the ion implantation process 20 after the formation of the tunneling dielectric layer 24 prior to formation of the charge storage dielectric layer 26. Second doped region 22. In another implementation, the second doped region 22 can also be formed through the ion implantation process 20 after the formation of the tunnel dielectric layer 24 and the charge storage dielectric layer 26 prior to formation of the top dielectric layer 28. In still another implementation, the second doping region 22 may also be formed after the tunneling dielectric layer 24, the charge storage dielectric layer 26, and the top dielectric layer 28 are formed, before the gate layer 30 is formed. Process 20 is formed. 6A to 6F are cross-sectional views showing the flow of a method of manufacturing a flash memory cell according to a thirteenth embodiment of the present invention. 6A and 6B, in accordance with the above-described manufacturing method corresponding to FIGS. 3A to 3C, the well region 12, the first doping region 14, the semiconductor layer 40, the hard mask layer 16, the trench 32, and the spacer 18 are formed. And using the spacer 18 and the hard mask layer 16 as a mask, a second doping region 22 is formed under the trench 32, and the first doping region 14 is divided into two separated source or drain doping regions 14a. With 14b. [0087] Next, referring to FIG. 6C, the spacers 18 are also removed in accordance with the above method. Thereafter, on the hard mask layer 16 and the side walls 32a and the bottom portion 32c of the trench 32, and the bottom portion 32c 100112123, the form number A0101, page 24/75, 1002020232-0 201242033 [0088] [0090] Electrical layer 24. Then, a floating gate material layer 30a' is formed on the substrate 10, and a floating gate material layer 3a is overlaid on the hard mask layer 16, and is filled in the trench 32. The material of the floating gate material layer 3〇a is, for example, a doped polycrystalline stone. Then, referring to FIG. 6D, the floating gate material layer 3a, the tunneling dielectric layer 24, and the hard mask layer 16 above the semiconductor layer 4〇 are removed, and the method of removing may be performed by using a surname process or a chemical process. The mechanical polishing process (CMp) is performed until the semiconductor layer 40 is exposed. The floating gate material layer 3〇a remaining in the semiconductor layer 4 and the trenches of the substrate 1 is used as a floating gate of the flash memory cell. The surface of the floating gate 30 is substantially flush with the surface of the semiconductor layer 40. Thereafter, referring to FIG. 6E, the inter-gate dielectric layer 48 and the control gate material layer 5A are sequentially formed on the substrate 1. The inter-gate electrical layer 48 may be a high dielectric constant single material layer, a single material layer. The material such as the HfG2i dielectric layer 48 may also use a two-layer stacked structure or a multi-layer stacked structure to increase the gate breakdown voltage (gate c〇up_lmg = tl.) to improve stylization and erase efficiency. The growth structure is, for example, a high dielectric constant material and a low dielectric constant material, and a high dielectric constant material/low dielectric constant material is represented by a high dielectric constant material. Dielectric constant material stack structure (represented by multi-layer material composed of low dielectric constant material), for example = Saki constant material / low dielectric constant / Al2 〇 3 / oxygen cut. Control 2 / 虱: _ Oxygen cut or oxidized stone Xijing dream. The material of 50a is, for example, doped more than 100112123 Form No. A0I01 25th/total 75 pages 1002020232-0 201242033 [0091] Thereafter, referring to FIG. 6F, the gate material layer 50a and the inter-gate dielectric layer 48 are patterned. The patterned gate material layer 50a is used as a flash memory cell. The control gate 50. Thereafter, an insulating layer 52 is formed around the control gate 50 and the inter-gate dielectric layer 48. The insulating layer 52 is formed by, for example, forming an insulating material layer (not shown) on the substrate 10 to cover the semiconductor layer. 40 and the control gate 50, after which the planarization process is performed to remove the insulating material layer on the control gate 50. The planarization process is, for example, a chemical mechanical polishing process (CMP). [0092] The flash memory cell shown in FIG. 6F A substrate 10, a semiconductor layer 40, a well region 12, a first doped region 14 having a first conductivity type, a second doped region 22 having a second conductivity type, a floating gate 30, and a tunneling dielectric layer 24 are included. The inter-gate dielectric layer 48 and the control gate 50. The semiconductor layer 40 is located on the substrate 10. The well region 12 and the first doping region 14 are located in the substrate 10. The semiconductor layer 40 and the first doping region 14 of the substrate 10 have Ditch 32. The second doping region 22 is located at the bottom 32c of the trench 32 to make the first doping 14 is separated to form separate source or drain doped regions 14a and 14b, and between the source doped region 14a and the doped region 14b is a channel region 34. The floating gate 30 is located on the semiconductor layer 40 and The trench 32 of the substrate 10 has a substantially flat surface and is substantially flush with the surface of the semiconductor layer 40. The tunneling dielectric layer 24 covers the sidewalls 32a and 32c of the trench 32, separating the floating gate 30 from the substrate. 10. The control gate 50 is located on the floating gate 30 and a portion of the semiconductor layer 40 therearound. The inter-gate dielectric layer 48 is located between the control gate 50 and the floating gate 30 and between the control gate 50 and the semiconductor layer 40. 7A to 7F are cross-sectional views showing the flow of a method of manufacturing a flash memory cell according to a fourteenth embodiment of the present invention. 7A to 7F are similar to FIGS. 6A to 6F, but 100112123 Form No. A0101 Page 26 of 75 pages 1002020232-0 201242033 ', please refer to FIG. 7D, formed in the trench 32 After the floating gate material layer 30a is followed by an etch back process, a portion of the floating gate material layer 30a is removed to expose the tunnel dielectric layer 24, and then the tunnel dielectric layer 24 is over the hard mask layer 16. Remove. Then, using a etching solution or etching gas having a lower removal rate than the hard mask layer 16 for the floating gate material layer 30a, a portion of the floating gate material layer 30a and a portion of the hard mask layer 16 are removed, leaving the remaining The surface of the floating gate material layer 30a protrudes from the surface of the hard mask layer 16 as a floating gate 30. In one embodiment, the material of the hard mask layer 16 is the same as that of the tunneling dielectric layer 24. The etchback process described above requires only one etching process to use the removal rate of the floating gate material layer 30a. It may be carried out below the etching solution or etching gas of the hard mask layer 16. 7E and 7F, in accordance with the above-described methods of FIGS. 6E and 6F, the inter-gate dielectric layer 48 and the control gate material layer 50a are sequentially formed on the substrate 10 and patterned. The patterned control gate material layer 5 0 a acts as a control gate for the flash memory cell 5 0 . Thereafter, an insulating layer 52 is formed around the control gate 50 and the inter-gate dielectric layer 48. [0096] In this embodiment, the floating gate and the control gate are added by the surface of the floating gate protruding from the surface of the hard mask layer. The coupling area between them to increase the coupling ratio of the components. 8A to 8F are cross-sectional views showing the flow of a method of manufacturing a flash memory cell according to a fifteenth embodiment of the present invention. The manufacturing method of the flash memory cell of FIGS. 8A to 8F is similar to that of FIGS. 6A to 6F. However, referring to FIG. 8D, after the floating gate material layer 30a is formed in the trench 32, the etchback process is performed to remove the portion. The floating gate material layer 30a exposes the via layer 100112123 Form No. A0101 page 27/75 page 1002020232-0 201242033, and then removes the tunneling dielectric layer 24. Then, using the etching solution or etching gas for the floating gate material layer 30a to be removed at a higher rate than the hard mask layer 16, the portion of the floating gate material layer 30a is removed, leaving the remaining floating gate material layer 30 a The surface is lower than the surface of the hard mask layer 16. In one embodiment, the material of the hard mask layer 16 is the same as that of the tunneling dielectric layer 24. The above-mentioned etching process only needs to pass through a #etch process, and the floating gate material layer 30a is selected to have a high removal rate. The etching solution or etching gas of the hard mask layer 16 may be performed. 8E and 8F, another layer of floating gate material layer 30b is formed on the substrate 10 to cover the hard mask before the inter-gate dielectric layer 48 is formed on the substrate 10 according to the method of FIG. 6E. The curtain layer 16 covers the layer of floating material 30a remaining in the trench 32. The floating gate material layer 30b does not fill the trench 32 and has a groove surface 54 in the trench 32. Thereafter, the inter-gate dielectric layer 48 and the gate material layer 50a are sequentially formed on the substrate 10 in accordance with the above-described methods of Figs. 6E and 6F, and patterned. The patterned floating gate material layer 30a and the floating gate material layer 30b are used as the floating gates 30. [0100] In this embodiment, the floating gate 30 having the groove surface 54 is formed by the double-layer floating gate material layers 30a and 30b, thereby increasing the area of the floating gate 30 and the control gate 50. Improve the engagement rate of components. 9A to 9F are cross-sectional views showing the flow of a method of manufacturing a flash memory cell according to a sixteenth embodiment of the present invention. 10A through 10F are cross-sectional views showing the flow of a method of manufacturing a flash memory cell according to a seventeenth embodiment of the present invention. 11A to 11F are cross-sectional views showing the flow of a method of manufacturing a flash memory cell according to an eighteenth embodiment of the present invention. 100112123 Form No. A0101 Page 28 of 75 1002020232-0 201242033 ''[0102] ❹ The manufacturing method of the flash memory cells of FIGS. 9A to 9F is similar to that of FIGS. 6A to 6F; FIG. 10 to 10F of the flash memory cell The manufacturing method is similar to that of FIGS. 7A to 7F; the manufacturing method of the flash memory cells of FIGS. 11A to 11F is similar to FIGS. 8A to 8F, but please refer to FIGS. 9A, 10B, and 11B to form in the hard mask layer 16 and the substrate 10. After the trench 32, the spacers 18 are not formed in the side walls 32a of the trenches 32 (Figs. 6B, 7B, 8B). The second doped region 22 is directly covered by the hard mask layer 16 (with no spacers 18) as an mask, and is subjected to an ion implantation process 20, such as a vertical ion implantation process, and formed under the trench 32. A doped region 14 extends downwardly into the well region 12 and extends laterally to the bottom corner 32b of the trench 32 and extends upwardly to the lower sidewall 32a of the trench 32. The second doped region 22 extends from the first doped region 14 into the well region 12, separating the first doped region 14 into separate source or drain doped regions 14a and 14b. The second doped region 22 extends from the bottom portion 32c of the trench 32 along the bottom corner 32b of the trench 32 to the lower sidewall 32a of the trench 32, so that the formed source or drain doped regions 14a and 14b are not covered with trenches. The bottom portion 32c of the 32 and the bottom corner 32b extend from the upper side wall 32a of the trench 32 to the surface of the substrate 10. 12A to 12F are cross-sectional views showing the steps of a method of fabricating a MOS field effect transistor according to an eighteenth embodiment of the present invention. After forming the well region 12, the first doping region 14, the semiconductor layer 40, the hard mask layer 16, and the trench 32 in accordance with the above-described manufacturing method corresponding to Figs. 3A to 3C, the spacer material layer 44 is formed first. Then, using the spacer material layer 44 and the hard mask layer 16 as a mask, a second doping region 22 is formed under the trench 32 to separate the first doping region 14 into two separated source or drain electrodes. Zones 14a and 14b. However, in this embodiment, the second doping region 22 includes two first regions 22a and second regions 100112123 having the same conductivity type but different depths. Form No. A0101 Page 29/75 pages 1002020232-0 201242033 =b . The area near the bottom 32c of the trench 32 is the first area "a", the area away from the bottom 32c of the trench 32 is thinner than the second area, and the area of the second area 22b is larger than the area of the first area 22a, so that the source or the pole is The wheel grinding of the ramming zone Uam4b is stepped. The forming method of the first region 22a and the second region 22b of the second doping region 22 can be formed by the ion implantation process through the ion implantation process. The ion implantation process of the first product or the ion implantation process 2Qa has a lower implantation energy, and the ion implantation process of the second region 22b has a higher ion implantation energy. In the implementation J, the first doping region 14 is N-type. The second doped region is of a 卩 type. The ions implanted in the first region 22a of the second impurity region 22 are, for example, 1Kev, and the dose is, for example, fine.

1〇14: Hey. The sub-implant energy is, for example, a dose, for example, 3X

[0106] 100112123 θ ^ , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Next, the material of the substrate ～~::, is, for example, a towel of the oxygen-Xi's nitrogen channel 32 (4) material layer or a combination thereof. Next, for example, the doped polysilicon (4) is a material of the metal or the (4) layer 3〇a. Thereafter, referring to Fig. 12E, the gate 30a and the gate dielectric layer 24 are removed. The gate material on the mask layer 16 is wide. Removing the free layer on the hard mask layer: the pole material layer 3〇a is used as the interpole 30 method, for example, by the hard mask layer 16 as the gate dielectric layer 24 or the briber process. 2,,, cut, chemical mechanical polishing semiconductor layer 40 exposed to ^ hard ^ hard mask layer 16 removed, so that the form of the bat surface of the core mask layer 16 can be used page 30 / a total of 75 pages 201242033 It is a dry engraving process or a wet money engraving process. [0107] Thereafter, referring to FIG. 12F, the self-aligned layer 40 and the surface of the curry are formed with gold metal. The material of the semiconductor material is, for example, refractory metal 6 ° metal deuterium, cobalt, titanium, copper, indium, Crane: The second fire metal is, for example, an alloy.钇, platinum or these metals [0108] riding gates buried in the meixi Ο == and - also made in the vertical direction of the base two transmission gates to create a source-doped region with a lifting effect soul. Since the portion below the __ location 相当 is relatively shallow, it can have the effect of a shallow junction to achieve the purpose of avoiding the short channel effect. On the other hand, since the source doping region and the drain doping region are also extended around the sidewall of the gate, it has the advantage of having a raised wire and a low resistance value (10) in the source doping region. Further, a semiconductor layer which is still in a mixed concentration can be formed with the electrodeless doping region to further reduce the contact resistance. [0109] In the other embodiments of the present invention, the first doped region for separating the source or the immersed doping region may extend from the bottom of the trench along the bottom corner of the trench to the m of the trench. The source or drain doping region does not cover the bottom and the bottom corner of the trench, and not only can extend the length of the channel, but also can provide carrier injection because the exposed bottom corner has a high electric field when the device is operated. effectiveness. In addition, the above-mentioned silk scarf of the present invention, the __ region and the drain region (the tempering process of the first doping region is in the dielectric layer (tunnel dielectric layer) and 100112123

Form No. A010I Page 31 of 75 1002020232-0 [0110] 201242033 The gate is formed before the formation of the gate, thus ensuring the stability of the dielectric layer (via dielectric layer) and the gate and other materials without being affected by the source The effect of the tempering process of the pole doped region and the drain doped region (first doped region). The present invention has been disclosed in the above embodiments, and is not intended to limit the present invention. Any one of ordinary skill in the art can make a few changes without departing from the spirit and scope of the invention. The scope of protection of the present invention is defined by the scope of the appended patent application. BRIEF DESCRIPTION OF THE DRAWINGS [0112] FIG. 1 is a view showing a prototype of a semiconductor element of the present invention. 2A to 2D-1 are cross-sectional views showing a process of manufacturing a tantalum nitride read-only memory according to a first embodiment of the present invention. 2D-2 is a cross-sectional view showing a tantalum nitride read-only memory of the second embodiment. 2D-3 is a cross-sectional view showing a tantalum nitride read-only memory of the third embodiment. 3A to 3D-1 are cross-sectional views showing a process of manufacturing a tantalum nitride read-only memory according to a fourth embodiment of the present invention. 3D-2 is a cross-sectional view showing a tantalum nitride read-only memory according to a fifth embodiment of the present invention. 3 is a cross-sectional view showing a tantalum nitride read only memory according to a sixth embodiment of the present invention. 4A to 4D-1 illustrate a nitriding 100112123 according to a seventh embodiment of the present invention. Form No. A0101 Page 32 of 75 1002020232-0 201242033 [0120] [0121] [0123] [0123] ] Ο [0124] [0126] [0126]

[0130] [0130] A cross-sectional view of a process for manufacturing a read-only memory. 4D-2 is a cross-sectional view showing a tantalum nitride read only memory according to an eighth embodiment of the present invention. 4D-3 is a cross-sectional view showing a tantalum nitride read only memory according to a ninth embodiment of the present invention. 5A to 5D-1 are cross-sectional views showing a process of manufacturing a tantalum nitride read-only memory according to a tenth embodiment of the present invention. Fig. 5D-2 is a cross-sectional view showing a tantalum nitride read only memory according to an eleventh embodiment of the present invention. Figure 5D-3 is a cross-sectional view showing a tantalum nitride read only memory in accordance with a twelfth embodiment of the present invention. 6A to 6F are cross-sectional views showing the flow of a method of manufacturing a flash memory cell according to a thirteenth embodiment of the present invention. 7A to 7F are cross-sectional views showing the flow of a method of manufacturing a flash memory cell according to a fourteenth embodiment of the present invention. 8A through 8F are cross-sectional views showing the flow of a method of manufacturing a flash memory cell according to a fifteenth embodiment of the present invention. 9A to 9F are cross-sectional views showing the flow of a method of manufacturing a flash memory cell according to a sixteenth embodiment of the present invention. 10A through 10F are cross-sectional views showing the flow of a method of manufacturing a flash memory cell according to a seventeenth embodiment of the present invention. 11A to 11F are flow diagrams showing a method of manufacturing a flash memory cell according to an eighteenth embodiment of the present invention. 100112123 Form No. A0101 Page 33 of 75 1002020232-0 201242033. [0133] [0137] [0146] [0146] [0146] [0146] [0146] [0147] [0147] 12A to 12F are cross-sectional views showing the steps of a method of fabricating a MOS field effect transistor according to a nineteenth embodiment of the present invention. [Main component symbol description] 10: Substrate 12: Well region 14: First doped region 14a, 14b: Source or electrodeless doped region 16: Hard mask layer 18: Clearance walls 20, 20a, 20b, 36 : Ion implantation process 22: second doped regions 22a, 22b: region 24: dielectric layer, tunneling dielectric layer 26: charge storage dielectric layer 28: top dielectric layer 3 0: gate, floating gate 30a, 30b: floating gate material layer 32: trench 32a: side wall 100112123 Form No. A0101 Page 34/75 page 1002020232-0 201242033 [0148] 32b: bottom angle [0149] 32c: bottom [0150] 34: channel area 38: photoresist layer [0152] 40: semiconductor layer [0153] 42: opening [0154] 44: spacer material layer Ο [0155] 46: spacer [0156] 50a: control gate material layer [0157] 50: control gate [0158] 52: insulating layer [0159] 54: groove surface [0160] 5 6 : metal lithium 〇 [0161] wl, w2, w3, w4: width [0162] hl, h2, h3 :depth [0163] tl ' t2 ' t3 : thickness 100112123 form number A0101 page 35 / total page 752020232-0

Claims (1)

201242033 VII. Patent application scope: 1. A semiconductor device comprising: a first doped region having a first conductivity type in a substrate, a trench in the first doped region; and a second conductivity type a doped region is disposed at the bottom of the trench, and the first doped region is separated into a separated source doped region and a drain doped region, and between the source doped region and the drain doped region a channel region; a gate is located in the trench; and a dielectric layer is between the gate and the substrate of the trench. 2. The semiconductor component of claim 2, wherein each of the source or drain doped regions extends along the sidewall from the bottom of the trench to a bottom corner to a surface of the 5 kel base. 3. The semiconductor device of claim 2, wherein the second doped region comprises two first regions and a second region having different depths, wherein an area of the second region away from the bottom of the trench is larger than An area of the first region near the bottom of the trench is such that the source or drain doped region is stepped. 4. The semiconductor device of claim 2, further comprising a spacer between the dielectric layer on the sidewall of the trench and the substrate. 5. The semiconductor device of claim i, wherein the second dummy region extends from a bottom of the trench to a side wall of the trench near a bottom corner, such that each source or electrodeless region is not included The bottom and bottom corners of the trench are covered and extend from the sidewall of the trench to the surface of the trench. 6. The semiconductor device of claim i, further comprising a semiconductor layer that completely covers and contacts the source or electrodeless doped regions. The semiconductor element of the sixth aspect, wherein the semiconductor layer comprises a doped single crystal germanium layer, a doped polysilicon layer, and a doped layered surface, wherein the semiconductor layer comprises a doped single crystal germanium layer, a doped polysilicon layer, and a doped layer. The germanium layer is doped with a germanium telluride layer or a combination thereof. ^ The semiconductor component of claim 6, further comprising a metal-lithium layer on the semiconductor layer. 9. The semiconductor device of claim 6, further comprising a hard mask layer on the semiconductor layer. 10. The semiconductor component of claim i, further comprising a hard mask layer on the source or drain doping region. The semiconductor device of claim i, wherein the dielectric layer is further extended over the source or drain doping region. 12. The semiconductor device of claim i, wherein the closed electrode extends over the source or the non-polar doped region. 13. The semiconductor component of claim 1, wherein the semiconductor component is a MOS transistor, and the dielectric layer is a gate dielectric layer. 14. The semiconductor component of claim 1, wherein the semiconductor component is a non-volatile memory cell and the dielectric layer is a tunneling dielectric layer. The semiconductor device of claim 14, wherein the closed gate is a floating gate, and further comprising: a control gate is located above the floating gate; and a gate dielectric layer is located at the floating Between the gate and the control gate. The semiconductor device of claim 15, wherein the floating gate protrudes from a surface of the substrate. The semiconductor device of claim 15, wherein the floating gate, the closed dielectric layer, and the control gate extend further above the source or drain doping region. 100112123 Form No. A0101 Page 37 of 75 1002020232-0 201242033 18 19 20 21 22 23 . 24 . . . The semiconductor element of claim 15 wherein the surface of the floating surface is a flat surface or A surface with grooves. The semiconductor device of claim 14, further comprising a storage dielectric layer between the tunneling dielectric layer and the gate. The semiconductor component of claim 19, wherein the charge storage dielectric layer extends over the source or drain doping region. = The semiconductor device of claim 19, further comprising a shell dielectric layer between the charge storage dielectric layer and the gate. And a method of manufacturing a semiconductor device, comprising: providing a substrate; forming a first doped region having a first conductivity type in the substrate; removing a portion of the first doped region to Forming in the doped region - the channel 9 forms a second doped region having a second conductivity type at the bottom of the trench, and dividing the first doped region into two source or drain doped regions; Forming a gate in the trench; and forming a dielectric layer between the gate and the substrate of the trench. The method for fabricating a semiconductor device according to claim 22, further comprising forming a spacer on a sidewall of the trench. The method of fabricating a semiconductor device according to claim 23, wherein the second doping-forming method comprises performing a single ion implantation process with the mask (the fourth substrate) as a mask to separate the respective sources The extremely doped region is from. The surface of the base of the base extends along the side wall to the bottom of the trench near the bottom corner. Form number A0101 is as stated. The method for manufacturing a semiconductor device according to Item 23, wherein the method for forming the 6-second second doped region comprises using the spacer as a mask - 100205 Page 38 / 75 pages 201242033 First ion implantation a process and a second ion implantation process, wherein the energy of the second ion implantation process is higher than the energy of the first ion implantation process, so that the second ion implantation process forms an area away from the bottom of the trench The area is larger than the area of the first ion implantation process that is close to the bottom of the trench. The method of fabricating a semiconductor device according to claim 23, further comprising removing the spacer after forming the second doped region and before forming the dielectric layer. 27. The method of manufacturing a semiconductor device according to claim 22, wherein θ The method of forming the second doped region in 100112123 includes performing an ion implantation process with the trench as a mask such that the second doped region extends from the bottom of the trench to a side wall near a bottom corner. The method of fabricating a semiconductor device according to claim 22, further comprising forming a semiconductor layer on the substrate before the trench is formed, the semiconductor layer being in contact with the first doped region. The method of fabricating a semiconductor device according to claim 28, further comprising forming a hard mask layer on the semiconductor layer after forming the semiconductor layer and before forming the trench. 30. The method of fabricating a semiconductor device according to claim 29, further comprising removing the hard mask layer after forming the trench and before forming the dielectric layer. The method of manufacturing a semiconductor device according to claim 29, further comprising removing the hard mask layer after forming the gate. The method of manufacturing a semiconductor device according to claim 29, further comprising forming a deuterated metal layer on the semiconductor layer after removing the hard mask layer. Form No. 1010101 Page 39/75 Page 1002020232-0 201242033 33 · The remote method of the semiconductor component as described in the scope of the patent application, including the formation of a hard disk on the substrate before forming the trench Floor. The method of manufacturing a semiconductor device according to claim 33, further comprising removing the hard mask layer before forming the dielectric layer. 35. The method of fabricating a semiconductor device according to claim 22, wherein the semiconductor device is a MOS transistor, and the dielectric layer is a gate dielectric layer. 36. A method of fabricating a semiconductor device according to claim 22, wherein the semiconductor device is a non-volatile memory cell and the dielectric layer is a tunneling dielectric layer. The method of manufacturing a semiconductor device according to claim 22, wherein the gate is a floating gate, and the method further comprises: forming a control gate on the floating gate; and the floating gate A gate dielectric layer is formed between the control gates. 38. The method of fabricating a semiconductor device according to claim 22, further comprising: forming a hard mask layer on the substrate before forming the trench; causing the upper surface of the gate in the trench to be low a sidewall of the hard mask layer is exposed on the upper surface of the hard mask layer; a gate material layer is formed on the sidewall of the hard mask layer and the gate to form a floating gate having a groove surface; Forming a control gate on the floating gate; and forming a gate dielectric layer between the floating gate and the control gate. 39. The floating $, the inter-gate electrical layer, and the control formed in the method of fabricating the semiconductor device of claim 37, further extending over the source or the non-polar doped region. The method of fabricating a semiconductor device according to claim 36, further comprising forming a charge storage dielectric between the tunnel dielectric layer and the gate. 1002020232-0 100112123 Form No. A0101 Page 4 / Total? The method of manufacturing a semiconductor device according to claim 40, wherein the charge storage dielectric layer extends further to the source or the drain doping region 〇42. The method for fabricating the semiconductor device of claim 40, further comprising forming a top dielectric layer between the charge storage dielectric layer and the gate. 〇 ❹ 100112123 Form number A0101 Page 41 of 75 1002020232-0