TWI353672B - Non-volatile memory and fabricating method thereof - Google Patents

Description

1353672 095006(1) 21483twf.doc/n IX. Description of the Invention: TECHNICAL FIELD The present invention relates to a semiconductor element, and more particularly to a non-volatile memory and a method of fabricating the same. [Prior Art] When the semiconductor enters the Deep Sub-Micron process, the size of the element is gradually reduced. For the memory element, the memory cell size is becoming smaller and smaller. On the other hand, with information electronics (such as computers, mobile phones, digital cameras or personal digital assistants (personal Digital)

Assistant, PDA)) The amount of data that needs to be processed and stored increases, and the amount of memory required in these information electronics products is increasing. In the case where the size is small and the memory capacity needs to be increased, how to make the size reduction, the degree of integration, and the uniformity of the memory components of the quality can be achieved. /' Non-volatile memory components have the advantage of making the stored data not disappear after power-off, so it has become a memory component widely used in oil-based computers and electronic devices. / 丨典 f's hair memory component is made up of a doped polysilicon 矽si icon as a floating gate (published (four) gamma) and a control gate: 01 Gate) to form a stacked structure gate and control gate A dielectric layer is provided between the layers. The multi-reed hair memory needs to form a multi-layered polycrystalline stone layer and the process of going through multiple reticle steps, stretching the clothes for private use, and costing more manufacturing costs. 5 1353672 095006(1) 21483twf.doc/n _US^^ US 6678190 discloses a non-volatile memory, such memory n money (four) nostalgic crystal rhyme 'but two pieces of two connected in the N well 1> type MOS transistor as the selection gate is more floating two 'two! : The control gate is not formed, so the process of the non-volatile memory can integrate the process of the MOS transistor to reduce the manufacturing cost. σ

The non-volatile memory stylized or read kinetics formed on such early-layered ceramsite is not _, but when the erase operation is performed, the voltage is usually applied to the well area. To the floating _, so that the floating closed pole forms a foot_difference with the well d, and the germanium electrons pass through the dielectric layer: the pure and removed. Since the programming operation and the erasing operation of the non-volatile memory are performed, the electrons are traversed through the dielectric layer and are discharged into the gate or discharged from the floating gate, so that it is easy to wear the device. The electrical layer is damaged and causes leakage current, resulting in a decrease in the reliability of the memory component. As the component fill increases, the resulting high leakage current will be more severe, which will greatly limit the size of the component. Another disadvantage of using the well-area-electrical-combination method is that the efficiency may not be good, which may require the wire to be in the well H. The electricity may be very A, so that the single-layer polycrystalline non-volatile memory requires a high-voltage module. In this way, the process complexity becomes higher and the cost is not easy to reduce. SUMMARY OF THE INVENTION In view of the above, an object of the present invention is to provide a non-volatile memory in which a conductive plug is disposed as a erase gate on a dielectric layer between gates of a floating gate, which can be non-volatile. The memory is repeatedly programmed and wiped 095006(1) 21483twf.doc/n =:=moving through, layer 2 is directly applied to the floating closed-end 度=degree plug, I efficiency is very good, can reduce erase Voltage, Reducing Process Negative Miscellaneous Another object of the present invention is to provide a method of connection, - Γ ν, and the manufacture of a non-volatile memory to produce a non-volatile semiconductor process. Non-volatile memory can increase the accumulation of memory S. The present invention proposes a non-volatile memory isolation structure, a floating closed crystal, and a specific gate-brake B/structure disposed on the substrate towel to define the A-outlet region. Floating =; ΓΓ-based wide floating inter-electrode has a floating closed pole, a second electric layer, a source/secret area and a second secret/secret area. The floating gate r is placed on the substrate' and spans the active area. The wearing dielectric layer is placed in the floating red room. The first source/secret area is distinguished from the second source/drainage layer. The limb dielectric layer acts as a dielectric layer between the gates of / : St. The erase gate is placed on a specific dielectric, and the erase gate is the first conductive plug. Layer In accordance with a non-volatile memory of the preferred embodiment of the invention, the specific dielectric layer of J covers the portion of the m-gate. According to a non-volatile memory of the preferred embodiment of the present invention, the specific dielectric layer covers the entire floating gate. According to a preferred embodiment of the present invention, the non-volatile memory has a ratio of 3672 095006 (1) 21483 twf. doc; and the specific dielectric layer is made of yttrium oxide or yttrium oxynitride. In accordance with a non-volatile memory of the preferred embodiment of the present invention, the noisy is erased, the floating (tetra) pole-end is disposed, and is located above the isolation structure. The non-volatile memory according to the preferred embodiment of the present invention further includes a second plug and a third conductive plug respectively electrically connected to the first source/drain region and the second source/ Bungee area. According to a preferred embodiment of the present invention, the non-volatile memory is further provided in the base red, and (4) is connected to the gate electrode, and the selection gate has a gate and a gate. The electrical layer, the third source, the // and the polar regions and the first source/no-polar region. The selection gate is placed on the substrate and spans the active area. The gate dielectric is placed between the selection and the substrate I. The first region and the second source 'the non-polar region are respectively disposed on the selective gate two = the transmissive memory according to the preferred embodiment of the present invention, and the specific dielectric layer above covers a portion of the floating gate Share. The specific dielectric layer covers the whole basket

According to the Α?, the light singer of the present invention is also a gentleman, + π private..

The non-volatile memory of the preferred embodiment of the invention, the second conductive plug and the third conductive plug, the external companion memory are electrically connected to the first source 8 1353672 095006, respectively. 2l483twf.doc/n pole/nopole zone and third source/bungee zone. The non-volatile memory of the invention is made by the first conductive plug which is disposed on the floating gate. Moreover, '(4) a specific dielectric layer (self-scale metal-wet resistive layer or resistive protective oxide layer) acts as a dielectric layer between the inter-gate dielectric between the floating interpole and the first conductive interpole, so it can be left unchanged - (: : Producing non-volatile notes in the case of rolling semiconductors, (4). When the voltage is applied to the first conductive plug (wiping the gate), 'just two:' and read the first conductive plug in the floating track. The plug can be erased by smearing the electrons from the floating gate through the specific dielectric layer with the effect barrier or against the protective oxide layer. By setting the eraser to the body and repeating the stylization and wiping it, the right-handed conductive plug (wiping the gate) is set to make the first-wheel plug (erasing the closed pole) and: the area can be reduced, That is to say, it can be reduced to wear the window, and the lighter one can speed up the erasing when erasing the memory. / The present invention proposes a non-volatile memory manufacturing region "interelectrode, through dielectric layer, first-source/drainage f multi-divided portion of the dielectric layer n remaining 1 after. A first conductive plug is formed on the dielectric layer, which is 9 1353672 095006 (1) 21483 twf.doc / n a conductive plug as an erase gate. 造方 = "The non-volatile memory system described in the example /, towel to remove part of the specific dielectric layer, leaving only the bit, the specific dielectric layer steps are as follows. First, ^ two; float = pole. Then, with the mask layer as a mask, the portion St"" is removed. Thereafter, the mask layer is removed. The non-volatile memory method according to the preferred embodiment of the present invention is specific to Before the step of forming the first conductive plug on the dielectric layer, the interlayer insulating layer is further formed on the substrate. The specific dielectric layer is formed according to the method of non-volatile memory. Covering a portion of the floating gate. According to the method of non-volatile memory of the preferred embodiment of the present invention, the specific dielectric layer covers the entire floating gate. The method for manufacturing a non-volatile memory according to a preferred embodiment of the present invention, in the step of forming a first conductive plug on a specific dielectric layer, further comprising electrically connecting the first source/汲a first conductive plug and a third conductive plug of the polar region and the second source/drain region. A method for fabricating a non-volatile memory according to a preferred embodiment of the present invention The material comprises cerium oxide or oxynitride eve. According to a preferred embodiment of the invention The edge-making method of the hair memory further includes forming a selection gate transistor on the substrate, and selecting the gate transistor to connect the floating gate transistor in series, and selecting the gate transistor has a selection gate, a dielectric layer, and a third source /汲polar region and the second source/drain region. 丄095006(1) 21483twf.doc/n 造方: The steps of the specific dielectric layer on the basis of the volatile memory are as follows; The floating idler covers the floating idle pole. The mask m2 is first formed after the mask layer is formed on the substrate. A 4 turns, a part of the mosquito dielectric layer. ▲ The square body is formed on the substrate. Before the step of forming the interlayer insulation $ and the electrical plug, the Hi dielectric layer of the non-volatile memory described in the embodiment is covered to cover the portion of the floating open electrode. The non-volatile memory layer of the non-volatile memory covers the entire floating opening. The second side of the non-volatile memory is described in the preferred embodiment of the second day.轮之第== 狮与第三办和极造方 ί照 Γ Γ Γ Γ 佳 实施 实施 实施 实施 实施 实施 实施 实施 实施 非 非 非 非 非 非 非(4) of the dielectric layer includes oxygen cutting or oxynitridation in the floating dielectric layer. The first conductive plug can be 11 1353672 095006 (1) 21483 twf.doc/n, and the third conductive plug is fabricated in the same process.制作To make non-volatile memory without changing the complementary MOS process. Moreover, the flute is formed between the floating idler and the first acoustic-upper plug (wiping off) The above-mentioned and other objects of the present invention are added to the preferred embodiment of the present invention. Figure 4: Embodiments [Embodiment] First, the non-volatile memory of the present invention will be described. (4) The non-volatile memory of the present invention - the preferred embodiment is shown as 1A, along the line AA, the cross-sectional view of the line c, 曰 is not a cross-sectional view taken along line B_B in Fig. 1A. It is set to the non-volatile memory of the present invention such as 〇X:土-. The substrate 100 is, for example, a crucible substrate. A well region 102 is provided, for example, in the substrate 100. Moreover, the isolation structure 104 is provided to define the main soil "for example, for example, a shallow trench isolation structure or field oxidation ^. Isolation - structure 1 〇 4 The non-volatile memory of the invention is L The gate electrode 1G8 is, for example, disposed on the substrate (10). The floating power is, for example, a tunneling dielectric layer 11〇, a floating gate ιΐ2, a source second=polar region U6, Source/no-pole area U8, specific dielectric layer plug 124. Etc. 4 broadcast 12 1353672 095006(1) 21483twf.doc/n moving area ==:==(10) on 'and across the main gate (4) The material of 2; the isolation junction (4) The dielectric layer 110 is, for example, between the first and second layers. The material 112 and the substrate of the dielectric layer UG are in the floating gate 112 and the dielectric layer; n oxonite Even more. Moreover, the gap wall m. the gap wall 114 ==, also _ there is

The source region 116 and the =::== m (four) are described in the "substrate 100." and the source/nopole region 116 and the source/polar region 118 are located in the active region. The specific dielectric layer m is, for example, floating. The specific dielectric layer 120 can cover a portion of the floating gate 112 or cover the entire ocean gate m. For example, the specific dielectric layer m can be disposed in the conductive plug Between the plug m and the floating gate (1), the material of the specific dielectric layer (10) is, for example, ruthenium oxide or ruthenium oxynitride.

The conductive plug 124 is, for example, disposed on a specific dielectric layer 12A. Moreover, the conductive plug 12 4 sets the floating gate 丨! 2 One end and just above the isolation structure. In the present invention, the conductive plug 124 acts as an erase gate. The material of the conductive plug 124 includes a conductor material, such as a metal material, and a plurality of conductive plugs 126 are further disposed on the source/j: and the pole region 116 and the source/drain region 118. Conductive plug 128. The conductive plug 126 and the conductive plug 128 are electrically connected to the source/drain region U6 and the source/drain region Π8, respectively. The material of the conductive plug 126 and the conductive plug 128 includes a conductor material, and 13 1353672 095006(1) 21483 twf.doc/n is, for example, a metal material, a doped polysilicon or the like. Conductive plug 124, conductive plug 126 and conductive plug 128 are formed in the same process. Moreover, the conductive plug 124, the conductive plug 126, and the conductive plug 128 are disposed, for example, in the interlayer insulating layer 122. The material of the interlayer insulating layer 122 is, for example, phosphor bismuth glass, borophosphoquinone glass or the like. 2A is a top view of a non-volatile memory in accordance with another preferred embodiment of the present invention. Figure 2B is a cross-sectional view taken along line A-A of Figure 2A. 2C is a cross-sectional view taken along line B_B of FIG. 2A. . Q Referring to Fig. 2A to Fig. 2C, the non-volatile memory of the present invention, for example, is disposed on the substrate 200. The substrate 200 is, for example, a crucible substrate. A well region 202 is provided, for example, in the substrate 2A. Moreover, an isolation structure 204 is provided, for example, in the substrate 2 to define the active region 2〇6. The isolation structure 2〇4 is, for example, a shallow trench isolation structure or a field oxide layer. The non-volatile memory includes a floating gate transistor 208 and a selection gate transistor 210, a specific dielectric layer 230, and a conductive plug 232 (erasing gate). The floating gate transistor 208 and the selection gate transistor 21 are, for example, disposed on the substrate 2, and are connected in series in series. — The thyristor 208 is formed, for example, by a tunneling dielectric layer 212, a floating gate 214, a source/drain region 218, and a source/drain region 22 。. The floating gate 214 is disposed, for example, on the substrate 2 and over the active region 206 such that a portion of the floating interpole 214 is located on the isolation structure 2〇4. The material of the floating gate 214 is, for example, doped polysilicon. The tunneling dielectric layer 212 is disposed, for example, between the floating gate 214 and the substrate 2A. The material of the tunneling dielectric layer 212 is, for example, oxidized ash. Further, 1353672 095006(1) 21483twf.doc/n may also be provided with a gap wall 216 on the sidewalls of the floating gate 2H and the dielectric layer m. The material of the spacer 216 is, for example, oxidized or nitrided. The source/drain regions 218 and the source/drain regions 22 are, for example, disposed in the substrate 2's on both sides of the floating gate 214, respectively. Moreover, the source/nomogram region 218 and the source/drain region 220 are located in the active region 2〇6. The gate transistor 210 is formed, for example, by a gate dielectric layer 222, a selective opening 224, a source/drain region 220, and a source/drain region 228. The select gate 224 is, for example, disposed on the substrate and spans the active region 206. The material of the gate 224 is selected, for example, to push the polycrystalline spine. The dielectric layer 222 is disposed, for example, between the selection gate η4 and the substrate. The material of the gate dielectric layer 222 is, for example, oxidized oxide. Further, a spacer 226 may be provided in the sidewalls of the gate 224 and the gate dielectric layer 222. The material of the spacer 226 is, for example, oxidized oxide or tantalum nitride. The source/drain regions 220 and the source and drain regions 228 are, for example, disposed in the substrates on both sides of the select gate 224, respectively. Moreover, source/drain regions 220 and source/no-polar regions 228 are located in active region 206. The floating gate transistor 208 shares the source/no-polar region with the selection gate transistor 21〇. The dielectric layer 230 is disposed, for example, on the floating gate 214. The specific portion 2 covers a portion of the ocean gate 214 and does not cover the floating gate 214 of the product 206. Of course, the specific dielectric layer 230 is disposed only between the conductive plug 232 and the floating gate 214. The material of the specific "electric layer 230" is, for example, oxygen cutting or arsenic oxynitride. The so-called specific dielectric layer 23G in the middle of the logic is a self-aligned metal wafer layer in the logic process (Sdf-Aligned Salicide 15 1353672). 095006(]) 21483twf.doc/n

The film layer of Block Oxide'SAB). (4) 'In the semiconductor component wafer, the main component area and the peripheral circuit area are generally distinguishable, and the element in the main L is opened. The components in the 丨 红 红 ' ' ' ' 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 (mectro-S her Discharge, ESD) The protection circuit and the like are located in the road area, for example, logic elements and the like. Because the elements in the main component area are the same as the electrical components of the peripheral circuit. Therefore, after the formation of the element, the eve process is usually performed to form a layer of metal material on the closed/pole region, thereby reducing the resistance of the element. However, in the above-mentioned Wei process, it is necessary to cover the portion which does not need to form the metal ruthenium by the film layer (specific dielectric layer 23 〇) to avoid the occurrence of the lithospheric reaction. The specific dielectric layer 230 (Seif Aii (S) Salidde Bbclc Oxide ' SAB) or the protective oxide layer used as the floating gate and the conductive plug is used as the general logic processing towel. The dielectric layer between the gates (wiping the gate). Therefore, the non-volatile memory of the present invention can be made without changing the complementary MOS process without adding extra space, and the degree of accumulation of the memory elements can be increased. The conductive plug 232 is disposed, for example, on a specific dielectric layer 230. Moreover, the conductive plug 232 is disposed at one end of the floating gate 214 and above the isolation structure 2〇4. In the present invention, the conductive plug 232 is used as an eraser. In addition, a conductive plug 234 and a conductive plug 236 are further disposed on the source/drain region 218 and the source/drain region 228. The conductive plug 234 and the conductive plug 236 are electrically connected to the source/drain region 218 and the source/drain region 228, respectively. The material of the conductive plug 234 and the conductive plug 236 includes a conductor material, 16 丄 ^ 3672 095006 (1) 21483 twf.d 〇 c / n such as a bismuth metal material, doped polycrystalline stone, and the like. The conductive plug 232, the conductive plug 234 and the conductive plug 236 are formed in the same process. Moreover, the conductive plug 232, the conductive plug 234, and the conductive plug 236 are disposed, for example, in the interlayer insulating layer 238. The material of the interlayer insulating layer 238 is, for example, a stone-filled glass or a boron-filled glass. Further, as shown in Fig. 2A, a well zone pull-out zone 240 may also be provided in the substrate 200. The well area pull-out area 24〇 connects the well area 2〇2. A conductive plug 242 is provided, for example, on the well draw-out area 240. The conductive plug 242 is electrically connected to the well region 202. 3A is a top view of a non-volatile memory in accordance with still another preferred embodiment of the present invention. Figure 3B is a cross-sectional view taken along line A-A of Figure 3A. 3C is a cross-sectional view taken along line B-B of FIG. 3A. The same components as those in Figs. 2A to 2C are given the same reference numerals in Figs. 3A to 3C, and detailed description thereof will be omitted. Referring to Figures 3A through 3C, the non-volatile memory of the present invention, e.g., tantalum, is placed on substrate 200. The substrate 200 is, for example, a base substrate. A well region 202 is provided, for example, in the substrate 2A. Moreover, an isolation structure 204 is provided, for example, in the substrate 2 to define the active region 206. The non-volatile memory includes a floating gate transistor 2〇8 and a selection gate transistor 210, and a specific dielectric layer 230a' conductive plug 232 (erasing gate). The floating gate transistor 208 and the selection gate transistor 21 are, for example, disposed on the substrate 2, and are connected in series in series. The floating gate transistor 208 is formed, for example, by a tunneling dielectric layer 212, a floating gate 214, a source/drain region 218, and a source/drain region 22A. In the floating 17 1353672 095006 (1) 2l483twf.doc / n the gate 214 and the tunnel dielectric wall -1$. ^ Θ ^ side soil, for example, is provided with a spacer 216. The inter-connector transistor 21, for example, 224, and the source/drain region 22 〇 / 222 are selected to select the interpolar pole and the pole region 228. The gate 224 and the gate dielectric layer 22 may also be provided with a spacer 226 on the side wall of the selection Β 2 . / Pre-gate transistor 2〇8 virtual region 22〇. /~ Selecting the gate $Japanese body 210 sharing source / 汲 The eight-coin dielectric layer side is, for example, disposed on the floating interpole 214. specific

The cover layer covers the entire floating gate 214. The material of the specific dielectric layer is, for example, tantalum oxide or tantalum oxynitride, etc. The conductive plug 232a is disposed, for example, on a specific dielectric layer 23〇a. The plug is provided with the end of the floating gate and is located above the isolation structure 2〇4. In the present invention, the conductive plug 232 is used as the erased closed pole. Since the conductive plug 232a is disposed on the floating gate 214 Therefore, the area between the central gate 214 and the conductive plug can be reduced, that is, the tunneling window can be reduced. When the memory is erased,

Speed up the erasure. Of course, the conductive plug 232a can also be disposed at any position on the specific dielectric layer 230a. In addition, a conductive plug 234 and a conductive plug 236 are further disposed on the source/drain region 218 and the source/drain region 228. The conductive plug 234 and the conductive plug 236 are electrically connected to the source/drain region 218 and the source/drain region 228, respectively. Moreover, the conductive plug 232, the conductive plug 234, and the conductive plug 236 are disposed, for example, in the interlayer insulating layer 238. Further, a well zone pull-out zone 240 may also be provided in the substrate 200 as shown in Fig. 3A. This well zone pull-out zone 240 connects the well zone 202. Pull out in the well area 1353672 095006 (1) 21483twf.doc / n area 24 〇 for example. A conductive plug sc is also placed. The conductive plug (10) is electrically connected to the well region 202. In the non-volatile memory of the present invention, a conductive plug is provided on the free dielectric layer on the floating interpole. This conductive plug can serve as an eraser. 〃Using special features; the i-electrode layer (self-aligning the metal-block barrier or resisting the protective oxide layer) acts as the "electrical layer" between the floating gate and the conductive plug (wiping the interpole). Non-volatile memory is produced without changing the general complementary MOS process. Moreover, when a voltage is applied to the conductive plug (erasing the gate), it can reach the floating idler' and The floating and conductive plugs (the voltage difference formed between the erased electrodes is formed, and the F_N wear-through effect is generated, so that the electrons are discharged from the floating (f) specific dielectric layer (the metal-containing material barrier layer or the protective oxidation resistance) The layer is exported to the conductive plug (erasing the gate), and the memory can be erased. By setting the erase gate, the non-volatile memory of the present invention can be repeatedly programmed and erased. In addition, if the conductive plug (wiping gate) is provided with one end of the floating gate, • the area between the conductive plug (wiping gate) and the floating gate can be reduced, that is, it can be reduced Tunneling window. When erasing this memory, you can add Next, the manufacturing method of the non-volatile memory of the present invention will be described. Figure 4A to Figure 4D are cross-sectional views showing the manufacturing process of the non-volatile memory of the present invention, which is illustrated in Figures 5A to 5D. A cross-sectional view of the manufacturing process of the non-pinched memory of the present invention. Fig. 4A to Fig. 4A are cross sections corresponding to the line A-A'; Fig. 5A to Fig. 5D are corresponding to B_B in Fig. 3A, and the line is divided into 1353672 095006 (1) 2l483twf.doc/n face. Referring to Figures 4A and 5A simultaneously, a substrate 3 is first provided. The substrate 3 is, for example, a germanium substrate. A well region 3〇2 is formed in the substrate 3〇〇. The formation method of the region 302 is, for example, an ion implantation method. Next, a spacer is formed in the structure, and the isolation structure is, for example, a shallow trench isolation structure.

Next, a gate structure 3〇6a and a gate structure 〇6b gate structure 3 are formed on the substrate 300. For example, the gate structure 306b is formed by the dielectric layer 3〇ga and the floating gate 31〇. The gate dielectric layer 3〇8b and the selected gate=jin are formed. The method for forming the gate structure 3〇6a and the gate structure 3〇6b=such as the formation of a dielectric layer and a layer of a conductor material layer on the substrate 3GG, followed by a lithography process, a patterned conductor (4) . Wear the financial layer and the electric layer of the material f = Z 矽. Of course, the material and thickness of the tunneling dielectric layer 3〇8a and the gate dielectric layer 3 may be the same or different. The floating gate 31〇a and the selective gate 3i〇b 2 are, for example, doped and multi-corrected, and the formation method thereof is, for example, chemical meteorology

Referring to Fig. 4B and Fig. SB, a dopant implantation step is performed to form lightly doped regions 312 & 31, 3i2c in the T. For example, the doping is implanted into the base of the substrate by ion implantation (the material of the sidewall structure of the gate structure 306a and the gate structure 3_, and the material of the spacers 314a, 314b is, for example, oxidized stone. Etc. The formation of the spacers 314a, 314b is formed by chemical vapor deposition, after the layer of insulating material is removed, and the portion of the insulating material is removed (4). ° 20 1353672 095006 (1) 2l483twf. Doc/n then 'with the gate structures 3〇6a, 306b having the spacers 314a, 314b as masks, the dopant implantation step is performed, and the heavily doped regions 316a, 316b, 316c are formed on the substrate 3. The dopant implantation step is, for example, implanting a dopant into the substrate 300 by ion implantation. The lightly doped region 312a and the heavily doped region 316a constitute a source/drain region 318a; the lightly doped region 312b is heavily doped The region 316b constitutes the source/drain region 318b; the lightly doped region 312c and the heavily doped region 316c constitute the source/drain region 318 (^ gate structure 3, source/drain region 318a and source/ The bungee region 318b constitutes a floating gate transistor. The gate electrode structure 3〇6b, the source/polar region 318b and the source/drain region 3 are decoupled to form a closed cell. Referring to FIG. 4C and FIG. 5C, a layer of electrical layer 320 is formed on the substrate. The specific dielectric layer 32 is, for example, a general logic layer 自行 self-aligned metal barrier layer. The crystal layer 320 of the anti-oxidation layer is in the self-alignment process, using ^ =

=: sub-! layer to avoid the shearing reaction; raw = ^ ί "2 5 and the self-aligned metal fragmentation in the avoidance process to make the non-volatile material of the present invention, for example It is an oxide stone 鸠 = in-body. The special-dielectric layer is then formed on the substrate 300 - the stem plate covers the dielectric on the gate structure 3G6a; the mask layer 322 is, for example, a photoresist material s 0. The mask layer 322 The method for forming the material shattering mask layer 322 is formed, for example, by applying a layer of photoresist material by spin coating on the substrate 21 1353672 095006 (1) 21483 twf.doc/n 300 and then performing a micro-process. The material of the mask layer 322 may also be other materials. Referring to FIG. 4D and FIG. 5D, the mask layer 322 is used as a mask to remove the dielectric layer 320' and leave only the dielectric 320 on the gate structure 3. A portion of the dielectric layer 32 is removed. The method includes wet etching, and hydrofluoric acid is used as an etchant. Then, the mask layer 322 is removed. Then, an interlayer insulating layer 324 is formed on the substrate 300. The material of the interlayer insulating layer 324 is, for example, phosphor bismuth glass, borophosphon glass or the like. Conductive is formed in the interlayer insulating layer 324. Plugs 326, 328, 33〇. = Electrical plug 328 The power plugs 33 are electrically connected to the source/drain regions 318a and the source/pole regions. The conductive plugs 326 are located at the floating poles. The dielectric layer 32a is connected to the dielectric layer 32A. The conductive plug 326 is used as a eraser. The steps of forming the conductive plugs 326, 328, 330 are as follows. First, the interlayer insulating layer 324 is patterned to form a plug opening σ. The plug opening exposes the dielectric layer 320a, the source/drain region 318a and the source/drain region 318A. Thereafter, the plug opening is filled with a conductive material to form it. In the method of manufacturing the memory, since the conductive recording is formed on the floating gate, the specific electrical layer (self-aligning the metallization resisting layer or resisting the protective oxide layer) is used as the floating gate. The dielectric layer is closed between the conductive plug (wiping the gate), so that the military can be made without changing the complementary sub-conductance (four) ^, and the conductive plug (wipe In addition to the gate) directly placed on the dielectric layer of the gate on the floating gate, does not add extra space, but can increase by half The degree of accumulation of conductor elements. 22 1353672 095006(1) 21483twf.doc/n In summary, in the case of the conversion of the system, due to the conductive plug on the closed dielectric layer on the floating gate, the method can be used for riding _, and 'This is aligned with the metal-shield resistive layer or resists the protection of the oxidized Hi-electric layer (self: the plug of the source-salt region of the corpus callosum is in the same out. Therefore, it can be changed without changing - the complementary galvanic coat The scaly memory is produced under the condition of the main condition, and the increase of the amount of the memory element can be increased without increasing the amount of the memory element. Although the present invention has been disclosed in the preferred embodiment as above, the iron invention is familiar with any of the above. The skilled artisan can make some changes and refinements without departing from the essence of the present invention. Therefore, the scope of the present invention is defined by the scope of the appended claims, and * [simplified description of the drawings 1A is a top view of a memory of the present invention. The opening 1 is shown in FIG. 1A as a cross-sectional view of the line along the line 。 。. Figure ic is shown in Figure 1 A cross-sectional view along the line Β Β 。. Memory is another non-volatile diagram of the preferred embodiment of the invention Β 2C is a cross-sectional view along the line Α_Α, Figure 2C is a cross-sectional view along the line Β_Β in Figure 2Α. Figure 7 is a further example of the invention. Figure 1B is a cross-sectional view taken along line A_A in Figure 3A. Figure 3C is taken along line B_B in Figure 3A. Figure 1B is a cross-sectional view taken along line A_A in Figure 3A. 4A to 4D are cross-sectional views showing a manufacturing process of a non-volatile memory according to a preferred embodiment of the present invention. Figs. 5A to 5D are diagrams showing a preferred embodiment of the present invention. Cross-sectional view of the manufacturing process of the non-volatile memory. [Main component symbol description] 100, 200, 300: substrate 102, 202, 302: well region 104, 204, 304: isolation structure 106, 206: active region 108, 208 : floating gate transistors 110, 212, 308a: tunneling dielectric layers 112, 214, 310a: floating gates 114, 216, 226, 314a, 314b: spacers 116, 118, 218, 220, 228, 318a , 318b, 318c: source / > and polar regions 120, 230, 230a, 320, 320a: specific dielectric layers 122, 238, 324: interlayer insulating layers 124, 126, 128, 232, 234, 2 36, 242, 326, 328, 330: conductive plug 210: select gate transistor 222, 308b: gate dielectric layer 224, 310b: select gate 24 1353672 095006 (1) 21483twf.doc / n 240: well area pull Outlet regions 306a, 306b: gate structures 312a, 312b, 312c: lightly doped regions 316a, 316b, 316c · concentrated doped regions 322: mask layer

25

Claims (1)

100-9-27 X. Patent application scope · · —— 1曰- kinds of non-volatile memory (4) manufacturing methods, including · · Floating ' ΐ ΐ has formed on the substrate - floating gate transistor, the pole 1 a closed-pole, a dielectric layer, a first source/and a pole E and a second source/drain region; forming a specific dielectric layer on the substrate; the dielectric layer , leaving only the conductive == into-first conductive plug on the floating gate, wherein the first manufacturing side is a non-volatile memory forming gate 1 as described in Patent Item 1 The step of leaving the dielectric layer on the floating gate except for a portion of the specific dielectric layer includes: forming a mask layer covering the floating gate; shifting: the mask Curtain, remove part of the specific dielectric layer; and the method of making 3, such as Shen 2: = 介介 i;: said: before the non-volatile discussion, the step is further included in the step of the base two conductive plugs = = circumference 41, the non-volatile memory system 5 such as Shen Mei straight ^, 丨 - '丨 electric layer covers part of the ocean gate. Method 2, 2: The non-volatile memory of the item 1 is made up of: ί, and the dielectric layer covers the entire floating questioner. The non-volatile memory system 1353672 100-9-27 described in Item 1 of the above-mentioned item is included in the substrate to form a selective gate transistor, and the selective idle transistor is connected in series to the floating gate transistor. The = one choice gate, one gate dielectric reed is a basket _, heart evaluation J electric 曰 day basket including source / no pole area. "and the L source/secret area and the second method of manufacturing the transfer memory of the ship" to remove a portion of the specific dielectric layer, the step of placing the specific dielectric layer on the gate includes: Located at i y = ί ΐ ί 成 成 成 成 成 成 成 成 罩 罩 罩 罩 罩 罩 罩 罩 罩 罩 罩 罩 罩 罩 罩 罩 罩 罩 罩 罩 罩 罩 罩 罩 罩 罩 罩 罩 罩 罩 罩 罩 罩 罩 罩 罩 ; ; 罩 ; Forming a method of forming an interlayer insulating layer w on the substrate, a method of forming a non-volatile memory, and a part of the intermediate portion of the patent application range. The manufacturing method, wherein the specific eight item 11. The non-volatile memory 11. If the W-range range is the sixth layer = the entire floating gate. In the step, the Μ(4) is formed; the third source/drain region of the field-first plug - _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ The material of the layer includes yttrium oxide or nitrogen oxide 27