TWI256726B - Non-volatile memory and fabricating method thereof - Google Patents

Non-volatile memory and fabricating method thereof

Info

Publication number
TWI256726B
TWI256726B TW94107440A TW94107440A TWI256726B TW I256726 B TWI256726 B TW I256726B TW 94107440 A TW94107440 A TW 94107440A TW 94107440 A TW94107440 A TW 94107440A TW I256726 B TWI256726 B TW I256726B
Authority
TW
Taiwan
Prior art keywords
layer
charge trapping
metal gate
substrate
volatile memory
Prior art date
Application number
TW94107440A
Other languages
Chinese (zh)
Other versions
TW200633191A (en
Inventor
Kent Kuohua Chang
Original Assignee
Macronix Int Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Macronix Int Co Ltd filed Critical Macronix Int Co Ltd
Priority to TW94107440A priority Critical patent/TWI256726B/en
Application granted granted Critical
Publication of TWI256726B publication Critical patent/TWI256726B/en
Publication of TW200633191A publication Critical patent/TW200633191A/en

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  • Non-Volatile Memory (AREA)

Abstract

A non-volatile memory which is constituted of a substrate, a metal gate layer, a source region and a drain region, a tunneling dielectric layer, a charge trapping layer, a blocking dielectric layer and a channel region is provided. The metal gate layer is formed on the substrate. The source region and the drain region are located in the substrate on both sides of the metal gate layer. The tunneling dielectric layer is located between the metal gate layer and the substrate. The charge trapping layer is located between the tunneling dielectric layer and the metal gate layer. The charge trapping layer is constituted of a plurality of charge trapping blocks which are divided from a trench. The blocking dielectric layer is located between the charge trapping layer and the metal gate layer, and it fills the trench in the charge trapping layer. The channel region is located in the substrate between the source region and the drain region under the charge trapping layer.
TW94107440A 2005-03-11 2005-03-11 Non-volatile memory and fabricating method thereof TWI256726B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW94107440A TWI256726B (en) 2005-03-11 2005-03-11 Non-volatile memory and fabricating method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW94107440A TWI256726B (en) 2005-03-11 2005-03-11 Non-volatile memory and fabricating method thereof

Publications (2)

Publication Number Publication Date
TWI256726B true TWI256726B (en) 2006-06-11
TW200633191A TW200633191A (en) 2006-09-16

Family

ID=37614762

Family Applications (1)

Application Number Title Priority Date Filing Date
TW94107440A TWI256726B (en) 2005-03-11 2005-03-11 Non-volatile memory and fabricating method thereof

Country Status (1)

Country Link
TW (1) TWI256726B (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI469361B (en) * 2011-04-08 2015-01-11 Macronix Int Co Ltd Semiconductor device and method of fabricating the same

Also Published As

Publication number Publication date
TW200633191A (en) 2006-09-16

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