JPH05304302A - Conductive film patterning method and fabrication of nonvolatile semiconductor memory - Google Patents
Conductive film patterning method and fabrication of nonvolatile semiconductor memoryInfo
- Publication number
- JPH05304302A JPH05304302A JP4131576A JP13157692A JPH05304302A JP H05304302 A JPH05304302 A JP H05304302A JP 4131576 A JP4131576 A JP 4131576A JP 13157692 A JP13157692 A JP 13157692A JP H05304302 A JPH05304302 A JP H05304302A
- Authority
- JP
- Japan
- Prior art keywords
- film
- conductive film
- etching
- photoresist
- polycrystalline
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 18
- 239000004065 semiconductor Substances 0.000 title claims description 9
- 238000000059 patterning Methods 0.000 title claims description 3
- 238000004519 manufacturing process Methods 0.000 title description 5
- 238000005530 etching Methods 0.000 claims abstract description 18
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 23
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 14
- 238000005516 engineering process Methods 0.000 abstract description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 6
- 229910052681 coesite Inorganic materials 0.000 abstract 3
- 229910052906 cristobalite Inorganic materials 0.000 abstract 3
- 239000000377 silicon dioxide Substances 0.000 abstract 3
- 235000012239 silicon dioxide Nutrition 0.000 abstract 3
- 229910052682 stishovite Inorganic materials 0.000 abstract 3
- 229910052905 tridymite Inorganic materials 0.000 abstract 3
- 239000011248 coating agent Substances 0.000 abstract 1
- 238000000576 coating method Methods 0.000 abstract 1
- 239000010408 film Substances 0.000 description 99
- 229910004298 SiO 2 Inorganic materials 0.000 description 18
- 238000000206 photolithography Methods 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- 230000010354 integration Effects 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Landscapes
- Drying Of Semiconductors (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本願の発明は、導電膜のパターン
形成方法及び浮遊ゲートを有する不揮発性半導体記憶装
置に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a conductive film pattern forming method and a nonvolatile semiconductor memory device having a floating gate.
【０００２】[0002]
【従来の技術】図３は、ＥＰＲＯＭ等の様に浮遊ゲート
を有する不揮発性半導体記憶装置の一従来例を示してい
る。この一従来例を製造するためには、、Ｓｉ基板１１
の表面に、素子分離用のＳｉＯ2 膜１２をＬＯＣＯＳ法
で行列状に形成し、ＳｉＯ2 膜１２同士の間のＳｉ基板
１１の表面に、浮遊ゲート用のゲート酸化膜であるＳｉ
Ｏ2 膜１３を形成する。2. Description of the Related Art FIG. 3 shows a conventional example of a nonvolatile semiconductor memory device having a floating gate such as an EPROM. In order to manufacture this one conventional example, the Si substrate 11
SiO 2 films 12 for element isolation are formed in a matrix on the surface of the Si substrate 11 by the LOCOS method, and on the surface of the Si substrate 11 between the SiO 2 films 12, the gate oxide film Si for the floating gate is formed.
The O 2 film 13 is formed.
【０００３】次に、多結晶Ｓｉ膜１４を全面に堆積さ
せ、多結晶Ｓｉ膜１４上にレジストを塗布する。その
後、公知の写真製版技術によってレジストに開口１５を
形成し、このレジストをマスクにして多結晶Ｓｉ膜１４
をエッチングする。そして、レジストを除去した後、多
結晶Ｓｉ膜１４の表面の酸化等によって、浮遊ゲートと
制御ゲートとの間の絶縁膜であるＳｉＯ2 膜１６を形成
する。Next, a polycrystalline Si film 14 is deposited on the entire surface, and a resist is applied on the polycrystalline Si film 14. After that, an opening 15 is formed in the resist by a known photoengraving technique, and this resist is used as a mask to form a polycrystalline Si film
To etch. After removing the resist, the surface of the polycrystalline Si film 14 is oxidized to form the SiO 2 film 16 which is an insulating film between the floating gate and the control gate.
【０００４】次に、再び多結晶Ｓｉ膜１７を全面に堆積
させ、多結晶Ｓｉ膜１７、１４とＳｉＯ2 膜１６、１３
とを制御ゲートのパターンに加工する。この結果、多結
晶Ｓｉ膜１７から帯状の制御ゲートが形成されると共
に、多結晶Ｓｉ膜１４から各メモリセル毎に分離された
浮遊ゲートが形成される。Next, the polycrystalline Si film 17 is again deposited on the entire surface, and the polycrystalline Si films 17 and 14 and the SiO 2 films 16 and 13 are deposited.
And are processed into the pattern of the control gate. As a result, a strip-shaped control gate is formed from the polycrystalline Si film 17, and a floating gate separated from the polycrystalline Si film 14 for each memory cell is formed.
【０００５】次に、多結晶Ｓｉ膜１７、１４等とＳｉＯ
2 膜１２とをマスクにしてＳｉ基板１１に不純物を導入
して、各メモリセルに共通のソースである拡散領域２１
と、各メモリセルのドレインである拡散領域２２とを形
成する。そして、多結晶Ｓｉ膜１７等を層間絶縁膜（図
示せず）で覆い、拡散領域２２に達するコンタクト孔２
３をこの層間絶縁膜に開孔する。Next, the polycrystalline Si films 17, 14 and the like and SiO
The impurity is introduced into the Si substrate 11 by using the 2 film 12 as a mask, and the diffusion region 21 which is a source common to each memory cell is introduced.
And a diffusion region 22 which is a drain of each memory cell. Then, the polycrystalline Si film 17 and the like are covered with an interlayer insulating film (not shown), and the contact hole 2 reaching the diffusion region 22 is formed.
3 is opened in this interlayer insulating film.
【０００６】その後、コンタクト孔２３を介して拡散領
域２２にコンタクトするビット線であるＡｌ配線２４を
形成する。なお、コンタクト孔２３及びＡｌ配線２４
は、図３（ｂ）（ｃ）には示していない。After that, an Al wiring 24, which is a bit line, which contacts the diffusion region 22 through the contact hole 23 is formed. The contact hole 23 and the Al wiring 24
Are not shown in FIGS. 3B and 3C.
【０００７】[0007]
【発明が解決しようとする課題】ところで、以上の様な
一従来例の製造方法では、制御ゲートの延在方向で浮遊
ゲート同士を各メモリセル毎に分離するために、写真製
版技術によって形成した開口１５を有するレジストをマ
スクにして、多結晶Ｓｉ膜１４をエッチングしている。
従って、０．６μｍが最小寸法である現在の写真製版技
術では、多結晶Ｓｉ膜１４同士のスペース幅２５も最小
でも０．６μｍになる。By the way, in the above-described conventional manufacturing method, the floating gates are formed by photolithography in order to separate the floating gates from each other in the extending direction of the control gates. The polycrystalline Si film 14 is etched using the resist having the openings 15 as a mask.
Therefore, in the current photolithography technology in which the minimum dimension is 0.6 μm, the space width 25 between the polycrystalline Si films 14 is also 0.6 μm at the minimum.
【０００８】しかし、このスペース幅２５は、メモリセ
ルの特性上からは０．６μｍも必要ではなく、構造だけ
考えればＳｉＯ2 膜１６の膜厚の２倍つまり０．５μｍ
もあれば十分である。However, the space width 25 is not required to be 0.6 μm in view of the characteristics of the memory cell, and if the structure is taken into consideration, it is twice the film thickness of the SiO 2 film 16, that is, 0.5 μm.
There is enough.
【０００９】しかも、図３（ａ）からも明らかな様に、
スペース幅２５はメモリセル面積を決定する重要なパラ
メータの一つであり、スペース幅２５が小さければ小さ
いほどメモリセル面積が小さくなる。従って、スペース
幅２５を小さくすることができない上述の一従来例の製
造方法では、メモリセル面積を小さくすることが難し
く、ＥＰＲＯＭ等の高集積化が難しかった。Moreover, as is clear from FIG. 3 (a),
The space width 25 is one of the important parameters that determine the memory cell area, and the smaller the space width 25, the smaller the memory cell area. Therefore, it is difficult to reduce the memory cell area in the manufacturing method of the above-described conventional example in which the space width 25 cannot be reduced, and it is difficult to achieve high integration of the EPROM or the like.
【００１０】[0010]
【課題を解決するための手段】請求項１の導電膜のパタ
ーン形成方法は、導電膜１４を形成する工程と、前記導
電膜１４とはエッチング特性が異なる第１の膜２６を前
記導電膜１４上でパターニングする工程と、前記導電膜
１４及び前記第１の膜２６とはエッチング特性が異なる
第２の膜２７を前記導電膜１４及び前記第１の膜２６上
に形成する工程と、前記第２の膜２７とはエッチング特
性が異なる平坦化膜３１を前記第２の膜２７上に形成す
る工程と、前記第２の膜２７の一部が露出するまで前記
平坦化膜３１をエッチバックする工程と、露出した前記
第２の膜２７を等方性エッチングする工程と、前記等方
性エッチングの後に、前記第１の膜２６と前記平坦化膜
３１とをマスクにして前記導電膜１４をエッチングする
工程とを有している。According to a first aspect of the present invention, there is provided a conductive film pattern forming method, which comprises a step of forming a conductive film and a first film having a different etching characteristic from the conductive film. Patterning above, forming a second film 27 having etching characteristics different from those of the conductive film 14 and the first film 26 on the conductive film 14 and the first film 26, and Forming a flattening film 31 having a different etching characteristic from that of the second film 27 on the second film 27, and etching back the flattening film 31 until a part of the second film 27 is exposed. And a step of isotropically etching the exposed second film 27. After the isotropic etching, the conductive film 14 is formed by using the first film 26 and the planarization film 31 as a mask. Has a step of etching .
【００１１】請求項２の不揮発性半導体記憶装置は、請
求項１の方法でパターニングした導電膜１４を浮遊ゲー
トとしている。According to a second aspect of the non-volatile semiconductor memory device, the conductive film 14 patterned by the method of the first aspect is used as a floating gate.
【００１２】[0012]
【作用】請求項１の導電膜のパターン形成方法では、第
２の膜２７を薄く形成することによって、第１の膜２６
の側部を第２の膜２７で側壁状に覆うことができる。こ
のため、平坦化膜３１から露出した第２の膜２７を等方
性エッチングすることによって、第１の膜２６の側部を
覆っている側壁状の第２の膜２７が除去され、第１の膜
２６と平坦化膜３１との間に第２の膜２７の膜厚を幅と
するスペースが形成される。In the conductive film pattern forming method according to the first aspect of the present invention, the first film 26 is formed by thinly forming the second film 27.
The side portions of the can be covered with the second film 27 in a side wall shape. Therefore, the second film 27 exposed from the flattening film 31 is isotropically etched to remove the sidewall-shaped second film 27 covering the side portions of the first film 26, and the first film 26 is removed. A space having a width equal to the thickness of the second film 27 is formed between the film 26 and the flattening film 31.
【００１３】従って、第２の膜２７を等方性エッチング
した後に第１の膜２６と平坦化膜３１とをマスクにして
導電膜１４をエッチングすることによって、第２の膜２
７の膜厚のスペース幅２５で、つまり写真製版技術の限
界よりも狭いスペース幅２５で、導電膜１４同士を分離
することができる。Therefore, after the second film 27 is isotropically etched, the conductive film 14 is etched by using the first film 26 and the flattening film 31 as a mask.
The conductive films 14 can be separated from each other by the space width 25 of the film thickness of 7, that is, the space width 25 narrower than the limit of the photolithography technique.
【００１４】請求項２の不揮発性半導体記憶装置では、
写真製版技術の限界よりも狭いスペース幅２５で浮遊ゲ
ート１４同士が分離されているので、メモリセル面積を
小さくすることができる。According to another aspect of the nonvolatile semiconductor memory device of the present invention,
Since the floating gates 14 are separated by the space width 25 which is narrower than the limit of the photolithography technology, the memory cell area can be reduced.
【００１５】[0015]
【実施例】以下、浮遊ゲートを有する不揮発性半導体記
憶装置の製造に適用した本願の発明の一実施例を、図
１、２を参照しながら説明する。なお、図３に示した一
従来例と対応する構成部分には、同一の符号を付してあ
る。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention applied to the manufacture of a nonvolatile semiconductor memory device having a floating gate will be described below with reference to FIGS. The components corresponding to those of the conventional example shown in FIG. 3 are designated by the same reference numerals.
【００１６】本実施例でも、図１（ａ）に示す様に、多
結晶Ｓｉ膜１４を全面に堆積させるまでは、図３に示し
た一従来例と実質的に同様の工程を実行する。しかし本
実施例では、その後、ＳｉＮ膜２６を０．５μｍの膜厚
に全面に堆積させ、制御ゲートの延在方向で浮遊ゲート
間に設けるべきスペースの片側のエッジとＳｉＮ膜２６
のエッジとが一致する様に、ＳｉＮ膜２６をパターニン
グする。Also in this embodiment, as shown in FIG. 1A, substantially the same steps as those of the conventional example shown in FIG. 3 are executed until the polycrystalline Si film 14 is deposited on the entire surface. However, in this embodiment, thereafter, the SiN film 26 is deposited to a thickness of 0.5 μm on the entire surface, and one edge of the space to be provided between the floating gates in the extending direction of the control gate and the SiN film 26.
The SiN film 26 is patterned so that the edges thereof coincide with each other.
【００１７】その後、例えばＴＥＯＳガスを原料とする
減圧ＣＶＤ法で、段差被覆性の良いＳｉＯ2 膜２７を
０．３μｍの膜厚に全面に堆積させる。この様にＳｉＯ
2 膜２７の膜厚が薄く且つ段差被覆性が良いので、図１
（ａ）に示す様に、ＳｉＮ膜２６の側部をＳｉＯ2 膜２
７が側壁状に覆う。After that, a SiO 2 film 27 having good step coverage is deposited on the entire surface to a thickness of 0.3 μm by a low pressure CVD method using, for example, TEOS gas as a raw material. In this way SiO
Since the film thickness of the two films 27 is thin and the step coverage is good,
As shown in (a), the side portion of the SiN film 26 is covered with the SiO 2 film 2
7 covers the side wall.
【００１８】次に、図１（ｂ）に示す様に、平坦性の優
れた薄膜として例えばフォトレジスト３１を１μｍの膜
厚に平坦に塗布し、図１（ｃ）に示す様に、ＳｉＯ2 膜
２７の一部が露出するまでフォトレジスト３１をエッチ
バックする。Next, as shown in FIG. 1 (b), a thin film having excellent flatness, for example, a photoresist 31 having a film thickness of 1 μm is coated evenly, and SiO 2 is formed as shown in FIG. 1 (c). The photoresist 31 is etched back until a part of the film 27 is exposed.
【００１９】この時、エッチバックの速度やフォトレジ
スト３１の膜厚のバラツキによってＳｉＯ2 膜２７の露
出の度合いにバラツキが生じるが、ＳｉＯ2 膜２７のう
ちでＳｉＮ膜２６の側部を側壁状に覆っている部分が露
出し且つ多結晶Ｓｉ膜１４の上面に堆積している部分が
露出しない程度に、フォトレジスト３１が残ればよい。
従って、フォトレジスト３１のエッチバックのある程度
のバラツキは吸収することができる。[0019] At this time, variations in the degree of exposure of the SiO 2 film 27 by variation in the thickness of the etch-back speed and the photoresist 31, the side walls form the sides of the SiN film 26 among the SiO 2 film 27 It is sufficient that the photoresist 31 remains to such an extent that the portion covered with the photoresist is exposed and the portion deposited on the upper surface of the polycrystalline Si film 14 is not exposed.
Therefore, a certain amount of etch back of the photoresist 31 can be absorbed.
【００２０】次に、ＳｉＯ2 に対する公知の等方性エッ
チング技術、例えばＨＦ溶液を用いたウエットエッチン
グ法によって、図１（ｄ）に示す様に、フォトレジスト
３１から露出しているＳｉＯ2 膜２７をエッチングす
る。Next, as shown in FIG. 1D, the SiO 2 film 27 exposed from the photoresist 31 is formed by a known isotropic etching technique for SiO 2 , for example, a wet etching method using an HF solution. To etch.
【００２１】このエッチングは、ＳｉＮ膜２６とフォト
レジスト３１との間に開口３２を形成し且つこの開口３
２から多結晶Ｓｉ膜１４の表面が露出するまで十分に行
う。開口３２は、本実施例では、下地が高いＳｉＯ2 膜
１２上に形成されるので、図３（ａ）に示した開口１５
と寸法は異なるが類似のパターンになる。This etching forms an opening 32 between the SiN film 26 and the photoresist 31 and the opening 3
Sufficiently performed from 2 to the surface of the polycrystalline Si film 14 is exposed. Since the opening 32 is formed on the SiO 2 film 12 having a high base in this embodiment, the opening 15 shown in FIG.
And the dimensions are different, but the pattern is similar.
【００２２】次に、公知のドライエッチング技術で、開
口３２を通して、つまりＳｉＮ膜２６とフォトレジスト
３１とをマスクにして、図２（ａ）に示す様に、多結晶
Ｓｉ膜１４を異方性エッチングする。Next, as shown in FIG. 2A, the polycrystalline Si film 14 is anisotropically anisotropically etched through the opening 32, that is, using the SiN film 26 and the photoresist 31 as a mask by a known dry etching technique. Etching.
【００２３】次に、公知の技術でフォトレジスト３１、
ＳｉＯ2 膜２７及びＳｉＮ膜２６を順次に除去して、図
２（ｂ）に示す様に、多結晶Ｓｉ膜１４の全体を露出さ
せる。その後は、図３に示した一従来例と同様な工程を
実行して、図２（ｃ）に示す様に多結晶Ｓｉ膜１７から
成る制御ゲートの形成までを行い、更にビット線である
Ａｌ配線２４（図３（ａ）参照）等を形成する。Next, the photoresist 31,
The SiO 2 film 27 and the SiN film 26 are sequentially removed to expose the entire polycrystalline Si film 14 as shown in FIG. 2B. After that, the same steps as those of the conventional example shown in FIG. 3 are performed until the control gate formed of the polycrystalline Si film 17 is formed as shown in FIG. The wiring 24 (see FIG. 3A) and the like are formed.
【００２４】以上の様な本実施例では、図１（ｃ）から
も明らかな様に、ＳｉＯ2 膜２７のうちでＳｉＮ膜２６
の側部を側壁状に覆っている部分の幅がＳｉＯ2 膜２７
の膜厚に等しく、また図２（ａ）からも明らかな様に、
この幅が多結晶Ｓｉ膜１４同士のスペース幅２５にな
る。In this embodiment as described above, as is clear from FIG. 1C, the SiN film 26 among the SiO 2 films 27 is formed.
The width of the side wall of the SiO 2 film 27
Is equal to the film thickness of, and as is clear from FIG. 2 (a),
This width becomes the space width 25 between the polycrystalline Si films 14.
【００２５】そして、ＳｉＯ2 膜２７の膜厚が既述の様
に０．３μｍであるので、スペース幅２５も０．３μｍ
になる。従って、スペース幅２５が０．６μｍである図
３に示した一従来例に比べて、本実施例ではメモリセル
の一辺の長さを０．３μｍだけ短くすることができる。Since the thickness of the SiO 2 film 27 is 0.3 μm as described above, the space width 25 is also 0.3 μm.
become. Therefore, in this embodiment, the length of one side of the memory cell can be shortened by 0.3 μm as compared with the conventional example shown in FIG. 3 in which the space width 25 is 0.6 μm.
【００２６】[0026]
【発明の効果】請求項１の導電膜のパターン形成方法で
は、写真製版技術の限界よりも狭いスペース幅で導電膜
同士を分離することができるので、微細なスペース幅で
導電膜のパターンを形成することができる。According to the conductive film pattern forming method of the present invention, the conductive films can be separated from each other with a space width narrower than the limit of the photolithography technique, so that the conductive film pattern can be formed with a fine space width. can do.
【００２７】請求項２の不揮発性半導体記憶装置では、
写真製版技術の限界よりも狭いスペース幅で浮遊ゲート
同士が分離されており、メモリセル面積を小さくするこ
とができるので、高集積化が可能である。According to another aspect of the non-volatile semiconductor memory device of the present invention,
The floating gates are separated from each other with a space width narrower than the limit of the photoengraving technique, and the memory cell area can be reduced, so that high integration is possible.
【図１】本願の発明の一実施例の前半の工程を順次に示
す側断面図である。FIG. 1 is a side sectional view sequentially showing a first half process of an embodiment of the present invention.
【図２】一実施例の後半の工程を順次に示す側断面図で
ある。FIG. 2 is a side sectional view sequentially showing the latter half of the steps in one embodiment.
【図３】本願の発明の一従来例によって製造した不揮発
性半導体記憶装置を示しており、（ａ）は平面図、
（ｂ）は（ａ）のｂ−ｂ線に沿う位置の側断面図、
（ｃ）は（ａ）のｃ−ｃ線に沿う位置の側断面図であ
る。FIG. 3 shows a nonvolatile semiconductor memory device manufactured by a conventional example of the present invention, in which (a) is a plan view,
(B) is a side sectional view taken along the line bb in (a),
(C) is a side sectional view of a position along the line cc of (a).
１４ 多結晶Ｓｉ膜 ２５ スペース幅 ２６ ＳｉＮ膜 ２７ ＳｉＯ2 膜 ３１ フォトレジスト14 polycrystalline Si film 25 space width 26 SiN film 27 SiO 2 film 31 photoresist
Claims (2)
導電膜上でパターニングする工程と、 前記導電膜及び前記第１の膜とはエッチング特性が異な
る第２の膜を前記導電膜及び前記第１の膜上に形成する
工程と、 前記第２の膜とはエッチング特性が異なる平坦化膜を前
記第２の膜上に形成する工程と、 前記第２の膜の一部が露出するまで前記平坦化膜をエッ
チバックする工程と、 露出した前記第２の膜を等方性エッチングする工程と、 前記等方性エッチングの後に、前記第１の膜と前記平坦
化膜とをマスクにして前記導電膜をエッチングする工程
とを有する導電膜のパターン形成方法。1. A step of forming a conductive film, a step of patterning a first film having etching characteristics different from those of the conductive film on the conductive film, and a step of etching characteristics of the conductive film and the first film. Forming a second film on the conductive film and the first film having a different thickness, and forming a planarizing film having a different etching characteristic from the second film on the second film, Etching back the planarization film until a part of the second film is exposed; isotropically etching the exposed second film; and after the isotropic etching, the first film And a method of etching the conductive film using the flattening film as a mask.
を浮遊ゲートとする不揮発性半導体記憶装置。2. A non-volatile semiconductor memory device comprising a patterned conductive film according to claim 1 as a floating gate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4131576A JPH05304302A (en) | 1992-04-24 | 1992-04-24 | Conductive film patterning method and fabrication of nonvolatile semiconductor memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4131576A JPH05304302A (en) | 1992-04-24 | 1992-04-24 | Conductive film patterning method and fabrication of nonvolatile semiconductor memory |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05304302A true JPH05304302A (en) | 1993-11-16 |
Family
ID=15061287
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4131576A Pending JPH05304302A (en) | 1992-04-24 | 1992-04-24 | Conductive film patterning method and fabrication of nonvolatile semiconductor memory |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05304302A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7026683B2 (en) | 2003-04-11 | 2006-04-11 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory device having grooves isolating the floating electrodes of memory cells and method of manufacturing the nonvolatile semiconductor memory device |
-
1992
- 1992-04-24 JP JP4131576A patent/JPH05304302A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7026683B2 (en) | 2003-04-11 | 2006-04-11 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory device having grooves isolating the floating electrodes of memory cells and method of manufacturing the nonvolatile semiconductor memory device |
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