JP2007081106A - Nonvolatile semiconductor memory device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the surface area of a nonvolatile memory cell by suppressing characteristic variations caused by misalignment in the memory cell having a charge accumulator located at a side wall of a gate electrode. <P>SOLUTION: A memory cell comprises a gate insulating film 5 formed on a semiconductor substrate 2, a gate electrode 6 formed on the gate insulating film 5, charge accumulators 7 formed at both side walls of the gate electrodes 6 in a row direction, a channel region 3 positioned below the gate electrode 6 and the charge accumulator 7, and two diffusion layer regions 4 as diffusion layers buried in the both side surfaces of the semiconductor substrate 2 in a row direction of the channel regions 3. The gate electrodes 6 of two memory cells adjacent in the row direction form gate electrode wiring lines 6a which are passed above the two diffusion layer regions 4 and the two charge accumulators 7 interconnected each other, and extended in the row direction. The two diffusion layer regions 4 are positioned under the gate electrode wiring lines 6a, and the diffusion layer regions 4 of two memory cells adjacent in a column direction are interconnected to form buried diffusion wiring lines 4a extended in the columnar direction. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a non-volatile semiconductor memory device, and more specifically, a non-volatile semiconductor memory device including a non-volatile memory cell having a MOSFET structure having a charge storage portion capable of holding a charge on a side wall portion of a gate electrode, and , And its manufacturing method.

  In recent years, a further increase in capacity has been demanded in a nonvolatile semiconductor memory device including a nonvolatile memory cell by threshold voltage control of a transistor typified by a flash memory. As means for realizing such a request, there are mainly the following two methods. One is a method of storing quaternary data per transistor by controlling the amount of charge stored in a charge storage layer such as a floating gate and providing four or more threshold voltage control regions of the transistor. The other is a method of substantially increasing the storage capacity per transistor by physically providing a plurality of charge storage layers in one transistor. For the latter, two types of structures are currently devised. One is, for example, a three-layer structure of ONO (silicon oxide film-silicon nitride film-silicon oxide film) as a gate insulating film as shown in Patent Document 1 below, and is formed at both ends of the silicon nitride film. A storage capacity of 2 bits per transistor is realized by locally accumulating electric charges in the vicinity of the first and second diffusion regions located. The other is that, as shown in Patent Document 2 and Patent Document 3 below, two bits are stored per transistor by accumulating charges independently on the side walls located on both sides of the gate electrode of the transistor. The capacity is realized. The former has a simple device structure, but two charge storage regions exist in the same continuous film, and therefore there is a problem that it becomes difficult to separate the charge storage regions during miniaturization. On the other hand, the latter is advantageous for miniaturization because the charge storage region is previously separated on both sides of the gate electrode.

JP-T-2001-552290 International Publication No. 03/044868 Pamphlet JP 2003-332474 A

  FIG. 30 is a schematic cross-sectional view of the sidewall charge storage type nonvolatile memory cell disclosed in Patent Document 2 and Patent Document 3, and FIG. 31 is a plan view when the nonvolatile memory cells are arranged in an array. , Respectively. In order to arrange memory cells having an element structure as shown in FIG. 30 in as high density as possible in an array, as shown in FIG. 31, a plurality of columns extend in the vertical direction and each column in the horizontal direction. The gate electrodes 101 and the electric charge are passed through the diffusion regions 103 having a pattern in which the connection portions 103a connecting each other are alternately arranged in the vertical direction so as to pass between the connection portions 103a arranged in the vertical direction. A structure in which a side wall portion serving as the storage portion 102 extends in the lateral direction is common. At this time, as shown in FIGS. 32A and 32B, the corners are rounded at the boundary between the element isolation region 106 and the diffusion region 103, so that the charge accumulation unit 102 and the diffusion region 103 that cross the region directly overlap each other. The area changes due to a slight misalignment. Such misalignment causes a difference in the width of the channel under the charge storage portion on both sides of the gate electrode, and appears as a characteristic difference between the two bits.

In addition, in the planar structure shown in FIG. 31, the memory cell area per transistor (ie, 2 bits) is at least 10F ² (F is defined by the design rule of the semiconductor manufacturing process used for forming the nonvolatile memory cell). Although the minimum processing dimension is required, further reduction of the memory cell area is required to increase the capacity.

  The present invention has been made in view of the above-described problems, and an object of the present invention is to provide a nonvolatile semiconductor memory including a memory cell in which a charge storage portion is disposed on at least one of both side walls of a gate electrode. In the device, characteristic variation due to misalignment is suppressed, and the memory cell area is reduced.

  In order to achieve the above object, a nonvolatile semiconductor memory device according to the present invention is a nonvolatile semiconductor memory device including a memory cell array in which a plurality of nonvolatile memory cells are arranged in two directions orthogonal to each other. A nonvolatile memory cell is provided on at least one of a semiconductor substrate, a gate insulating film formed on the semiconductor substrate, a gate electrode formed on the gate insulating film, and both side walls of the gate electrode. A charge storage portion capable of storing the formed charge; a channel region located below the gate electrode and the charge storage portion; and the channel formed of a buried diffusion layer on the surface of the semiconductor substrate on both sides of the channel region. A diffusion layer region having a conductivity type opposite to that of the region, wherein the both side wall portions are in a first direction out of the two directions orthogonal to the gate electrode. Each of the two diffusion layer regions is formed in the first direction with respect to the channel region, and the gate electrodes of the two nonvolatile memory cells adjacent to the first direction are Connected to a common gate electrode wiring extending in the first direction, each of the two diffusion layer regions is formed below the gate electrode wiring, and the two diffusion layer regions of the nonvolatile memory cell are , And respectively connected to two embedded wirings extending in a second direction orthogonal to the first direction.

  According to the nonvolatile semiconductor memory device having the above characteristics, unlike the conventional structure, the first direction is the same in the extending direction of the gate electrode and the arrangement direction of the two diffusion layer regions that become the channel region, the drain electrode, and the source electrode. Therefore, the width of the channel region (that is, the length in the second direction) is not defined by the pattern width of the diffusion layer region, but the pattern width of each of the gate electrode and the charge storage portion (that is, the first direction). Therefore, the variation in channel width below the charge storage portion due to misalignment, which has been a problem in the past, is eliminated.

  Further, since the diffusion layer region is connected to the buried wiring extending in the second direction, it is not necessary to connect the diffusion layer region to the upper metal wiring for each memory cell, and the repetition pitch of the memory cell is set to the first pitch. In addition, the memory cell area can be reduced by reducing the size in both the second and second directions.

  Furthermore, in the nonvolatile semiconductor memory device having the above characteristics, it is preferable that the embedded wiring is a diffusion layer wiring formed by an embedded diffusion layer on the semiconductor substrate. As a result, the diffusion layer region serving as the drain or source electrode of the memory cell and the buried wiring are formed by the same buried diffusion layer, so that the memory cell structure is simplified and the memory cell area can be reduced.

  Furthermore, in the nonvolatile semiconductor memory device having the above characteristics, it is preferable that the charge storage unit is electrically insulated from the gate electrode, the gate electrode wiring, and the semiconductor substrate by an insulating film. Thereby, when the charge storage portion is formed of an insulator, the storage state of the charge stored in the charge storage portion formed in the insulator becomes better, and the charge storage portion is formed of a conductor. If this is the case, the charge stored in the charge storage portion can be prevented from leaking to the gate electrode, the gate electrode wiring, and the semiconductor substrate, a good charge storage state can be secured, and data as a nonvolatile memory cell can be secured. Holding characteristics are improved.

  Furthermore, in the nonvolatile semiconductor memory device having the above characteristics, it is preferable that the charge storage portion is formed in a flat plate shape parallel to the surface of the semiconductor substrate.

  Furthermore, in the nonvolatile semiconductor memory device having the above characteristics, it is preferable that the charge storage portion is formed of a silicon nitride film.

  Furthermore, in the nonvolatile semiconductor memory device having the above-described characteristics, the gate electrode wiring is provided for each dimension twice as large as a minimum processing dimension defined by a design rule of a semiconductor manufacturing process used for forming the nonvolatile memory cell. It is preferable that a plurality of embedded wirings are arranged in the second direction, and a plurality of the embedded wirings are arranged in the first direction every three times the minimum processing dimension.

  Furthermore, a method for manufacturing a nonvolatile semiconductor memory device according to the present invention is a method for manufacturing a nonvolatile semiconductor memory device having the above characteristics, wherein the gate insulating film and a dummy gate electrode layer are sequentially formed on the semiconductor substrate. Processing the gate insulating film and the dummy gate electrode layer into a stripe shape extending in the second direction to form a dummy gate electrode having the gate insulating film; and both sides of the dummy gate electrode The step of forming the charge storage portion on the wall portion, and the diffusion layer region and the buried wiring by impurity implantation on the surface of the semiconductor substrate in the region sandwiched between the dummy gate electrodes provided with the charge storage portion Forming a diffusion region to be formed, and filling a region sandwiched between the dummy gate electrodes with an insulator, and then planarizing the insulator to form a top of the dummy gate electrode. Exposing the dummy gate electrode; depositing a gate electrode material on the entire surface including the region from which the dummy gate electrode has been removed; and removing the gate electrode material in the first direction. The first feature is to have at least a step of forming the gate electrode and the gate electrode wiring by processing into a stripe shape extending in a straight line.

  Furthermore, a method for manufacturing a nonvolatile semiconductor memory device according to the present invention is a method for manufacturing a nonvolatile semiconductor memory device having the above characteristics, wherein a first insulating film, a charge storage portion film, and a second insulation are formed on the semiconductor substrate. A film and a dummy gate electrode layer are sequentially formed, and the first insulating film, the charge storage portion film, the second insulating film, and the dummy gate electrode layer are processed into stripes extending in the second direction. Forming a dummy gate electrode including the first insulating film, the charge storage portion film, and the second insulating film; and implanting impurities into a surface of the semiconductor substrate in a region sandwiched between the dummy gate electrodes The step of forming the diffusion layer region and the diffusion region to be the buried wiring, and filling the region sandwiched between the dummy gate electrodes with an insulator, and then planarizing the insulator to form the dummy gate electrode Top A step of exposing; a step of removing the dummy gate electrode; and removing a central portion of the charge storage portion film existing at a bottom portion of a groove portion formed by removing the dummy gate electrode, to thereby form the charge storage portion film Are processed into two charge storage portions separated in the first direction, the gate insulating film is formed in a region between the two separated charge storage portions, and the gate insulating film is formed on the gate insulating film. A step of depositing a gate electrode material on the entire surface, and a step of processing the gate electrode material into a stripe shape extending in the first direction to form the gate electrode and the gate electrode wiring. It has the 2nd characteristic to have at least.

  According to the method of manufacturing a nonvolatile semiconductor memory device having any one of the above characteristics, in the nonvolatile memory cell of the nonvolatile semiconductor memory device, in the extension direction of the gate electrode, two diffusions that become the channel region, the drain electrode, and the source electrode The arrangement directions of the layer regions are all the same first direction, and the two diffusion layer regions and the buried wiring are both formed by buried diffusion extending in the second direction. As a result, the width of the channel region (that is, the length in the second direction) is not defined by the pattern width of the diffusion layer region, but the respective pattern widths (that is, the second direction) of the gate electrode and the charge storage portion. The variation in channel width below the charge storage area due to misalignment, which was a problem in the past, has been eliminated, and the diffusion layer region is connected to the upper metal wiring for each memory cell. Thus, the memory cell repetition pitch can be reduced in both the first and second directions, and the memory cell area can be reduced.

  Embodiments of a nonvolatile semiconductor memory device and a method for manufacturing the same according to the present invention (hereinafter, abbreviated as “device of the present invention” and “method of the present invention” as appropriate) will be described below with reference to the drawings.

  1 and 2 show a basic configuration of the nonvolatile memory cell 1 of the device of the present invention. FIG. 1 shows memory cells 1 in a row direction (corresponding to a first direction of two directions orthogonal to each other in the horizontal direction in FIG. 1) and a column direction (vertical direction in FIG. 1 and two directions orthogonal to each other). Schematically showing a relationship between one memory cell and a memory cell adjacent in the row direction and the column direction around the memory cell array in a state in which a plurality of memory cells are arranged in the same direction (corresponding to the first direction). It is a top view. A portion surrounded by a broken line in FIG. 1 indicates a cell region of one memory cell. FIG. 2 is a schematic cross-sectional view showing a schematic cross-sectional structure of the main part of the memory cell array in a cross section perpendicular to the substrate indicated by the A-A ′ line in FIG. 1. A portion surrounded by a broken line in FIG. 2 indicates a cell region of one memory cell 1, and a horizontal direction in FIG. 2 corresponds to a row direction.

  As shown in FIGS. 1 and 2, the nonvolatile memory cell 1 includes a gate insulating film 5 formed on the semiconductor substrate 2, a gate electrode 6 formed on the gate insulating film 5, and a row of the gate electrodes 6. Charge storage portion 7 capable of storing charges formed on both side walls in the direction, channel region 3 located below gate electrode 6 and charge storage portion 7, and semiconductor substrate 2 on both sides in the row direction of channel region 3 Two diffusion layer regions 4 functioning as a drain electrode and a source electrode having a conductivity type opposite to that of the channel region 3 formed of a buried diffusion layer on the surface of the MOSFET are configured, and configured as a memory cell having a MOSFET structure. The memory cell configuration is basically the same as that of the conventional sidewall charge storage nonvolatile memory cell shown in FIGS. 30 and 31 except that the diffusion layer region 4 is a buried diffusion layer.

  Further, in the nonvolatile memory cell 1 of the device of the present invention, the gate electrodes 6 of two memory cells adjacent in the row direction pass over the two diffusion layer regions 4 and the charge storage unit 7 and are connected to each other. A common gate electrode wiring 6a extending in the row direction is formed. Each of the two diffusion layer regions 4 is located below the gate electrode wiring 6a, and the diffusion layer regions 4 of two memory cells adjacent in the column direction are connected to each other and extend in the column direction. A buried diffusion wiring 4a is formed. The gate electrode wiring 6a is a word line, and each buried diffusion wiring 4a connected to the two diffusion layer regions 4 of one memory cell functions as a buried bit line and a buried source line. Here, the word line 6a extends in the row direction, and the embedded bit line 4a and the embedded source line 4a extend in the column direction orthogonal to the word line 6a.

  The semiconductor substrate 2 is not particularly limited as long as it is used in a semiconductor device, and is a silicon substrate, a compound semiconductor substrate such as GaAs or InGaAs, an SOI (silicon on insulator) substrate, or a multilayer SOI substrate. A substrate such as can be used. The semiconductor substrate 2 may have P-type and N-type conductivity types, and preferably has at least one first conductivity type (P-type or N-type) well region formed therein. In this case, the semiconductor substrate 2 in FIG. 2 becomes a well region. The impurity concentration in the semiconductor substrate and well region can be within the range known in the art. When an SOI substrate is used as the semiconductor substrate 2, a well region may be formed in the surface semiconductor layer, but a body region may be provided under the channel region.

  The gate insulating film 5 is not particularly limited as long as it is used in a normal semiconductor device. For example, an insulating film such as a silicon oxide film or a silicon nitride film, an aluminum oxide film, a titanium oxide film, or a tantalum oxide is used. A film, a high dielectric constant oxide thin film such as a hafnium oxide film, or a laminated film of these insulating films can be used. Usually, when a silicon substrate is used as the semiconductor substrate 2, it is preferable to use a silicon oxide film.

  The gate electrode 6 is not particularly limited as long as it is used in a normal semiconductor device, and a conductive film, for example, a metal such as polysilicon, copper or aluminum, or a high melting point such as tungsten, titanium, or tantalum. A silicide with a metal or a refractory metal can be used, and a laminated film of these may be used.

  The charge accumulating portion 7 has a film for accumulating charges separated from the surrounding conductor portions (gate electrode 6, gate electrode wiring 6a, diffusion layer region 4, buried diffusion wiring 4a, semiconductor substrate 2) by an insulating film 8. It is preferable that the charge leakage is suppressed and a sufficient data holding time can be obtained. Therefore, it is possible to rewrite the apparatus of the present invention at high speed, improve reliability, and secure a sufficient data holding time. Further, it is particularly preferable that the charge storage portion 7 is a silicon nitride film, and a silicon oxide film is used as an insulating film with a surrounding conductor. Since the silicon nitride film has many levels for trapping charges, a large memory window can be obtained.

  According to the memory cell configuration shown in FIGS. 1 and 2, the extending direction of the gate electrode 6 and the arrangement direction of the two diffusion layer regions 4 serving as the channel region 3, the drain electrode, and the source electrode are both in the same row direction. Therefore, the width of the channel region (that is, the length in the column direction) is not defined by the pattern width of the diffusion layer region 4, but the pattern width of each of the gate electrode 6 and the charge storage portion 7 (that is, in the column direction). In the side wall charge storage type memory cell, the channel width below the two charge storage units arranged in one memory cell varies between bits due to misalignment. The inconvenience that was supposed to be solved.

Further, according to the memory cell configuration shown in FIG. 1 and FIG. 2, when the minimum processing dimension defined by the design rule of the semiconductor manufacturing process is F, the repetition interval in the row direction of the memory cell, that is, the embedded diffusion repetition interval of the wiring pitch of the wiring 4a 3F, the column direction of the memory cell, that is, can the wiring pitch of the gate electrode wirings 6a to 2F, the memory cell size is 6F ² and can miniaturization, the chip size of the device of the present invention Contributes to downsizing.

<First Embodiment>
Next, a first embodiment of the method of the present invention will be described. Hereinafter, in the method of the present invention, a processing procedure for realizing the memory cell array of the device of the present invention using a normal silicon semiconductor process will be described with reference to the process cross-sectional views of FIGS. 3 to 13 show the same cross section as FIG.

  First, as shown in FIG. 3, a gate oxide film (gate insulation) is formed on a P-type well (semiconductor substrate) 12 formed on a P-type silicon substrate 11 by using a normal gate oxide film formation technique such as thermal oxidation. Film) 13 and then a silicon nitride film 14 is deposited by a known technique such as CVD. Thereafter, as shown in FIG. 4, the silicon nitride film 14 and the gate oxide film 13 are processed in a stripe shape in the column direction by reactive ion etching or the like. At this time, the silicon nitride film 14 becomes a dummy gate to be removed later when the gate electrode is formed.

  Next, as shown in FIG. 5, a silicon oxide film 15 and a silicon nitride film 16 serving as a charge storage portion are sequentially deposited by a CVD method or the like. The silicon oxide film 15 is used to insulate the surrounding gate electrode and the silicon substrate 12 from the charge storage portion, and usually has a thickness of about 3 nm to 30 nm.

  Next, as shown in FIG. 6, a p-type charge storage portion lower channel region 17 is formed by impurity implantation. The impurity implantation of the channel region 17 is for controlling the threshold voltage of the region, and is adjusted for the impurity concentration of the P-type well 12 in the initial state. Therefore, the ion species to be implanted are N-type and P-type. Either of these cases is possible.

  Next, as shown in FIG. 7, a silicon oxide film 18 is deposited by CVD or the like. Thereafter, as shown in FIG. 8, etching back is performed by reactive ion etching or the like until the top of the dummy gate (silicon nitride film) 14 is exposed. As a result, the silicon nitride film 16 serving as a charge storage portion is formed in a sidewall shape between the silicon oxide films 15 and 18 on both side walls of the dummy gate 14 which will later become a gate electrode. The sidewall portions 15, 16, and 18 extend in the column direction together with the dummy gate 14.

  Next, as shown in FIG. 9, N + impurity implantation is performed to form an N type diffusion layer region 19 having a conductivity type opposite to that of the channel region 17. Note that the diffusion layer region 19 is formed as a buried diffusion wiring 19 extending in the column direction because it is formed in a groove portion sandwiched between the sidewall portions 15, 16, and 18.

  Next, as shown in FIG. 10, a silicon oxide film 20 is deposited by CVD or the like. Subsequently, as shown in FIG. 11, CMP (Chemical Mechanical Polish) or a planarization process using a dry etching technique or the like is performed. Then, the silicon oxide film 20 is planarized to expose the top of the dummy gate 14.

  Next, as shown in FIG. 12, a silicon nitride film (dummy gate) 14 is selectively removed using a wet etching technique such as phosphoric acid boil to form a groove structure for embedding the gate electrode. The groove is formed in a stripe shape extending in the column direction.

  Next, as shown in FIG. 13, polysilicon 21 (gate electrode material) to be a gate electrode and a gate electrode wiring is deposited, and the gate electrode wiring functioning as a word line functions as a buried bit line or a buried source line. The polysilicon 21 is processed into a stripe shape by dry etching or the like so as to be formed in a row direction (left and right direction in the figure) orthogonal to the buried diffusion wiring 19.

  In the present embodiment, since the silicon nitride film 16 serving as a charge storage portion is formed of an insulator, it is not necessary to separately separate memory cells adjacent in the column direction. The sidewall portions 15, 16, and 18 are not processed, extend in the column direction, and continue to the same sidewall portions 15, 16, and 18 of memory cells adjacent in the column direction. Although not shown, the gap in the column direction of the gate electrode and the gate electrode wiring after the processing of the polysilicon 21 is filled with an interlayer insulating film deposited on the gate electrode and the gate electrode wiring. A gate electrode and a gate electrode wiring are electrically insulated between adjacent memory cells.

  Through the above processing procedures, the memory cell array of the device of the present invention schematically shown in FIGS. 1 and 2 is specifically formed.

Second Embodiment
Next, a second embodiment of the method of the present invention will be described. Hereinafter, in the method of the present invention, a processing procedure for realizing the memory cell array of the device of the present invention using a normal silicon semiconductor process will be described with reference to the process cross-sectional views of FIGS. 14 to 29 show the same cross sections as those in FIG.

  First, as shown in FIG. 14, a silicon oxide film 25 / silicon nitride film 24 / silicon oxide film 23 (ONO film) are stacked on a P-type well (semiconductor substrate) 12 formed on a P-type silicon substrate 11. The film is deposited using a known technique such as a CVD method. Each film thickness at this time is about 3 nm to 30 nm. The silicon nitride film 24 is a charge storage portion film that is later processed as a charge storage portion. Thereafter, a silicon nitride film 26 is deposited on the ONO film to a thickness of about 100 nm to 500 nm using a known technique. The silicon nitride film 26 contributes as a dummy structure that is removed when a trench structure for forming a charge storage portion and a gate electrode is formed later. Thereby, as shown in FIG. 14, a four-layered film of silicon nitride film 26 / silicon oxide film 25 / silicon nitride film 24 / silicon oxide film 23 is formed on the P-type well 12.

  Next, as shown in FIG. 15, the four-layered laminated films 23 to 26 are removed in a stripe shape along the column direction by using reactive ion etching or the like, and a four-layered stripe shape extending in the column direction. Films 23 to 26 are formed.

  Next, as shown in FIG. 16, an insulating film 27 is deposited using a known technique such as a CVD method. The film thickness of the insulating film 27 is an element that determines the distance between the end portion of the diffusion layer region to be formed later and the end portion of the charge storage portion, and may be adjusted as necessary.

  After that, as shown in FIG. 17, the insulating film 27 is etched back by reactive ion etching or the like so that the insulating film 27 remains only on both side walls of the stripe-shaped four-layer laminated films 23 to 26. An insulating film 27 is formed. The sidewall-like insulating film 27 extends in the column direction together with the stripe-like four-layer laminated films 23 to 26.

  Next, as shown in FIG. 18, N + impurity implantation is performed to form an N type diffusion layer region 28 having a conductivity type opposite to that of the P type well 12. The diffusion layer region 28 is formed as a buried diffusion wiring 28 extending in the column direction because it is formed in a groove portion sandwiched between the sidewall-like insulating films 27.

  By the way, the sidewall-like insulating film 27 is for controlling the distance between the end portion of the diffusion layer region 28 and the end portion of the silicon nitride film 24 serving as the charge storage portion. If the thickness, that is, the deposited film thickness of the insulating film 27 may be adjusted, and if it is not necessary to control the distance between the end of the diffusion layer region 28 and the end of the charge storage unit, the step of depositing the insulating film 27 is performed. Can be omitted.

  Next, an interlayer insulating film 29 is deposited by a known deposition technique to a film thickness enough to fill the groove between the sidewall-like insulating films 27. After that, as shown in FIG. 19, the interlayer insulating film 29 is embedded in the trench using a surface flattening technique by CMP (Chemical Mechanical Polish).

  Next, as shown in FIG. 20, the silicon nitride film 26 is selectively removed using a wet etching technique such as phosphoric acid boil to form a groove structure in which the tops of the ONO films 23 to 25 are exposed on the bottom surface. To do. The grooves 30 of the groove structure are formed in a stripe shape extending in the column direction.

  Next, as shown in FIG. 21, channel implantation by impurity implantation is performed to form a P-type charge storage portion lower channel region 31. The impurity implantation of the channel region 31 is for controlling the threshold voltage of the region, and is adjusted for the impurity concentration of the P-type well 12 in the initial state. Therefore, the ion species to be implanted are N-type and P-type. Either of these cases is possible.

  Next, as shown in FIG. 22, a second interlayer insulating film 32 is deposited by a known technique. Also in this step, a deposition method with good step coverage such as a CVD method is desirable. Subsequently, as shown in FIG. 23, the second interlayer insulating film 32 and the silicon oxide film 25 are etched back by reactive ion etching or the like, and the interlayer insulating film 32 and the silicon oxide film are formed on the side walls of the trench 30. A side wall is formed by 25 and the surface of the silicon nitride film 24 is exposed at the bottom of the groove 30.

  Next, as shown in FIG. 24, an insulating film 33 is deposited by a known technique. Subsequently, as shown in FIG. 25, a P-type gate electrode lower channel region 34 is formed by impurity implantation into the groove 30 after the insulating film 33 is deposited. The impurity implantation of the gate electrode lower channel region 34 is for controlling the threshold voltage of the region, and the impurity concentration of the P-type well 12 which is in the initial state and the impurity of the charge storage portion lower channel region 31 formed earlier. Since the impurity concentration is adjusted to match the concentration, the ion species to be implanted can be either N-type or P-type.

  Thereafter, as shown in FIG. 26, the insulating film 33 is removed by etch back. Further, as shown in FIG. 27, the silicon nitride film 24 and the silicon oxide film 23 exposed at the bottom of the groove 30 are removed by reactive ion etching or the like. As a result, the silicon nitride film 24 and the silicon oxide film 23 are divided into two on both the left and right (row direction) sides of the bottom of the groove 30. The silicon nitride film 24 left on the side wall portion of the trench 30 becomes two charge storage portions per memory cell. The width of the charge storage portion is determined by the thickness of the side wall portion of the second interlayer insulating film 32, and the thickness may be adjusted as necessary. Note that the silicon nitride film 24 serving as the charge storage portion extends in the column direction along the side wall portion of the groove 30 with the upper and lower sides sandwiched by the silicon oxide films 23 and 25.

  Next, as shown in FIG. 28, an insulating film 35 is deposited, and a gate insulating film is formed so as to cover the bottom of the trench 30.

  Subsequently, as shown in FIG. 29, polysilicon 36 (gate electrode material) to be a gate electrode and a gate electrode wiring is deposited, and the gate electrode wiring functioning as a word line is embedded as a buried bit line or a buried source line. The polysilicon 36 is processed into a stripe shape by reactive ion etching or the like so as to be formed in a row direction (left and right direction in the drawing) orthogonal to the diffusion wiring 28.

  In the present embodiment, since the silicon nitride film 24 serving as a charge storage portion is formed of an insulator, it is not necessary to separately separate memory cells adjacent in the column direction. The ONO films 23, 24, and 25 on the side walls of the trench 30 are not processed, extend in the column direction, and continue to the ONO films 23, 24, and 25 on the same side wall of memory cells adjacent in the column direction. Although not shown, the gap in the column direction of the gate electrode and the gate electrode wiring after the processing of the polysilicon 36 is filled with an interlayer insulating film deposited on the gate electrode and the gate electrode wiring. A gate electrode and a gate electrode wiring are electrically insulated between adjacent memory cells.

  Through the above processing procedures, the memory cell array of the device of the present invention schematically shown in FIGS. 1 and 2 is specifically formed. In particular, in this embodiment, since the size of the charge storage portion can be formed smaller than that in the first embodiment, a high-performance nonvolatile memory cell with little characteristic variation can be realized.

  Next, another embodiment of the device of the present invention and the method of the present invention will be described.

  <1> In the first and second embodiments, silicon nitride films are used as the charge storage units 16 and 24. This is because it is easy to introduce into a mass production factory and is very preferable. However, the film configuration and material of the charge storage units 16 and 24 are not limited to the above embodiment. Furthermore, the charge storage portions 16 and 24 may be formed of a conductive film instead of an insulating film. In this case, since it is necessary to separate the charge storage units 16 and 24 that are continuous between the memory cells adjacent in the column direction for each memory cell, the separation is performed simultaneously with or after the processing of the gate electrode and the gate electrode wiring. The processing for this may be performed.

  <2> In the above-described embodiment (see FIGS. 1 and 2), the case where the charge storage unit 7 is formed on both side walls of the gate electrode 6 has been described. The present invention can also be applied to a memory cell structure that exists only on one side of the wall, and the improvement effect of suppressing variation in the channel width below the charge storage unit 7 according to the present invention is I can expect.

  <3> In the first and second embodiments, the case where the impurity implantation for the channel regions 17, 31, and 34 is performed has been described. However, each impurity implantation process is intended to adjust the threshold voltage in the region. If the adjustment is unnecessary, a part or all of the adjustment may be omitted.

  <4> In each of the above embodiments, the nonvolatile memory cell of the device of the present invention has been described as having a memory cell structure based on an N-channel MOSFET, but the memory cell may be a P-channel type, In that case, the processing procedure of each step is the same except that the conductivity type (P-type or N-type) of each part is reversed from that of the above embodiment and the impurity concentration and the like are changed.

  INDUSTRIAL APPLICABILITY The nonvolatile semiconductor memory device and the manufacturing method thereof according to the present invention can be used for the nonvolatile semiconductor memory device, and more specifically, a MOSFET having a charge storage unit capable of holding charges in the third wall portion of the gate electrode. By using the nonvolatile semiconductor memory device having the nonvolatile memory cell having the structure, characteristic variation due to misalignment can be suppressed and the memory cell area can be reduced.

1 is a schematic plan view schematically showing a basic configuration of a memory cell of a nonvolatile semiconductor memory device according to the present invention. 1 is a schematic cross-sectional view schematically showing a basic configuration of a memory cell of a nonvolatile semiconductor memory device according to the present invention. Process sectional drawing which shows the process sequence in 1st Embodiment of the manufacturing method of the non-volatile semiconductor memory device based on this invention Process sectional drawing which shows the process sequence in 1st Embodiment of the manufacturing method of the non-volatile semiconductor memory device based on this invention Process sectional drawing which shows the process sequence in 1st Embodiment of the manufacturing method of the non-volatile semiconductor memory device based on this invention Process sectional drawing which shows the process sequence in 1st Embodiment of the manufacturing method of the non-volatile semiconductor memory device based on this invention Process sectional drawing which shows the process sequence in 1st Embodiment of the manufacturing method of the non-volatile semiconductor memory device based on this invention Process sectional drawing which shows the process sequence in 1st Embodiment of the manufacturing method of the non-volatile semiconductor memory device based on this invention Process sectional drawing which shows the process sequence in 1st Embodiment of the manufacturing method of the non-volatile semiconductor memory device based on this invention Process sectional drawing which shows the process sequence in 1st Embodiment of the manufacturing method of the non-volatile semiconductor memory device based on this invention Process sectional drawing which shows the process sequence in 1st Embodiment of the manufacturing method of the non-volatile semiconductor memory device based on this invention Process sectional drawing which shows the process sequence in 1st Embodiment of the manufacturing method of the non-volatile semiconductor memory device based on this invention Process sectional drawing which shows the process sequence in 1st Embodiment of the manufacturing method of the non-volatile semiconductor memory device based on this invention Process sectional drawing which shows the process sequence in 2nd Embodiment of the manufacturing method of the non-volatile semiconductor memory device based on this invention Process sectional drawing which shows the process sequence in 2nd Embodiment of the manufacturing method of the non-volatile semiconductor memory device based on this invention Process sectional drawing which shows the process sequence in 2nd Embodiment of the manufacturing method of the non-volatile semiconductor memory device based on this invention Process sectional drawing which shows the process sequence in 2nd Embodiment of the manufacturing method of the non-volatile semiconductor memory device based on this invention Process sectional drawing which shows the process sequence in 2nd Embodiment of the manufacturing method of the non-volatile semiconductor memory device based on this invention Process sectional drawing which shows the process sequence in 2nd Embodiment of the manufacturing method of the non-volatile semiconductor memory device based on this invention Process sectional drawing which shows the process sequence in 2nd Embodiment of the manufacturing method of the non-volatile semiconductor memory device based on this invention Process sectional drawing which shows the process sequence in 2nd Embodiment of the manufacturing method of the non-volatile semiconductor memory device based on this invention Process sectional drawing which shows the process sequence in 2nd Embodiment of the manufacturing method of the non-volatile semiconductor memory device based on this invention Process sectional drawing which shows the process sequence in 2nd Embodiment of the manufacturing method of the non-volatile semiconductor memory device based on this invention Process sectional drawing which shows the process sequence in 2nd Embodiment of the manufacturing method of the non-volatile semiconductor memory device based on this invention Process sectional drawing which shows the process sequence in 2nd Embodiment of the manufacturing method of the non-volatile semiconductor memory device based on this invention Process sectional drawing which shows the process sequence in 2nd Embodiment of the manufacturing method of the non-volatile semiconductor memory device based on this invention Process sectional drawing which shows the process sequence in 2nd Embodiment of the manufacturing method of the non-volatile semiconductor memory device based on this invention Process sectional drawing which shows the process sequence in 2nd Embodiment of the manufacturing method of the non-volatile semiconductor memory device based on this invention Process sectional drawing which shows the process sequence in 2nd Embodiment of the manufacturing method of the non-volatile semiconductor memory device based on this invention Device sectional view schematically showing a schematic configuration of a conventional sidewall charge storage type nonvolatile memory cell The top view which shows typically the state which has arrange | positioned the conventional side wall charge storage type non-volatile memory cell in the array form A plan view for explaining how the channel width under the charge storage portion varies due to misalignment in a conventional sidewall charge storage type nonvolatile memory cell

Explanation of symbols

1: Nonvolatile memory cell 2: Semiconductor substrate 3: Channel region 4: Diffusion layer region 4a: Buried diffusion wiring (buried bit line, buried source line)
5: Gate insulating film 6: Gate electrode 6a: Gate electrode wiring (word line)
7: Charge storage unit 8: Insulating film 11: P-type silicon substrate 12: P-type well 13: Gate oxide film (gate insulating film)
14: Silicon nitride film (dummy gate)
15: Silicon oxide film 16: Silicon nitride film (charge storage part)
17: Lower channel region of charge storage portion 18: Silicon oxide film 19: Diffusion layer region (buried diffusion wiring)
20: Silicon oxide film 21: Polysilicon (gate electrode, gate electrode wiring)
23: Silicon oxide film 24: Silicon nitride film (charge storage part)
25: Silicon oxide film 26: Silicon nitride film 27: Insulating film 28: Diffusion layer region (buried diffusion wiring)
29: Interlayer insulating film 30: Groove 31: Lower channel region of charge storage portion 32: Second interlayer insulating film 33: Insulating film 34: Lower channel region of gate electrode 35: Insulating film (gate insulating film)
36: Polysilicon (gate electrode, gate electrode wiring)
DESCRIPTION OF SYMBOLS 101: Gate electrode 102: Charge storage part 103: Diffusion area | region 103a: Connection part 104: Silicon oxide film 105: Gate insulating film 106: Element isolation area | region 107: Contact w ', w2 ": Channel width under charge storage part

Claims (8)

A nonvolatile semiconductor memory device including a memory cell array in which a plurality of nonvolatile memory cells are arranged in two directions orthogonal to each other,
The nonvolatile memory cell includes a semiconductor substrate, a gate insulating film formed on the semiconductor substrate, a gate electrode formed on the gate insulating film, and at least one side of both side walls of the gate electrode A charge accumulation part capable of accumulating charges formed on the gate electrode, a channel region located below the charge accumulation part, and a buried diffusion layer formed on a surface of the semiconductor substrate on both sides of the channel area. Two diffusion layer regions having a conductivity type opposite to the channel region are provided,
The both side wall portions are located in a first direction of the two directions orthogonal to the gate electrode;
Each of the two diffusion layer regions is formed in the first direction with respect to the channel region;
The gate electrodes of two non-volatile memory cells adjacent in the first direction are connected to a common gate electrode wiring extending in the first direction;
Each of the two diffusion layer regions is formed below the gate electrode wiring,
The non-volatile semiconductor memory device, wherein the two diffusion layer regions of the non-volatile memory cell are respectively connected to two embedded wirings extending in a second direction orthogonal to the first direction.   The nonvolatile semiconductor memory device according to claim 1, wherein the embedded wiring is a diffusion layer wiring formed by an embedded diffusion layer in the semiconductor substrate.   The nonvolatile semiconductor memory device according to claim 1, wherein the charge storage portion is electrically insulated from the gate electrode, the gate electrode wiring, and the semiconductor substrate by an insulating film. .   4. The nonvolatile semiconductor memory device according to claim 1, wherein the charge storage portion is formed in a flat plate shape parallel to a surface of the semiconductor substrate.   The nonvolatile semiconductor memory device according to claim 1, wherein the charge storage unit is formed of a silicon nitride film. A plurality of the gate electrode wirings are arranged in the second direction for each dimension twice the minimum processing dimension defined by the design rule of the semiconductor manufacturing process used for forming the nonvolatile memory cell,
6. The nonvolatile semiconductor memory device according to claim 1, wherein a plurality of the embedded wirings are arranged in the first direction every three times the minimum processing dimension. . A method for manufacturing the nonvolatile semiconductor memory device according to claim 1,
The gate insulating film and the dummy gate electrode layer are sequentially formed on the semiconductor substrate, the gate insulating film and the dummy gate electrode layer are processed into a stripe shape extending in the second direction, and the gate insulating film is formed. Forming a dummy gate electrode with a film;
Forming the charge storage portion on both side walls of the dummy gate electrode;
Forming a diffusion layer region and a diffusion region serving as the buried wiring by impurity implantation on a surface of the semiconductor substrate in a region sandwiched between the dummy gate electrodes provided with the charge storage portion;
Filling the region sandwiched between the dummy gate electrodes with an insulator, and then planarizing the insulator to expose the top of the dummy gate electrode;
Removing the dummy gate electrode;
Depositing a gate electrode material on the entire surface including the region from which the dummy gate electrode has been removed;
Processing the gate electrode material into a stripe shape extending in the first direction to form the gate electrode and the gate electrode wiring;
A method for manufacturing a nonvolatile semiconductor memory device, comprising: A method for manufacturing the nonvolatile semiconductor memory device according to claim 1,
A first insulating film, a charge storage portion film, a second insulating film, and a dummy gate electrode layer are sequentially formed on the semiconductor substrate, and the first insulating film, the charge storage portion film, the second insulating film, and the dummy are formed. Processing a gate electrode layer into a stripe shape extending in the second direction to form a dummy gate electrode including the first insulating film, the charge storage portion film, and the second insulating film;
Forming a diffusion region to be the diffusion layer region and the buried wiring by impurity implantation on the surface of the semiconductor substrate in a region sandwiched between the dummy gate electrodes;
Filling the region sandwiched between the dummy gate electrodes with an insulator, and then planarizing the insulator to expose the top of the dummy gate electrode;
Removing the dummy gate electrode;
The two charge storage portions in which the charge storage portion film is separated in the first direction by removing the central portion of the charge storage portion film existing at the bottom of the groove portion formed by removing the dummy gate electrode The process of processing into
Forming the gate insulating film in a region between the two separated charge storage portions;
Depositing a gate electrode material on the entire surface including on the gate insulating film;
Processing the gate electrode material into a stripe shape extending in the first direction to form the gate electrode and the gate electrode wiring;
A method for manufacturing a nonvolatile semiconductor memory device, comprising: