JP2005277190A - Semiconductor memory and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor memory which suppresses variance in position of a carrier storage part so that the carrier storage part is always formed nearby both ends of a gate insulating film with small variance in position even if there is variance in drain voltage or impurity region structure due to variance of manufacturing stages. <P>SOLUTION: Provided are a 1st gate electrode 4 arranged on a 1st gate insulating film 3 where carriers are accumulated and a 2nd gate electrode 5, which is capacitively coupled with the 1st gate electrode, on both sides of it. When a write voltage is applied to one of the 1st and 2nd gate electrodes, a voltage is induced at the other gate electrode in a floating state and hot carriers are injected within a narrow range nearby the boundary to perform writing operation. Impurity regions 2-1 and 2-2 as a source and a drain are formed apart from the 1st gate electrode. The 1st gate electrode can be replaced with a high-dielectric film. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a nonvolatile semiconductor memory device and a method for manufacturing the same, and more particularly to a transistor that stores multiple bits in one transistor by accumulating carriers at both ends of a gate insulating film.

  A nonvolatile semiconductor memory device, for example, a SONOS (Silicon Oxide Nitride Oxide Silicon) memory for storing and storing carriers in a gate insulating film, stores carriers at both ends of the gate insulating film to constitute a one-transistor two-bit memory cell. Therefore, high integration is easy. In addition, the operating voltage is lower than that of a floating gate type memory such as a flash memory, which is suitable for use as a logic embedded memory. Furthermore, since the gate oxide film is thin, it is suitable for simultaneous production with logic. Because of such advantages, a nonvolatile semiconductor memory device that stores and stores carriers in the gate insulating film (hereinafter referred to as “MNOS (Metal Nitride Oxide Semiconductor) memory” including the case where the gate insulating film does not include a nitride film for convenience) Is considered important as a storage device for mixed logic.

  In the conventional MNOS memory, when the gate length of the transistor is shortened, both ends of the gate insulating film (both ends in the gate length direction) approach each other. Therefore, the carriers accumulated at both ends of the gate insulating film interfere with each other, thereby preventing the memory operation. Become stable. For this reason, miniaturization of elements has been limited. Hereinafter, this situation will be described with reference to a conventional example.

  FIG. 10 is a cross-sectional view of a conventional semiconductor memory device, showing a cross section of a transistor used in an MNOS memory. Referring to FIG. 10, the transistor includes a first gate insulating film 3 formed of three layers (ONO film) of a tunnel oxide film 3-1, a nitride film 3-2, and an oxide film 3-3 on an upper surface of a semiconductor substrate 1. A gate electrode 13 is provided via the. Two impurity regions 2-1 and 2-2 constituting a source and a drain are formed on the surface of the substrate 1 exposed on both outer sides of the gate electrode 13. The impurity regions 2-1 and 2-2 are formed in self-alignment with the gate electrode 13, and extend from the outside of the gate electrode to the vicinity of the end of the gate electrode 13 to the lower surface of the gate electrode 13.

  In the writing to the MNOS transistor, for example, the source voltage Vs and the drain voltage Vd are applied so that the impurity region 2-1 becomes the source and the impurity region 2-2 becomes the drain, and at the same time, the write voltage Vwr ( This is done by applying the same polarity as the drain voltage). At this time, carriers (for example, electrons) traveling in the channel are accelerated near the drain to generate hot carriers. The hot carriers pass through the tunnel oxide film 3-1 provided on the upper surface of the channel and are trapped in the trap level of the nitride film 3-2, and are stored as storage charges. The region where the carriers are stored (hereinafter referred to as “carrier storage portion”) is directly above the channel near the drain (impurity region 2-2) where hot carriers are generated, that is, the nitride film in the first gate insulating film 3. This is a portion (carrier accumulation unit 3B) close to the drain end of 3-2.

On the other hand, when the source voltage Vs and the drain voltage Vd are applied in the opposite direction so that the impurity region 2-1 is the drain and the impurity region 2-2 is the source, hot carriers are generated as the drain. Carriers are accumulated in the carrier accumulation unit 3A that occurs near the region 2-1 and is located at the end of the gate electrode 13 opposite to the carrier accumulation unit 3B. As described above, by selecting either one of the impurity regions 2-1 and 2-2 as a source and the other as a drain, one of the carrier accumulation portions 3A and 3B formed at both ends of the first gate insulating film 3 is selected. You can select and accumulate carriers. Accordingly, 2-bit information can be recorded with one transistor. (See Patent Document 1)
As described above, in the conventional MNOS transistor, hot carriers (for example, channel hot electrons) generated by accelerating carriers near the drain of the channel are injected into the gate insulating film to accumulate the carriers. Accordingly, the formation position of the accumulation portion corresponds to a region where carriers are accelerated and hot carriers are generated.

  The position where the carriers are accelerated strongly depends on the drain voltage and the structure of the drain region (for example, the junction position between the impurity region serving as the drain and the channel, or the impurity concentration of the impurity region and the substrate). For this reason, the carrier storage units 3A and 3B move according to the drain voltage and the structure of the drain region. As a result, due to variations in the manufacturing process of the semiconductor substrate, wiring, and impurity region (for example, variations in the impurity concentration of the substrate, transistor characteristics and wiring resistance, or variations in impurity ion implantation and heat treatment), the carrier accumulation unit 3A. The formation position of 3B varies.

Such variations in the formation positions of the carrier accumulation units 3A and 3B cause instability of the reading operation due to interference of accumulated carriers accompanying the approach of the carrier accumulation units 3A and 3B, particularly in a short channel transistor. Therefore, in order to avoid such instability of operation, the channel length has to be increased, and miniaturization and high integration of elements are limited. In particular, in the MNOS transistor constituting the SONOS memory, a thick ONO film is used as the first gate insulating film for accumulating carriers, and the scattering of impurity ions injected through the thick ONO film is large, so that the impurity region is precisely defined. Difficult to form. As a result, variations in the formation positions of the carrier accumulation portions 3A and 3B are large, which is an obstacle to miniaturization.
JP 2002-164449 A (FIG. 45 and paragraphs (0002) to (0004))

  As described above, in the conventional nonvolatile semiconductor memory device that stores and stores carriers at both ends of the gate insulating film, it is formed in the gate insulating film due to variations in drain voltage or impurity region structure caused by variations in the manufacturing process. The position of the carrier storage unit to be used varies greatly. As a result, when the channel length is short, there is a problem in that the separation interval between the carrier storage portions formed at both ends of the gate insulating film is shortened, resulting in reading failure. In order to avoid this reading failure, miniaturization of the semiconductor memory device has been limited.

  The present invention relates to a nonvolatile semiconductor memory device that stores and stores carriers at both ends of a gate insulating film, even if there are variations in drain voltage or impurity region structure due to variations in manufacturing processes. An object of the present invention is to provide a semiconductor memory device in which the variation is suppressed and the carrier accumulation portion is always formed in the vicinity of both ends of the gate insulating film with a small variation in position.

  In the semiconductor memory device according to the first configuration of the present invention for solving the above-described problem, a first gate electrode is provided on a semiconductor substrate with a first insulating film capable of storing carriers interposed therebetween. First and second impurity regions functioning as a source / drain are formed on both sides of the first and second electrodes apart from the first gate electrode. Then, the second gate electrode is provided on the substrate between the first gate electrode and the first and second impurity regions with the second gate insulating film interposed therebetween. In this configuration, the second gate electrode is a floating gate that is capacitively coupled to the first gate and the electrode.

  First, the write operation of the semiconductor memory device having the first configuration will be described. First, one of the first and second impurity regions is selected as a source and the other is selected as a drain. Source and drain voltages are applied to the respective impurity regions according to the selection, and simultaneously a write voltage is applied to the first gate electrode. Apply. The write voltage applied to the first gate electrode forms a channel immediately below the first gate electrode. On the other hand, a voltage is induced also in the second gate electrode through capacitive coupling with the first gate electrode, and a channel is also formed immediately below the second gate electrode. As a result, a channel is formed between the source and the drain, and hot carriers are injected and accumulated at an end portion near the drain of the first gate insulating film. By reversing the selection of the source and drain, hot carriers are accumulated at the other end of the first gate insulating film. This operation is the same as that of the conventional semiconductor memory device described above except for the involvement of the second gate electrode.

  In the first configuration described above, the first and second impurity regions are provided at a distance from the first gate electrode, for example, at a distance at which the channel is cut. For this reason, the influence of the potential of these impurity regions on the electric field of the channel immediately below the first gate electrode is small. On the other hand, the second gate electrode is provided between these impurity regions and the first gate electrode, and is adjacent to the first gate electrode. Therefore, the potential of the second gate electrode generates a large electric field in the channel near the end of the first gate electrode. That is, a large electric field is generated near the end of the first gate electrode on the drain side by the voltage induced in the second gate electrode. The second gate electrode is provided close to the substrate surface via a thin second gate insulating film. For this reason, the electric field generated from the second gate electrode is concentrated near the end of the first gate electrode adjacent to the second gate electrode, and hardly reaches the center of the first gate electrode. Carriers traveling in the channel are mainly accelerated in the electric field near the end of the first gate electrode to generate hot carriers, so that carrier injection into the first insulating film is restricted to the end region near the end of the first gate electrode. Is done. Accordingly, since carrier injection into the central portion of the first insulating film is small, the carrier storage portions (portions where carriers are stored) formed at both ends of the first insulating film are sufficiently separated so as not to cause read failure. Formed.

  As described above, in the first configuration, the electric field intensity for accelerating carriers traveling in the channel is mainly determined by the potential of the second gate electrode, and the influence of the drain potential is small. Therefore, even if there are variations in the impurity concentration of the drain, variations in the applied voltage, and variations in the drain end position and depth, the influence on the acceleration of carriers in the channel is small. Therefore, the influence of variations in the manufacturing process of the impurity region on the formation position of the carrier accumulation portion is small. Further, the electric field generated from the second gate electrode is concentrated in the vicinity of the end of the first gate electrode and has little influence on the central portion, so that the position of the carrier accumulation portion, in other words, the position where the carriers are accelerated until hot carriers are generated. Is limited to a narrow region near the second gate electrode. Therefore, the carrier storage portions formed at both ends of the first insulating film do not interfere during reading, and a semiconductor memory device that operates stably even in a short channel is obtained.

  Note that the voltage induced in the second gate electrode at the time of writing varies depending on the capacitance with the first gate electrode, the capacitance with the drain, other stray capacitance, or the drain voltage. However, since the electric field from the second gate electrode is concentrated in the vicinity of the end of the first gate electrode, the influence of the fluctuation of the second gate electrode voltage on the position of the carrier storage portion is small. The capacitance of the second gate electrode is mainly determined by the shape of the second gate electrode, the thickness of the capacitor insulating film and the second insulating film, and the dielectric constant. In a normal manufacturing process, fluctuations in the induced voltage of the second gate electrode due to variations in these capacitance determining factors are negligible. Further, since the same voltage is applied to the first gate electrode and the drain voltage at the time of writing, the influence of the fluctuation of the drain voltage on the induced voltage of the second gate electrode is small, and there is no practical problem in this configuration. .

  In the second configuration of the present invention, the gate electrode to which the write voltage of the first configuration described above is applied and the gate electrode to be a floating gate are interchanged. That is, in the second configuration, the first gate electrode is set in a floating state, and a write voltage is applied to the second gate electrode.

  In the second configuration, since the voltage of the second gate electrode for accelerating carriers is higher than the voltage induced in the first gate electrode, the writing voltage can be lowered. Further, in this configuration, since the potential of the second gate electrode is determined by the write voltage and is not affected by the stray capacitance, shape, or source voltage of the second gate electrode, the position variation of the carrier accumulation portion is small.

  The second gate electrode having the first and second configurations can be formed of a sidewall formed on a side surface of the first gate electrode via a capacitive insulating film. Thus, since the second gate electrode can be formed in self-alignment, the second gate electrode can be formed in a precise shape.

  Further, in the second configuration, the second gate electrode can be extended across the first gate electrode in the channel direction and on the substrates on both sides of the first gate electrode. For example, a second gate electrode perpendicular to the first gate electrode extending in the direction perpendicular to the channel is disposed on the substrate as a control gate electrode to which a write voltage is applied. At this time, the dummy sidewall formed on the side surface of the first gate electrode and the first and second impurity regions serving as the source and drain are formed by ion implantation using the first gate electrode as a mask, and then the dummy side is formed. The wall can be removed and a second gate electrode can be placed there. In the semiconductor memory device manufactured by this manufacturing method, the distance between the first gate electrode and the impurity region is precisely formed by self-alignment.

  In a third configuration of the present invention, the first gate electrode of the second configuration is replaced with a high dielectric film. In this configuration, the second gate electrode of the second configuration functions as a control gate electrode that forms a channel immediately below the first gate insulating film by applying a write voltage. When a write voltage is applied to the control gate electrode (second gate electrode), an electric field from the control gate electrode provided on the high dielectric is channeled immediately below the high dielectric film (that is, directly below the first gate insulating film). And a writing operation similar to that of the second configuration is performed. In the third configuration, since only the control gate electrode is sufficient as the gate electrode, the manufacture is easy.

  The high dielectric film must have a large dielectric constant and a thin film thickness so that a channel is formed immediately below the high dielectric film. On the other hand, the high dielectric film needs to have a thickness that protects the first gate insulating film as an ion implantation prevention during subsequent ion implantation for forming the impurity region. This high dielectric film may be composed of a lower layer made of a high dielectric material and an upper layer having a smaller dielectric constant but a large effect of preventing ion implantation. As a result, a semiconductor memory device is provided in which channel formation is performed at a low write voltage and the first gate insulating film has a good quality.

  In the third configuration of the present invention, a dummy sidewall may be formed on the side surface of the high dielectric film and ion implantation may be performed, and then the dummy sidewall may be removed to form a control gate electrode. As a result, the distance between the high dielectric film and the impurity region is precisely formed by self-alignment.

  According to a fourth configuration of the present invention, in the third configuration, a floating electrode is formed on the side surface of the high dielectric film on the second gate insulating film, and this is used as the second gate electrode. Further, the control gate electrode is disposed so as to cross the high dielectric film and the second gate electrode. In this configuration, the induced voltage of the second gate electrode with respect to the write voltage can be easily controlled by the coupling capacitance.

  As described above, according to the present invention, even if there is a variation in drain voltage or impurity region structure due to a variation in the manufacturing process, the variation in the formation position of the carrier accumulation portion is small, and the carrier accumulation portion is always the gate insulating film. It is possible to provide a nonvolatile semiconductor memory device that is precisely formed in the vicinity of both ends.

(1) First Embodiment of the Present Invention The first embodiment of the present invention relates to an embodiment in which a first gate electrode is a control gate electrode and a second gate electrode is a floating gate electrode. Note that the control gate electrode in this specification refers to a gate electrode that forms a channel immediately below a first gate insulating film by applying a writing voltage. Hereinafter, this embodiment will be described with reference to the manufacturing process.

  FIG. 1 is a cross-sectional process diagram of a first embodiment of the present invention, showing a cross section of an MNOS transistor in the middle of a manufacturing process. FIG. 7 is a plan view of the first embodiment of the present invention, showing a layout in which a plurality of MNOS transistors are integrated.

  Referring to FIGS. 1A and 7, first, STI (shallow trench isolation band) 11 that defines a transistor formation region is formed on a semiconductor substrate 1 to form transistor formation regions arranged in a lattice pattern. To do. Next, after ion-implanting an impurity that determines the threshold value of the transistor, the impurity is activated by performing an RTA treatment at 1000 ° C. for 10 seconds, for example (not shown).

  Next, a tunnel oxide film 3-1 having a thickness of 2 to 10 nm is formed by thermal oxidation, a nitride film 3-2 having a thickness of 2 to 10 nm is formed by a CVD method, and an oxide film 3-3 having a thickness of 5 to 20 nm is formed by a CVD method. These films are sequentially formed (these films 3-1 to 3-3 become the first gate insulating film 3 that is later patterned and accumulates carriers in the nitride film 3-2). Subsequently, a polycrystalline silicon film having a thickness of 50 to 150 nm (this film is later patterned to become the first gate electrode 4) is deposited by CVD. Thereafter, impurities are ion-implanted into the polycrystalline silicon film, and RTA treatment is performed at 1000 ° C. for 5 seconds to activate the impurities in the polycrystalline silicon film. Next, the polycrystalline silicon film, the oxide film 3-3, the nitride film 3-2, and the tunnel oxide film 3-1 are patterned using lithography and dry etching, and the first gate insulating film 3 and the first gate electrode having an ONO structure are patterned. 4 is formed. At this point, the tunnel oxide film 3-1 can be left. As a result, referring to FIG. 7, the first gate electrode 4 (the first gate insulating film 3 is disposed below the first gate electrode 4 extending across the top and bottom of the paper crossing the transistor formation regions arranged above and below the paper. Is formed).

  Next, referring to FIG. 1B, a capacitor insulating film 7 made of an oxide film covering the exposed surfaces of the first gate electrode 4 and the first gate insulating film 3 and the first gate by thermal oxidation or CVD. A second gate insulating film 6 made of an oxide film covering the exposed surface of the substrate 1 extending outside the electrode 4 is formed.

  Next, referring to FIG. 1C, a polycrystalline silicon film doped with an impurity having a thickness of 30 to 150 nm is formed on the upper surface of the substrate 1 by CVD, and activated by RTA treatment at 1000 ° C. for 5 seconds. . Thereafter, the entire surface of the polycrystalline silicon film is etched back, and a second gate electrode 5 made of a polycrystalline silicon sidewall is formed on the side surface of the first gate electrode 4 via the capacitive insulating film 7. The second gate electrode 5 is provided on the second gate insulating film 6. The second gate electrode 5 is a floating gate, and extends along the first gate electrode 4 with a capacitive insulating film 7 sandwiched between both sides of the first gate electrode 4 with reference to FIG. Further, the upper end of the second gate electrode 5 is set lower than the upper end of the first gate electrode 4. Accordingly, the interlayer insulating film can be left on the second gate electrode 5 when the sidewall of the interlayer insulating film is formed. Accordingly, when the salicide structure is formed on the upper surface of the first gate electrode 4, an insulation failure between the first gate electrode 4 and the second gate electrode 5 can be avoided.

  Next, low-concentration impurity regions 2-3 and 2-4 constituting part of the source and drain are formed by ion implantation using the first gate electrode 4, the capacitor insulating film 7 and the second gate electrode 5 as a mask.

  Next, referring to FIG. 1D, an insulating film having a thickness of 50 to 100 nm is formed on the entire surface of the substrate 1 by the CVD method, and this is etched back to cover the second gate electrode 5. A wall 14 is formed. Next, after ion implantation of impurities using the first gate electrode 4, the capacitor insulating film 7, the second gate electrode 5, and the insulating sidewall 14 as a mask, activation is performed by RTA treatment at 1000 ° C. for 5 seconds to obtain a high concentration. Impurity regions 2-5 and 2-6 are formed. The high-concentration impurity regions 2-5 and 2-6 include first and second impurity regions 2-1 and 2-2 that serve as source or drain regions together with the low-concentration impurity regions 2-3 and 2-4, respectively. Form.

  Next, a Co film having a thickness of 5 to 30 nm and a TiN film having a thickness of 5 to 50 nm are formed by a PVD (physical vapor deposition) method, and then at a temperature of 500 to 550 ° C. Silicide is formed on the first gate electrode 4 and the impurity regions 2-1 and 2-2 by a salicide process using RTA for 30 seconds and etching with sulfuric acid / hydrogen peroxide. Thereafter, silicide resistance reduction processing is performed at 800 to 900 ° C. for 30 seconds. Further, an interlayer insulating film is deposited, and wirings 12-1 and 12-2 and other wirings connected to the first and second impurity regions are formed to manufacture a semiconductor memory device.

  With reference to FIG. 7, the wirings 12-1 and 12-2 are provided for each row of transistors (transistors arranged in the left-right direction on the paper surface of FIG. 7), and the first and second gate electrodes 4, 5 is orthogonal. One set of the wirings 12-1 and 12-2 is selected, the drain voltage Vd is applied to one of them, the source voltage Vs is applied to the other, and one first gate electrode 4 is selected to apply the write voltage Vwr. To do. As a result, one transistor located at the intersection of the selected wirings 12-1 and 12-2 and the selected first gate electrode 4 is selected, and the first gate on the selected side as the drain of the transistor is selected. Carriers are injected into the end of the insulating film 3 and writing is performed. In the present embodiment, each of the transistors is separated by the STI 11, but the first and second impurity regions 2-1 and 2-2 of the adjacent transistors are shared, and the NOR type cell of the flash memory A similar configuration can be used. In this case, a pattern perpendicular to the STI channel is not required.

  Next, the write characteristic of the transistor of the first embodiment described above will be described. FIG. 2 is an explanatory diagram of write characteristics according to the first embodiment of the present invention. FIG. 2A shows a partially enlarged cross section near the drain of the first gate electrode of the transistor of the first embodiment. FIG. 2B shows an energy band diagram in the vicinity of the channel and the drain obtained by calculation when 5 V, 6 V, and 7 V are applied to the drain, respectively. 2B, the horizontal axis represents the distance from the end of the first gate electrode 4, and the vertical axis represents the conduction band lower end energy of the channel.

  Referring to FIG. 2A, second impurity region 2-2 (including adjacent low-concentration impurity region 2-4) is selected as a drain, and drain voltage Vd is applied (hereinafter selected as a drain). The second impurity region 2-2 is referred to as “drain 2-2”.) A write voltage Vwr is applied to the first gate electrode 4, and a channel 21 is formed immediately below. An induced voltage is applied to the second gate electrode 5 on the second gate insulating film 6 through the capacitive insulating film 7. As a result, a channel is also formed in the offset region 22 between the drain 2-2 and the first gate electrode 4, and the carrier 23 travels through the channel 21.

  Referring to FIG. 2B, the conduction band lower end energy rapidly decreases near the end of the first gate electrode 4 of the channel 21, and gradually decreases outside the first gate electrode 4 (offset region 22). 2-2 potential. Hot carriers are injected into the first gate insulating film 3 in the channel 21 near the end of the first gate electrode 4 in the region where the energy at the lower end of the conduction band rapidly decreases and the carrier 23 (FIG. 2A) is accelerated. Arise. This range is limited to a very narrow range as shown in the circle of FIG. Therefore, the region (carrier accumulation portion) where hot carriers are injected as the accumulation carrier 24 is limited to a narrow range at the end of the first gate electrode 4.

  Furthermore, even if the voltage of the drain 2-2 varies in the range of 5 to 7V, the position where the conduction band bottom energy rapidly decreases hardly changes. This indicates that the drain 2-2 voltage has little influence on the hot carrier generation position, that is, the formation position of the carrier accumulation portion.

  As described above, the carrier accumulation part is formed in a narrow region at the end of the first gate electrode, and the formation position thereof is hardly affected by the drain voltage. The inventor of the present invention infers the reason from the calculation result of FIG. 2 as follows.

  Referring to FIG. 2B, the drain 2-2 voltage difference gradually decreases as the distance from the drain 2-2 in the offset region 22 increases, and the difference between the offset region 22 and the channel 21 is extremely small. small. In this embodiment, since the channel is not formed without the second gate electrode 5 and the first gate electrode 4 and the drain 2-2 are separated to an offset region, the electric field from the drain 2-2 Does not reach the channel 21 beyond the offset region. Therefore, the influence of the shape of the drain 2-2 (for example, the depth / planar shape of the drain, the distance from the first gate electrode 4) or the impurity concentration of the drain 2-2 or the substrate 1 on the electric field in the channel is small.

  In addition, in the vicinity of this boundary, the gradient of the conduction band bottom energy in the channel 21 is large, so even if there is a potential difference (difference in conduction band bottom energy) at the boundary, the maximum conduction band bottom energy caused by the potential difference is present. The change in gradient position is only small. For this reason, even if the change in the electric field due to the difference in voltage and structure of the drain 2-2 reaches the channel, the change has a small effect on the variation in the hot carrier generation position.

As described above, since the drain 2-2 is away from the first gate electrode 4 and a steep conduction band bottom energy gradient is generated in the vicinity of the end face of the first gate electrode 4, in this embodiment, carrier accumulation is performed. The variation in position is small and the formation region is limited to a narrow range.
(2) Second Embodiment of the Present Invention The second embodiment of the present invention relates to an embodiment in which a first gate electrode is a floating gate and a write voltage is applied to the second gate electrode. FIG. 3 is a cross-sectional process diagram of a second embodiment of the present invention, showing a cross section of a transistor in a manufacturing process.

  First, referring to FIG. 3A, after STI is formed and impurity doping is performed to determine a threshold value, tunnel oxide film 3-1, nitride film 3-2, oxide film 3-3, and thickness 50 are formed. A polycrystalline silicon film of ˜150 nm (which will later become the first gate electrode 4) is sequentially deposited, and the polycrystalline silicon film is further doped with impurities. The above steps (not shown) are the same as in the first embodiment. Next, a nitride film having a thickness of 30 to 100 nm is deposited and patterned to form a nitride film mask 25. Next, the laminated film is patterned using the nitride film mask 25 to form a three-layer pattern including the first gate insulating film 3, the first gate electrode 4, and the nitride film mask 25. The three-layer pattern was the same planar pattern as the first gate electrode of the first embodiment described.

  Next, referring to FIG. 3B, an oxide film having a thickness of 5 to 20 nm is formed on the entire surface of the substrate 1 by thermal oxidation or CVD. In this oxide film, the portion formed on the side surface of the first gate electrode 4 becomes the capacitive insulating film 7, and the portion formed on the surface of the substrate 1 becomes the second gate insulating film 6.

  Next, referring to FIG. 3C, a second gate electrode 5 made of a polycrystalline silicon sidewall is formed on the side surface of the first gate electrode 4 by the same process as in the first embodiment. It is preferable to align the upper end of the second gate electrode 5 with the upper end of the nitride film mask 25 in order to increase the area where silicide can be formed on the second gate electrode 5. Next, low-concentration impurity regions 2-3 and 2-4 are formed by ion implantation and activation heat treatment using the first and second gate electrodes 4 and 5 as a mask.

  Next, referring to FIG. 3 (d), an insulating film is deposited by the CVD method and etched back to form an insulating sidewall 14 on the side surface of the second gate electrode 5. The insulating sidewall 14 is formed by adjusting the etch back amount so that the upper part of the second gate electrode 5 is exposed. Thereafter, high-concentration impurity regions 2-5 and 2-6 are formed by ion implantation using the first gate electrode 4, the second gate electrode 5 and the insulating sidewall 14 as a mask, and the first and second impurity regions 2 are formed. -1, 2-2.

  Next, a silicide film is formed on the exposed surface of the second gate electrode 5 and the exposed surface of the substrate 1 through a salicide process similar to that of the first embodiment. Next, an interlayer insulating film is formed, and necessary wirings are formed to manufacture the semiconductor memory device according to the second embodiment. In this embodiment, the same structure as that of the NOR type cell of the flash memory can be used.

In the second embodiment, a write voltage is applied to the second gate electrode 5, and the first gate electrode 4 is a floating gate electrode. Since a silicide film is formed on the surface of the second gate electrode 5 to reduce the resistance, the delay is small.
(3) Third Embodiment of the Present Invention In a third embodiment of the present invention, a second gate electrode in a floating state is provided on the side surface of a high dielectric film, and the orthogonal direction (channel direction) of the first gate insulating film is provided. The present invention relates to an embodiment provided with an extended control gate electrode. Hereinafter, it demonstrates along the manufacturing process. FIG. 4 is a cross-sectional process diagram of the third embodiment of the present invention, showing a cross-sectional structure of a transistor. FIG. 8 is a plan view of the third embodiment of the present invention, showing the electrode arrangement before the interlayer insulating film is deposited.

  First, referring to FIG. 8, an STI 11 similar to that of the first embodiment is formed, and an impurity for threshold adjustment is doped. Next, referring to FIG. 4A, a first gate insulating film 3 in which a tunnel oxide film 3-1, a nitride film 3-2, and an oxide film 3-3 are sequentially stacked is formed, and a thickness of 30 is formed thereon. A nitride film mask 25 which is a high dielectric film of ˜100 nm is formed. Next, a stacked pattern 15 of the first gate insulating film 3 and the nitride film mask 25 is formed by dry etching using the nitride film mask 25. With reference to FIG. 8, the laminated pattern 15 extends in the vertical direction on the paper surface. The tunnel oxide film 3-1 may be left.

  Next, referring to FIG. 4B, an oxide film having a thickness of 5 to 20 nm is formed on the entire surface of the substrate 1 by CVD or thermal oxidation. In this oxide film, the portion formed on the exposed surface of the substrate 1 constitutes the second gate insulating film 6. The oxide film formed on the surface of the stacked pattern 15 serves as a protective film for the first gate insulating film 3.

  Next, referring to FIG. 4C, a second gate electrode 5 made of a doped polycrystalline silicon sidewall is formed on the side surface of the laminated pattern 15. First and second impurity regions 2-1 and 2-2 are formed by ion implantation using the second gate electrode 5 and the nitride film mask 25 as a mask.

  Next, referring to FIG. 4D, an oxide film 26 having a thickness of 5 to 20 nm covering the side surface of the second gate electrode 5 is formed by CVD or thermal oxidation. This oxide film 26 can also cover the surface of the substrate 1 extending outside the stacked pattern 15 and the second gate electrode 5 alone or together with the second gate insulating film 6.

  Next, referring to FIG. 4E, a polycrystalline silicon film having a thickness of 50 to 150 nm is deposited on the entire surface of the substrate 1 by the CVD method, doped with impurities, and then patterned by lithography and dry etching. The control gate electrode 8 is used. Referring to FIG. 8, the control gate electrode 8 extends across the plurality of transistors in a direction orthogonal to the extending direction (vertical direction of the paper surface) of the nitride film mask 25 and the first gate insulating film 3. doing.

  Next, an interlayer insulating film is deposited, and wirings extending along the nitride film mask 25 and connected to the first and second impurity regions 2-1 and 2-2 and other wirings are formed thereon. An AND type semiconductor memory device is manufactured.

  In this embodiment, the write voltage is applied to the control gate electrode 8, and a voltage is induced through capacitive coupling using the oxide film 26 as a dielectric film to the second gate electrode which is a floating gate. The writing operation of the transistor of this embodiment is the same as that of the first embodiment described above. That is, the control gate electrode 8 is provided on the first gate insulating film 3 through the nitride film mask 25 which is a high dielectric film instead of the first gate electrode of the first embodiment. Then, a channel is formed under the first gate insulating film 3 by the writing voltage applied to the control gate electrode 8, and writing is performed. Here, since the dielectric constant of the nitride film mask 25 is high, even if the nitride film mask 25 has a sufficient thickness to prevent ion implantation, an electric field sufficient to form a channel is generated with a low write voltage. be able to.

  During the patterning of the control gate electrode 8, the oxide film 26, the second gate insulating film 6, the oxide film formed at the same time, and the second gate electrode 5 exposed outside the control gate electrode 8 are etched. It is preferable to remove. 4E is an AB cross-sectional view in FIG. 8, and FIG. 4F is a CD cross-sectional view in FIG. As a result, referring to FIG. 4F, the second gate electrode 5 is removed in a place where the control gate electrode 8 is not present. In this way, by limiting the width (length in the extending direction) of the second gate electrode 5 to just below the control gate electrode 8, the second gate electrode 5 generated from the portion extending outside the control gate electrode 8. By blocking the stray capacitance, it is possible to avoid a decrease in the induced voltage of the second gate electrode 5 due to the stray capacitance.

In the third embodiment described above, each transistor is separated by the STI 11. This can also be configured in the same manner as an AND type cell of a flash memory. For example, referring to FIG. 8, first and second impurity regions 2-1 and 2-2 are formed as continuous regions by forming first impurity region 2-1 and second impurity region 2-2 adjacent in the vertical direction of the drawing. The wiring connected to 1 and 2-2 can be omitted. Furthermore, the impurity regions 2-1 and 2-2 adjacent to the left and right of the paper surface can be shared to reduce the area. Unlike the flash memory in which charges are stored in a conductive floating gate in an AND type cell in which the impurity regions of these adjacent cells are formed as continuous regions, the semiconductor memory device of the present invention that stores in an insulating film uses STI. There is no need to provide separation. Therefore, the first STI formation step can be omitted.
(4) Fourth Embodiment of the Present Invention In the fourth embodiment of the present invention, the first gate electrode is a floating gate, and the second gate electrode to which the write voltage is applied is on the first gate electrode in the channel direction. The present invention relates to a transversely extending embodiment. Hereinafter, it demonstrates along the manufacturing process. FIG. 5 is a cross-sectional process diagram of the fourth embodiment of the present invention, showing a cross-sectional structure of a transistor. FIG. 9 is a plan view of a fourth embodiment of the present invention, and shows an electrode arrangement before depositing an interlayer insulating film having an AND type cell structure.

  First, ion implantation and activation processing are performed to adjust the threshold value. Since the present embodiment adopts an AND type cell structure, it is not necessary to form an STI. Next, referring to FIG. 5A, as in the first embodiment, the first gate insulating film 3 composed of a laminated film of a tunnel oxide film 3-1, a nitride film 3-2 and an oxide film 3-3, A polycrystalline silicon film having a thickness of 30 to 100 nm is sequentially deposited and patterned thereon to form a pattern in which the first gate electrode 4 is provided on the first gate insulating film 3. This pattern is a plurality of patterns extending in parallel with each other in the vertical direction of the paper surface of FIG.

  Next, referring to FIG. 5B, an oxide film having a thickness of 5 to 20 nm is formed to cover the first gate electrode 4 and the exposed surface of the substrate by thermal oxidation or CVD. This oxide film becomes the capacitive insulating film 7 on the upper surface and side surfaces of the first gate electrode 4, and becomes the second gate insulating film 6 on the exposed surface of the substrate 1.

  Next, referring to FIG. 5C, a nitride film having a thickness of 30 to 150 nm is deposited by the CVD method and etched back to form dummy sidewalls 10 made of the nitride film on the side surfaces of the first gate electrode 4. . Next, first and second impurity regions 2-1 and 2-2 are formed by ion implantation using the first gate electrode 4 and the dummy sidewall 10 as a mask. Referring to FIG. 9, the first and second impurity regions 2-1 and 2-2 are offset regions determined by the thickness of the dummy sidewall 10 from the first gate electrode 4 in parallel with the first gate electrode 4. Are formed apart by a width of. By using this dummy sidewall 10, the offset width can be easily and precisely defined.

  Next, referring to FIG. 5D, the dummy sidewall 10 is removed by etching using phosphoric acid as an etchant.

  Next, referring to FIG. 5E, a polycrystalline silicon film having a thickness of 50 to 150 nm is deposited on the entire surface by CVD, and after ion implantation of impurities into this polycrystalline silicon film, an RTA treatment is performed at 1000 ° C. for 5 seconds. Activated by. Next, the polycrystalline silicon film is patterned to form the second gate electrode 5. At the same time, the first gate electrode 4 extending outside the second gate electrode 5 is removed by etching together with the oxide film on the upper surface thereof. At this time, the second gate insulating film 6 extending outside the second gate electrode 5 is also removed at the same time. Next, after the second gate electrode 5 is buried with an insulating film and planarized by CMP (chemical mechanical polishing), a silicide layer is formed on the upper surface of the second gate electrode 5.

  Referring to FIG. 9, the second gate electrode is formed as a belt-like pattern extending in a direction perpendicular to the first gate insulating film 3 and the first gate electrode 4 (left and right direction in FIG. 9). . Then, referring to FIG. 5 (e) showing the EF cross section in FIG. 9 and FIG. 5 (f) showing the GH cross section, the first gate electrode 4 which is a floating gate overlaps with the second gate electrode 5. Are not formed between adjacent second gate electrodes 5. In this way, the first gate electrode 4 immediately below the adjacent second gate electrode 5 is separated from each other, thereby reducing the capacitance coupled to the first gate electrode 4 and writing applied to the second gate electrode 5. The voltage induced to the second gate electrode by the built-in voltage can be increased.

In the fourth embodiment described above, an AND-type cell structure in which STI is not formed is used. However, all the transistors can be insulated and separated by STI, and necessary wiring can be formed. With this structure, a semiconductor memory in which one second gate electrode 5 and one of wirings connected to the first and second impurity regions 2-1 and 2-2 orthogonal to the second gate electrode 5 are selected and written to the transistor at the intersection. It can be a device.
(5) Fifth Embodiment of the Invention A fifth embodiment of the present invention uses a high dielectric film instead of the first gate electrode of the fourth embodiment, and the second gate of the fourth embodiment is a control gate. The present invention relates to an embodiment used as an electrode (an electrode for forming a channel immediately below a first gate insulating film when a writing voltage is applied). This high dielectric film may be continuous between adjacent cells, and need not be separated as in the first gate electrode of the fourth embodiment. Hereinafter, it demonstrates along the manufacturing process. FIG. 6 is a cross-sectional process diagram of a fifth embodiment of the present invention, showing a cross-sectional structure of a transistor.

First, ion implantation and activation for threshold adjustment are performed. Note that this embodiment has an AND-type cell structure as in the fourth embodiment shown in FIG. 9, and therefore it is not necessary to form an STI. Of course, a semiconductor memory device having a structure in which each transistor is separated by STI can be used. Next, referring to FIG. 6A, a first gate insulating film 3 in which a tunnel oxide film 3-1, a nitride film 3-2 and an oxide film 3-3 are stacked is deposited in the same manner as in the first embodiment. Next, an Al ₂ O ₃ film having a thickness of 30 to 50 nm is deposited by CVD. Next, the Al ₂ O ₃ film and the first gate insulating film 3 are patterned by dry etching, and a high dielectric composed of the first gate insulating film 3 and Al ₂ O ₃ extending in the direction perpendicular to the paper surface of FIG. A laminated pattern 15 of the film 9 is formed.

  Next, referring to FIG. 6B, an oxide film having a thickness of 5 to 20 nm is formed on the entire surface by thermal oxidation or CVD. A portion of the oxide film formed on the surface of the substrate 1 becomes the second gate insulating film 6.

  Next, referring to FIG. 6C, a nitride film having a thickness of 30 to 150 nm is deposited on the entire surface, and then etched back to form dummy sidewalls 10 made of the nitride film on the side surfaces of the laminated pattern 15. Next, first and second impurity regions 2-1 and 2-2 are formed by ion implantation using the stacked pattern 15 and the dummy sidewall 10 as a mask. At this time, since ion implantation into the first gate insulating film is effectively prevented by the high dielectric film 9, there is little deterioration in the characteristics of the first gate insulating film 3 that accumulates and stores carriers.

  Next, referring to FIG. 6D, the dummy sidewall 10 is etched and removed using phosphoric acid as an etchant.

  Next, referring to FIG. 6E, a polycrystalline silicon film is deposited on the entire surface and patterned to extend a strip-like pattern (FIG. 9) extending in the orthogonal direction of the laminated pattern 15 (the left-right direction in FIG. 9). The control gate electrode 8 having the same pattern as that of the second gate electrode 9 is formed. In the present embodiment, the stacked pattern 15 extends across a plurality of control gate electrodes 8 extending in parallel to each other, but has the same structure immediately below the control gate electrode 8 and between the control gate electrodes 8. Can do. Therefore, only the patterning of the control gate electrode 8 needs to be considered, and the process becomes simple. It is desirable to perform over-etching so that the polycrystalline silicon film constituting the control gate electrode 8 does not remain between the control gate electrodes 8.

  Further, since the dielectric constant of the high dielectric film 9 of the present embodiment is large, the effective gate film thickness as viewed from the control gate electrode 8 is thin. Therefore, even if the thick high dielectric film 9 sufficient to prevent ion implantation is used, channel formation is performed. A necessary electric field can be applied.

  Next, after depositing an insulating film and filling the space between the control gate electrodes 8 by CMP, a silicide film is formed on the upper surface of the control gate electrode 8. Thereafter, necessary wirings are formed on the interlayer insulating film, and the semiconductor memory device is manufactured.

The invention described in the following supplementary notes is disclosed in the above description.
(Appendix 1)
A first gate electrode provided on a semiconductor substrate via a first gate insulating film; and first and second impurity regions formed on both sides of the first gate electrode; In a semiconductor memory device capable of storing carriers injected from a channel at both ends,
A second gate insulating film formed on the substrate exposed between the first gate insulating film and the first and second impurity regions;
A second gate electrode capacitively coupled to the first gate electrode formed on the substrate on both sides of the first gate electrode via the second gate insulating film;
A side near the impurity region selected as the drain of the first and second impurity regions by applying a write voltage to the first gate electrode to induce a voltage in the second gate electrode in a floating state. A semiconductor memory device, wherein carriers are injected into an end portion of the first gate insulating film.
(Appendix 2)
A first gate electrode provided on a semiconductor substrate via a first gate insulating film; and first and second impurity regions formed on both sides of the first gate electrode; In a semiconductor memory device capable of storing carriers injected from a channel at both ends,
A second gate insulating film formed on the substrate exposed between the first gate insulating film and the first and second impurity regions;
A second gate electrode capacitively coupled to the first gate electrode formed on the substrate on both sides of the first gate electrode via the second gate insulating film;
A voltage close to the impurity region selected as the drain of the first and second impurity regions is induced by applying a write voltage to the second gate electrode to induce a voltage in the floating first gate electrode. A semiconductor memory device, wherein carriers are injected into an end portion of the first gate insulating film.
(Appendix 3)
The supplementary note 1 or 2, wherein the second gate electrode comprises a sidewall formed on a side surface of the first gate electrode through a capacitive insulating film provided on a side surface of the first gate electrode. Semiconductor memory device.
(Appendix 4)
The semiconductor memory device according to claim 2, wherein the second gate electrode extends in the channel length direction across the first gate electrode.
(Appendix 5)
First and second impurity regions formed in a semiconductor substrate;
A first gate insulating film formed on the substrate between the first and second impurity regions and capable of storing carriers injected from the channel at both ends;
A high dielectric film formed on the first gate insulating film and having a thickness that serves as an ion implantation prevention film during ion implantation for forming the first and second impurity regions;
A second gate insulating film formed on the substrate exposed between the first gate insulating film and the first and second impurity regions;
A control gate electrode extending on the second gate insulating film across the high dielectric film,
Applying a write voltage to the control gate electrode to inject carriers into the end of the first gate insulating film on the side close to the impurity region selected as the drain of the first and second impurity regions A semiconductor memory device.
(Appendix 6)
A floating second gate electrode formed on the second gate insulating film adjacent to the high dielectric film;
6. The semiconductor memory device according to claim 5, wherein the control gate electrode extends on the substrate across the high dielectric film and the second gate electrode capacitively coupled to the control gate electrode. .
(Appendix 7)
Forming the first gate electrode on the first gate insulating film;
Next, a capacitor insulating film that covers the upper surface and side surfaces of the first gate electrode and the side surfaces of the first insulating film, and the second gate insulating film that covers the substrate surface exposed outside the first gate insulating film; Forming a step;
Next, forming a dummy sidewall on the second gate insulating film, which is in contact with the side surface of the first gate electrode through the capacitive insulating film;
A step of forming the first and second impurity regions by ion implantation using the first gate electrode and the dummy sidewall as a mask;
Next, removing the dummy sidewalls;
And forming a second gate electrode extending over the second gate insulating film across the first gate electrode. 5. The method of manufacturing a semiconductor memory device according to claim 4, further comprising:
(Appendix 8)
Forming the high dielectric film on the first gate insulating film;
Next, forming the second gate insulating film covering the substrate surface exposed outside the high dielectric film;
Next, forming a dummy sidewall on the second gate insulating film and on the side surface of the high dielectric film,
A step of forming the first and second impurity regions by ion implantation using the high dielectric film and the dummy sidewall as a mask;
Next, removing the dummy sidewalls;
The method of manufacturing a semiconductor memory device according to claim 5, further comprising: forming a control gate electrode extending over the second gate insulating film across the high dielectric film.

  According to the present invention, the carrier writing position does not change and both ends of the first gate insulating film against variations caused in the manufacturing process such as source / drain shape, impurity concentration, drain applied voltage, or substrate concentration. A transistor which can be written nearby can be provided. Therefore, even if the channel length is shortened, the interference of written carriers is small, and it can be used for manufacturing a nonvolatile semiconductor memory device with a small cell area.

Sectional process drawing of the first embodiment of the present invention First embodiment writing characteristics explanatory diagram of the present invention Sectional process drawing of the second embodiment of the present invention Cross-sectional process drawing of the third embodiment of the present invention Sectional process drawing of the fourth embodiment of the present invention Sectional process drawing of the fifth embodiment of the present invention First embodiment plan view of the present invention Third embodiment plan view of the present invention Fourth embodiment plan view of the present invention Cross-sectional view of a conventional semiconductor memory device

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Substrate 2-1, 2-2 Impurity region 2-3, 2-4 Low concentration impurity region 2-5, 2-6 High concentration impurity region 3 First gate insulating film 3-1 Tunnel oxide film 3-2 Nitride film 3-3 Oxide film 3A, 3B Carrier accumulation part 4 First gate electrode 5 Second gate electrode 6 Second gate insulating film 7 Capacitance insulating film 8 Control gate electrode 9 High dielectric film 10 Dummy sidewall 11 STI (shallow trench isolation) band)
12-1, 12-2 wiring 13 gate electrode 14 insulating side wall 15 stacking pattern 21 channel 22 offset region 23 carrier 24 storage carrier 25 nitride film mask 26 oxide film Vwr write voltage Vs source voltage Vd drain voltage

Claims (5)

A first gate electrode provided on a semiconductor substrate via a first gate insulating film; and first and second impurity regions formed on both sides of the first gate electrode; In a semiconductor memory device capable of storing carriers injected from a channel at both ends,
A second gate insulating film formed on the substrate exposed between the first gate insulating film and the first and second impurity regions;
A second gate electrode capacitively coupled to the first gate electrode formed on the substrate on both sides of the first gate electrode via the second gate insulating film;
A side near the impurity region selected as the drain of the first and second impurity regions by applying a write voltage to the first gate electrode to induce a voltage in the second gate electrode in a floating state. A semiconductor memory device, wherein carriers are injected into an end portion of the first gate insulating film. A first gate electrode provided on a semiconductor substrate via a first gate insulating film; and first and second impurity regions formed on both sides of the first gate electrode; In a semiconductor memory device capable of storing carriers injected from a channel at both ends,
A second gate insulating film formed on the substrate exposed between the first gate insulating film and the first and second impurity regions;
A second gate electrode capacitively coupled to the first gate electrode formed on the substrate on both sides of the first gate electrode via the second gate insulating film;
A voltage close to the impurity region selected as the drain of the first and second impurity regions is induced by applying a write voltage to the second gate electrode to induce a voltage in the floating first gate electrode. A semiconductor memory device, wherein carriers are injected into an end portion of the first gate insulating film. First and second impurity regions formed in a semiconductor substrate;
A first gate insulating film formed on the substrate between the first and second impurity regions and capable of storing carriers injected from the channel at both ends;
A high dielectric film formed on the first gate insulating film and having a thickness that serves as an ion implantation prevention film during ion implantation for forming the first and second impurity regions;
A second gate insulating film formed on the substrate exposed between the first gate insulating film and the first and second impurity regions;
A control gate electrode extending on the second gate insulating film across the high dielectric film,
Applying a write voltage to the control gate electrode to inject carriers into the end of the first gate insulating film on the side close to the impurity region selected as the drain of the first and second impurity regions A semiconductor memory device. Forming the first gate electrode on the first gate insulating film;
Next, a capacitor insulating film that covers the upper surface and side surfaces of the first gate electrode and the side surfaces of the first insulating film, and the second gate insulating film that covers the substrate surface exposed outside the first gate insulating film; Forming a step;
Next, forming a dummy sidewall on the second gate insulating film, which is in contact with the side surface of the first gate electrode through the capacitive insulating film;
A step of forming the first and second impurity regions by ion implantation using the first gate electrode and the dummy sidewall as a mask;
Next, removing the dummy sidewalls;
3. The method of manufacturing a semiconductor memory device according to claim 2, further comprising: forming a second gate electrode extending on the second gate insulating film across the first gate electrode. . Forming the high dielectric film on the first gate insulating film;
Next, forming the second gate insulating film covering the substrate surface exposed outside the high dielectric film;
Next, forming a dummy sidewall on the second gate insulating film and on the side surface of the high dielectric film,
A step of forming the first and second impurity regions by ion implantation using the high dielectric film and the dummy sidewall as a mask;
Next, removing the dummy sidewalls;
4. A method of manufacturing a semiconductor memory device according to claim 3, further comprising a step of forming a control gate electrode extending over the second gate insulating film across the high dielectric film.

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