CN112768466A - Three-dimensional memory and preparation method thereof - Google Patents
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
The invention discloses a preparation method of a three-dimensional memory, wherein the three-dimensional memory comprises a selection tube grid, and the method comprises the following steps: providing a laminated structure; forming a channel structure vertically through the stack structure, the channel structure comprising a memory stack and a channel layer; removing the first sacrificial layer at the preset forming position of the grid electrode of the selection tube in the laminated structure; removing the storage lamination layer horizontally corresponding to the preset forming position of the grid electrode of the selection tube, and forming an insulated structure at the position of the removed storage lamination layer; filling grid metal in a preset forming position of the grid of the selection tube to form the grid of the selection tube; forming a select tube of the three-dimensional memory based on the select tube gate, the insulated structure, and the channel layer; wherein a memory layer of the memory stack is not included between the select gate and the channel layer.
Description
Technical Field
The invention relates to the technical field of storage devices, in particular to a three-dimensional memory and a preparation method thereof.
Background
Memory (Memory) is a Memory device used in modern information technology to store information. With the increasing demands of various electronic devices for integration and data storage density, it is increasingly difficult for a common two-dimensional memory device to meet the demands, and in such a situation, a three-dimensional (3D) memory has come into play.
NAND memory, a typical three-dimensional memory, has become a mainstream product in the non-volatile memory market due to its high storage density, controllable production cost, suitable programming and erasing speed, and retention characteristics. The NAND memory is programmed layer by layer when storing information, when a selection string unit (cell) is programmed, an upper selection tube grid (TSG) of the selection string is opened, high voltage is applied to a Word Line (WL) where the unit is located, electrons flow into a channel layer and enter a storage layer through FN (Fowler-Nordheim) tunneling, and programming is completed; for the non-selected string, the corresponding TSG is turned off, and electrons cannot flow into the channel layer, so that even though the cell on the non-selected string cell is also high-voltage-boosted, the non-selected string cell will not be programmed due to the lack of electrons in the channel layer.
However, with the increasing demand for memory density, there are more and more three-dimensional memory stacks and memory cells, which puts higher demands on the turn-off capability of the TSG. Therefore, how to prevent the threshold voltage (Vt) distribution from being widened or shifted due to the programming of the unselected string cell becomes a technical problem to be solved in the art.
Disclosure of Invention
In view of the above, the main objective of the present invention is to provide a three-dimensional memory and a method for manufacturing the same.
In order to achieve the purpose, the technical scheme of the invention is realized as follows:
the embodiment of the invention provides a preparation method of a three-dimensional memory, wherein the three-dimensional memory comprises a selection tube grid, and the method comprises the following steps:
providing a laminated structure;
forming a channel structure vertically through the stack structure, the channel structure comprising a memory stack and a channel layer;
removing the first sacrificial layer at the preset forming position of the grid electrode of the selection tube in the laminated structure;
removing the storage lamination layer horizontally corresponding to the preset forming position of the grid electrode of the selection tube, and forming an insulated structure at the position of the removed storage lamination layer;
filling grid metal in a preset forming position of the grid of the selection tube to form the grid of the selection tube; forming a select tube of the three-dimensional memory based on the select tube gate, the insulated structure, and the channel layer; wherein a memory layer of the memory stack is not included between the select gate and the channel layer.
In the foregoing solution, the stacked structure further includes a second sacrificial layer located at a preset formation position of another gate below the gate of the selection transistor, where the second sacrificial layer is selected from materials having different etching rates under the same etching conditions as the first sacrificial layer.
In the above scheme, the material of the first sacrificial layer includes silicon oxynitride or polysilicon.
In the foregoing scheme, after forming the channel structure and before removing the first sacrificial layer, the method further includes:
removing the second sacrificial layer based on a different etch rate between the second sacrificial layer and the first sacrificial layer;
and filling the gate metal at the vacant preset forming positions of the other gates after the removal.
In the above solution, the memory stack includes a tunneling layer, the memory layer, and a blocking layer sequentially arranged in a direction away from the channel layer; the removing of the memory lamination layer horizontally corresponding to the preset forming position of the grid electrode of the selection tube and the forming of an insulating structure at the position of the removed memory lamination layer comprise:
removing the barrier layer and part of the storage layer horizontally corresponding to the preset forming position of the grid electrode of the selection tube;
and oxidizing the rest part of the storage layer to form an insulated first oxide layer, wherein the first oxide layer and the tunneling layer jointly form the insulated structure.
In the above scheme, the first oxide layer and the tunneling layer are both silicon oxide layers.
The embodiment of the present invention further provides a three-dimensional memory, where the three-dimensional memory includes a selection transistor gate, and the three-dimensional memory further includes:
a channel layer;
an insulated structure is arranged between the grid electrode of the selection tube and the channel layer, and a storage layer is not arranged between the grid electrode of the selection tube and the channel layer; the grid electrode of the selection tube, the insulated structure and the channel layer jointly form a selection tube of the three-dimensional memory;
a memory stack located at a periphery of the channel layer; at a position corresponding to the selection tube grid level, at least partially removing the storage lamination and forming the insulated structure; the selection tube gate is at least partially formed at the position where the storage lamination layer is removed.
In the above scheme, the material of the insulating structure includes silicon oxide.
In the above solution, the three-dimensional memory further includes:
and the other grid electrode is positioned below the grid electrode of the selection tube, and the distance between the grid electrode of the selection tube and the channel layer is different from the distance between the other grid electrode and the channel layer.
In the above solution, the three-dimensional memory further includes:
and the memory lamination layer is positioned on the periphery of the channel layer, the memory lamination layer is disconnected at a position corresponding to the level of the grid electrode of the selection tube, and at least part of the grid electrode of the selection tube is formed at the disconnected position.
The preparation method of the three-dimensional memory provided by the embodiment of the invention comprises a selection tube grid, and the method comprises the following steps: providing a laminated structure; forming a channel structure vertically through the stack structure, the channel structure comprising a memory stack and a channel layer; removing the first sacrificial layer at the preset forming position of the grid electrode of the selection tube in the laminated structure; removing the storage lamination layer horizontally corresponding to the preset forming position of the grid electrode of the selection tube, and forming an insulated structure at the position of the removed storage lamination layer; filling grid metal in a preset forming position of the grid of the selection tube to form the grid of the selection tube; forming a select tube of the three-dimensional memory based on the select tube gate, the insulated structure, and the channel layer. Therefore, the prepared three-dimensional memory has a selection tube structure consisting of a selection tube grid electrode, an insulating structure and a channel layer, the Vt value of the selection tube structure is stable, and the influence of the process stability of a storage layer and the escape or enrichment of bound charges is avoided, so that the working stability of the device is improved; the preparation method has simple process and high reliability.
Drawings
Fig. 1 is a schematic structural cross-sectional view of a three-dimensional memory provided in the related art;
fig. 2 is a schematic flow chart of a method for manufacturing a three-dimensional memory according to an embodiment of the present invention;
fig. 3 to 13 are schematic cross-sectional views of device structures in a process of manufacturing a three-dimensional memory according to an embodiment of the invention.
Description of reference numerals:
100. 200-a three-dimensional memory;
10. 20-a semiconductor substrate;
111-a dielectric layer;
21-a laminated structure; 211-a second dielectric layer; 212-a second sacrificial layer; 213-first dielectric layer; 214-a first sacrificial layer;
12. 22-a memory stack; 221-a barrier layer; 222-a storage layer; 223-a tunneling layer; 224-a first oxide layer;
13. 23-a channel layer;
141-lower select gate; 142-memory layer and redundancy layer gate; 143-upper select gate;
24-a filler layer;
25-doped regions;
26-other gates; 261-a high-k dielectric layer; 262-a metal barrier layer; 263-gate metal;
26' -select gate;
27. 27' -a sidewall oxide layer;
28. 28' -ACS filler layer;
29-gate dielectric layer.
Detailed Description
Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the invention are shown in the drawings, it should be understood that the invention may be embodied in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the present invention; that is, not all features of an actual embodiment are described herein, and well-known functions and structures are not described in detail.
In the drawings, the size of layers, regions, elements, and relative sizes may be exaggerated for clarity. Like reference numerals refer to like elements throughout.
It will be understood that when an element or layer is referred to as being "on" … …, "adjacent to … …," "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on … …," "directly adjacent to … …," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention. And the discussion of a second element, component, region, layer or section does not necessarily imply that a first element, component, region, layer or section is present in the invention.
Spatial relationship terms such as "under … …", "under … …", "below", "under … …", "above … …", "above", and the like, may be used herein for ease of description to describe the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below … …" and "below … …" can encompass both an orientation of up and down. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
In the following description, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the present invention. The following detailed description of the preferred embodiments of the invention, however, the invention is capable of other embodiments in addition to those detailed.
Fig. 1 shows a three-dimensional memory structure provided by the related art.
As shown, the three-dimensional memory 100 includes: a semiconductor substrate 10; a stacked structure formed by alternately stacked gate layers and dielectric layers 111 is provided on the semiconductor substrate 10, and each gate layer specifically includes a lower selection transistor gate (BSG)141, a storage layer and redundancy layer gate 142, and an upper selection transistor gate (TSG) 143; a channel via CH penetrating the stacked structure is filled with a channel structure in the CH, the channel structure including at least a memory stack 12 and a channel layer 13.
In the three-dimensional Memory 100, since the channel structures and the gate layers of the select transistor and the Memory cell are formed in a unified manner, the upper select transistor is a trap Trapping Memory (CTM) structure as well as the Memory cell. When the upper selection tube is started, a starting voltage is loaded on the TSG, and the threshold voltage of the upper selection tube is easy to drift after repeated operation; the stability of the threshold voltage of the upper selection tube is also influenced by the long-term retention characteristic of the storage layer, and when the charge of the storage layer escapes or is enriched under the high-temperature condition or under the influence of a fringe electric field, the drift of the threshold voltage of the upper selection tube is aggravated, so that the stability of the programming of the memory is seriously influenced.
Based on this, the embodiment of the invention provides a preparation method of a three-dimensional memory, wherein the three-dimensional memory comprises a selection tube grid.
Fig. 2 shows a flow chart of a method for manufacturing the three-dimensional memory. As shown, the method comprises the steps of:
102, forming a channel structure vertically penetrating through the substrate structure, wherein the channel structure comprises a storage laminated layer and a channel layer;
103, removing the first sacrificial layer at the preset forming position of the grid electrode of the selection tube in the substrate structure;
104, removing the storage lamination layer horizontally corresponding to the preset forming position of the grid electrode of the selection tube, and forming a grid dielectric layer at the position of the removed storage lamination layer;
105, filling grid metal in a preset forming position of the grid of the selection tube to form the grid of the selection tube; and forming a selection tube of the three-dimensional memory based on the selection tube grid, the grid medium layer and the channel layer.
The present invention will be further described in detail with reference to the cross-sectional views of the device structure in the process of manufacturing the three-dimensional memory in fig. 3 to 13.
First, step 101 is performed to provide a base structure.
Referring to fig. 3, the substrate structure includes a first sacrificial layer 214, and the first sacrificial layer 214 is located at a predetermined forming position of the select gate.
Specifically, the selection tube gate is an upper selection tube gate of the three-dimensional memory.
In one embodiment, the base structure further comprises: a semiconductor substrate 20, and a stacked structure 21 formed on the semiconductor substrate 20.
Here, the semiconductor substrate 20 may include at least one elemental semiconductor material (e.g., a silicon (Si) substrate, a germanium (Ge) substrate), at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art.
The stacked structure 21 may include a first dielectric layer 213, a first sacrificial layer 214, a second dielectric layer 211, and a second sacrificial layer 212. The material of the second dielectric layer 211 includes, but is not limited to, silicon oxide, silicon nitride layer, silicon oxynitride, and other high dielectric constant (high-k) dielectric layers; in this embodiment, the second dielectric layer 211 is formed of silicon oxide; the material of the first dielectric layer 213 may be the same as or different from that of the second dielectric layer 211; the second sacrificial layer 212 may be formed of, for example, one of an oxide layer, a nitride layer, a silicon carbide layer, a silicon layer, and a silicon germanium layer; in the present embodiment, the second sacrificial layer 212 is formed of silicon nitride; the first sacrificial layer 214 is selected from a material having a different etch rate under the same etch conditions as the second sacrificial layer 212; in this embodiment, the material of the first sacrificial layer 214 includes silicon oxynitride or polysilicon. The second sacrificial layer 212 is located at a preset formation position of other gates below the gate of the select transistor, where the other gates specifically include at least one of: a lower selection tube grid, a redundant area grid and a storage area grid; the second sacrificial layer 212 is specifically a sacrificial layer at a predetermined formation position of the upper selection gate.
The stacked structure 21 may be formed using a Chemical Vapor Deposition (CVD) process, a Plasma Enhanced Chemical Vapor Deposition (PECVD) process, or an Atomic Layer Deposition (ALD) process.
Next, step 102 is performed to form a channel structure vertically through the base structure, the channel structure comprising a memory stack 22 and a channel layer 23.
In an embodiment, the forming the channel structure specifically includes: and etching the laminated structure 21 to form a channel through hole CH, wherein the channel through hole CH exposes the semiconductor substrate 20. The trench via CH may be formed through a dry etching process. Optionally, an epitaxial layer (SEG) is formed on the semiconductor substrate 20 at the bottom of the trench via CH. Next, the memory stack 22 is formed within the trench via CH. In one embodiment, the memory stack 22 includes a blocking layer 221, a memory layer 222, and a tunneling layer 223 formed in sequence; the memory stack 22 may specifically be an ONO stack, an AONO stack, an ONOP stack or other suitable memory stack structure. In this embodiment, the process of forming the memory stack 22 may specifically include: depositing an oxide layer (e.g., SiO) in the trench via CH2Layer) forming the barrier layer 221; depositing on the oxide layerA nitride layer (e.g., SiN layer) formed on the memory layer 222; in one embodiment, the storage layer 222 may be specifically a charge trapping layer; next, an oxide layer (e.g., SiO) is deposited on the nitride layer2Layer) forming the tunneling layer 223; the blocking layer 221, the memory layer 222, and the tunneling layer 223 collectively function to control the charge storage function of the memory device. The memory stack 22 may be deposited using a CVD or ALD process. After the formation of the memory stack 22, a step of etching the bottom of the memory stack 22 to expose the epitaxial layer SEG may be included. Next, depositing the channel layer 23, wherein the channel layer 23 provides a channel for movement of carriers for the three-dimensional memory; a filling layer 24 is formed inside the channel layer 23.
In an embodiment, after forming the channel structure, the method further comprises: removing the second sacrificial layer 212 based on the different etch rates between the second sacrificial layer 212 and the first sacrificial layer 214; and filling the gate metal at the vacant preset forming positions of the other gates after the removal.
Specifically, the removing the second sacrificial layer 212 may be removed from a position of an array common source via (ACS Hole) of the three-dimensional memory.
Referring to fig. 4, the ACS Hole is etched, which exposes the semiconductor substrate 20. In an embodiment, the method further comprises: in the semiconductor substrate 20 at the bottom of the ACS Hole, a doped region 25 is formed. The doped region 25 may be formed by implanting dopant atoms through the ACS Hole into the semiconductor substrate 20; alternatively, it may be formed by selective epitaxial growth of ion-doped semiconductor material. The doped region 25 may serve as a source region of the device. In this embodiment, the doped region 25 is, for example, an N-type semiconductor doped region; the semiconductor substrate 20 is, for example, a P-type semiconductor layer.
Next, referring to fig. 5, the second sacrificial layer 212 is removed based on the different etching rates between the second sacrificial layer 212 and the first sacrificial layer 214. Specifically, the second sacrificial layer 212 may be removed by a wet etching process.
Next, referring to fig. 6, the gate metal 263 is filled at the predetermined forming position of the other gate left after the removal. Specifically, a high-k dielectric layer 261 is deposited at the preset forming position of the other vacant gate; then, depositing a metal barrier layer 262 on the high-k dielectric layer 261; finally, the interior of the metal barrier 262 is filled with the gate metal 263 in the predetermined formation location. Here, the material of the high-k dielectric layer may be selected from high dielectric constant materials commonly used in the art, such as Al2O3(ii) a The metal barrier layer may be formed of a transition metal material or a conductive metal nitride, for example, including at least one of titanium, tantalum, titanium nitride, tantalum nitride; the gate metal may be formed of an electrode material, such as tungsten, nickel, or a tungsten-nickel alloy. The high-k dielectric layer 261, the metal barrier layer 262 and the gate metal 263 together form a gate structure (other gate) 26. Also, the high-k dielectric layer 261, the metal barrier layer 262, and the gate metal 263 may be deposited by a CVD or ALD process.
Next, please refer to fig. 7. In an embodiment, the method may further include: sidewall oxide layers 27, sidewall metal barrier layers (not shown) and ACS fill layers 28 are formed within the ACS Hole. The sidewall oxide layer 27, the sidewall metal barrier layer and the ACS filling layer 28 may be deposited by a CVD or ALD process, and the excess sidewall metal barrier layer, ACS filling layer and sidewall oxide layer are removed by dry etching or wet etching, thereby forming the structure shown in fig. 7.
Next, please refer to fig. 8. Step 103 is executed to remove the first sacrificial layer 214 at the preset forming position of the select tube gate in the substrate structure. Specifically, the first sacrificial layer 214 may be removed by a wet etching process.
Next, step 104 is executed to remove the memory stack layer horizontally corresponding to the preset formation position of the gate of the select transistor, and form a gate dielectric layer at the position of the removed memory stack layer.
In one embodiment, the memory stack 22 includes a tunneling layer 223, a memory layer 222, and a blocking layer 221 sequentially arranged in a direction away from the channel layer 23; the removing the storage stack 22 horizontally corresponding to the preset forming position of the gate of the selection tube, and forming a gate dielectric layer at the position of the removed storage stack includes: the barrier layer 221 and a portion of the memory layer 222 corresponding to the predetermined forming position level of the select gate are removed (refer to fig. 9).
Next, referring to fig. 10, the remaining portion of the memory layer 222 is oxidized to form a first oxide layer 224, and the first oxide layer 224 and the tunneling layer 223 together form the gate dielectric layer 29.
Specifically, the first oxide layer 224 and the tunneling layer 223 are both silicon oxide layers. For example, the material of the tunneling layer 223 is SiO2The memory layer 222 is made of SiN; an oxidation reaction is performed and the remaining portion of the SiN storage layer 222 is oxidized to form SiO2A first oxide layer 224; the first oxide layer 224 and the tunneling layer 223 are both SiO2And thus collectively form the gate dielectric layer 29.
It should be noted that the method for forming the gate dielectric layer 29 according to the embodiment of the present invention is not limited thereto, and in another embodiment, the gate dielectric layer may be deposited after removing the memory stack horizontally corresponding to the predetermined forming position of the select gate.
It should be noted that the gate dielectric layer 29 according to the embodiment of the present invention does not only refer to a material thereof as a dielectric material, but also refers to a gate dielectric layer functioning as a field effect transistor. The gate dielectric layer 29 may have a single-layer structure or a multi-layer structure. In one embodiment, the select transistor of the three-dimensional memory may be a MOS transistor structure.
Next, step 105 is executed to fill a gate metal in a preset forming position of the select transistor gate; and forming a selection tube of the three-dimensional memory based on the grid metal, the grid medium layer and the channel layer.
Specifically, please refer to fig. 11. And filling a gate metal at the preset forming position of the selection tube gate to form a gate structure (selection tube gate) 26'. The formation process of the gate structure 26' may be the same as the formation process of the gate structure 26, that is, the formation process also includes depositing a high-k dielectric layer, a metal barrier layer, and a gate metal in sequence; and the excess gate structure on the ACS Hole sidewall and the ACS fill layer 28 is removed by an etching process to form the structure shown in fig. 11. Thus, the fabrication of the selection tube of the three-dimensional memory is completed.
Next, please refer to fig. 12. In an embodiment, the method may further include: and forming a side wall oxide layer 27' in the ACS Hole corresponding to the selection tube. It will be appreciated that if the ACS fill layer 28 in the ACS Hole is now covered by other structures (e.g., oxide), the ACS fill layer 28 should be etched away to form the structure shown in fig. 12.
Next, please refer to fig. 13. In an embodiment, the method may further include: the sidewall oxide layer 27 'is filled with a sidewall metal barrier layer (not shown) and an ACS filling layer 28', completing an ACS structure.
The preparation method of the three-dimensional memory provided by the embodiment of the invention has the advantages that the process is simple, the reliability is high, the formed three-dimensional memory has the selection tube structure consisting of the selection tube grid electrode, the grid dielectric layer and the channel layer, the Vt value of the selection tube structure is stable, and the influence of the storage layer process stability and the escape or enrichment of bound charges is avoided, so that the working stability of a device is improved.
Based on the above method, and with reference to fig. 13, an embodiment of the invention further provides a three-dimensional memory 200.
The three-dimensional memory 200 includes a select gate 26', and the three-dimensional memory 200 further includes: a channel layer 23; a gate dielectric layer 29 is included between the select tube gate 26' and the channel layer 23; the selection tube gate 26', the gate dielectric layer 29 and the channel layer 23 together form a selection tube of the three-dimensional memory 200.
In one embodiment, the material of the gate dielectric layer 29 includes silicon oxide.
In one embodiment, the three-dimensional memory 200 further comprises: and the other grid 26 is positioned below the selection tube grid 26 ', and the distance between the selection tube grid 26' and the channel layer 23 is different from the distance between the other grid 26 and the channel layer 23.
In one embodiment, the three-dimensional memory 200 further comprises: a memory stack 22 located at the periphery of the channel layer 23, the memory stack 22 being disconnected at a location horizontally corresponding to the select tube gate 26 ', the select tube gate 26' being at least partially formed at the disconnected location.
It should be noted that the embodiments of the three-dimensional memory and the method for manufacturing the three-dimensional memory provided in the above embodiments belong to the same concept, and specific implementation processes and other detailed structures thereof are described in detail in the embodiments of the methods and are not described herein again. The technical schemes described in the embodiments of the present invention can be combined arbitrarily without conflict.
The above description is only exemplary of the present invention and should not be taken as limiting the scope of the present invention, and any modifications, equivalents, improvements, etc. that are within the spirit and principle of the present invention should be included in the present invention.
Claims (9)
1. A method for preparing a three-dimensional memory, wherein the three-dimensional memory comprises a selection tube grid, and the method comprises the following steps:
providing a laminated structure;
forming a channel structure vertically through the stack structure, the channel structure comprising a memory stack and a channel layer;
removing the first sacrificial layer at the preset forming position of the grid electrode of the selection tube in the laminated structure;
removing the storage lamination layer horizontally corresponding to the preset forming position of the grid electrode of the selection tube, and forming an insulated structure at the position of the removed storage lamination layer;
filling grid metal in a preset forming position of the grid of the selection tube to form the grid of the selection tube; forming a select tube of the three-dimensional memory based on the select tube gate, the insulated structure, and the channel layer; wherein a memory layer of the memory stack is not included between the select gate and the channel layer.
2. The method of claim 1, wherein the stacked structure further comprises a second sacrificial layer at a predetermined formation position of other gate electrodes below the gate electrode of the select transistor, the second sacrificial layer being selected from materials having different etching rates under the same etching conditions as the first sacrificial layer.
3. The method of claim 1, wherein the material of the first sacrificial layer comprises silicon oxynitride or polysilicon.
4. The method of claim 2, wherein after forming the channel structure and before removing the first sacrificial layer, the method further comprises:
removing the second sacrificial layer based on a different etch rate between the second sacrificial layer and the first sacrificial layer;
and filling the gate metal at the vacant preset forming positions of the other gates after the removal.
5. The method of claim 1, wherein the memory stack comprises a tunneling layer, the memory layer, and a blocking layer arranged sequentially in a direction away from the channel layer; the removing of the memory lamination layer horizontally corresponding to the preset forming position of the grid electrode of the selection tube and the forming of an insulating structure at the position of the removed memory lamination layer comprise:
removing the barrier layer and part of the storage layer horizontally corresponding to the preset forming position of the grid electrode of the selection tube;
and oxidizing the rest part of the storage layer to form an insulated first oxide layer, wherein the first oxide layer and the tunneling layer jointly form the insulated structure.
6. The method of claim 5, wherein the first oxide layer and the tunneling layer are both silicon oxide layers.
7. A three-dimensional memory comprising a select tube gate, the three-dimensional memory further comprising:
a channel layer;
an insulated structure is arranged between the grid electrode of the selection tube and the channel layer, and a storage layer is not arranged between the grid electrode of the selection tube and the channel layer; the grid electrode of the selection tube, the insulated structure and the channel layer jointly form a selection tube of the three-dimensional memory;
a memory stack located at a periphery of the channel layer; at a position corresponding to the selection tube grid level, at least partially removing the storage lamination and forming the insulated structure; the selection tube gate is at least partially formed at the position where the storage lamination layer is removed.
8. The three-dimensional memory according to claim 7, wherein the material of the insulating structure comprises silicon oxide.
9. The three-dimensional memory according to claim 7, further comprising:
and the other grid electrode is positioned below the grid electrode of the selection tube, and the distance between the grid electrode of the selection tube and the channel layer is different from the distance between the other grid electrode and the channel layer.
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