CN104157573A - Preparation method for FinFET structure - Google Patents
Preparation method for FinFET structure Download PDFInfo
- Publication number
- CN104157573A CN104157573A CN201410359358.3A CN201410359358A CN104157573A CN 104157573 A CN104157573 A CN 104157573A CN 201410359358 A CN201410359358 A CN 201410359358A CN 104157573 A CN104157573 A CN 104157573A
- Authority
- CN
- China
- Prior art keywords
- layer
- preparation
- coating
- finfet structure
- barrier layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000002360 preparation method Methods 0.000 title claims abstract description 39
- 238000000034 method Methods 0.000 claims abstract description 45
- 230000004888 barrier function Effects 0.000 claims abstract description 42
- 239000011248 coating agent Substances 0.000 claims description 38
- 238000000576 coating method Methods 0.000 claims description 38
- 239000004065 semiconductor Substances 0.000 claims description 35
- 239000000758 substrate Substances 0.000 claims description 27
- 239000000463 material Substances 0.000 claims description 19
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 13
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 13
- 229910003481 amorphous carbon Inorganic materials 0.000 claims description 11
- 229910052710 silicon Inorganic materials 0.000 claims description 11
- 239000010703 silicon Substances 0.000 claims description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 10
- 238000005530 etching Methods 0.000 claims description 10
- 238000000151 deposition Methods 0.000 claims description 5
- 230000007547 defect Effects 0.000 abstract description 7
- 238000005457 optimization Methods 0.000 abstract description 4
- 239000000126 substance Substances 0.000 abstract description 4
- 238000000227 grinding Methods 0.000 abstract description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 13
- 238000002955 isolation Methods 0.000 description 13
- 239000000377 silicon dioxide Substances 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 4
- 230000005669 field effect Effects 0.000 description 4
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- 239000008280 blood Substances 0.000 description 2
- 210000004369 blood Anatomy 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 229910003978 SiClx Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 239000003518 caustics Substances 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000003814 drug Substances 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000004064 recycling Methods 0.000 description 1
- 150000003376 silicon Chemical class 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention discloses a preparation method for a FinFET structure. According to the preparation method, an extra barrier layer is introduced after a PAD oxide layer is deposited to fill a shallow channel insulating layer to be used as a stop layer for chemical and mechanical grinding, so that well thickness control and defect optimization can be realized in a chemical and mechanical mask processing procedure of the shallow channel insulating layer. The method adopts oxide as side walls, so that the line width of the Fin can be adjusted conveniently in the Fin forming process; moreover, the side walls are easy to remove, so that the preparation process of the FinFET structure is further optimized; the compatibility of the method and a traditional process is high, and the implementation is easy.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, relate in particular to a kind of preparation method of FinFET structure.
Background technology
Along with semiconductor technology development, cmos circuit size is constantly dwindled, and traditional plane MOSFET technique has been difficult to meet performance and the power consumption requirement of device and circuit again.Thereby this brand-new semiconductor structure of fin formula field effect transistor (FinFET) has been proposed, to improve the device performance of CMOS (Complementary Metal Oxide Semiconductor) field-effect transistor (CMOS).
Advanced fin formula field effect transistor is the main technique of Logic 20nm processing procedure.CD especially little (being about 12nm) due to its Fin, the technology that needs double exposure (double patterning), so that being easy to the stop-layer of the cmp of the shallow trench isolations layer (STI) that forms in conventional planar technique can not form easily in fin formula field effect transistor, and hard mask (Hard Mask in Fin, be called for short HM) be difficult for removing, thus the thickness and the defect that cause forming the cmp processing procedure of shallow trench isolations layer are difficult to control.
Chinese patent (publication number: CN103871899A) disclose a kind of preparation method of FINFET structure, having comprised: grind away the silica 1 on silicon nitride 2; By low selection, than lapping liquid, continue to grind a certain amount of silica 1 and silicon nitride 2, with the thickness of attenuate silicon nitride 2; Wet etching is removed silicon nitride; Wet etching is removed partial oxygen SiClx 1, forms FinFET structure.The technical scheme of this invention is simple and easy to do, utilize CMP processing procedure twice, the thickness of attenuate silicon nitride, increase the width of silicon nitride, increase the contact area of silicon nitride and medicament, be conducive to the removal of wet method to silicon nitride, finally reach the removal completely of silicon nitride, avoided silicon nitride to remove incomplete consequence.
Chinese patent (publication number: CN101140887A) disclose a kind of transistorized method of making FINFET, that to select crystal orientation be that (110) SOI (SEMICONDUCTOR ON INSULATOR) wafer is backing material, with the semiconductor layer that anisotropic caustic solution corrodes this SOI material, form a smooth-sided compression candles and perpendicular to surperficial semiconductor bar, and the mid portion of this semiconductor bar is carried out to heavy doping.Then take this semiconductor bar as substrate, from both sides selective epitaxy growth semiconductor film, recycling is heavy, enough large corrosion selection ratio between light dope material, erodes the heavily doped region of semiconductor bar, leave two ends and the epitaxial loayer of semiconductor bar, just form required ultra-thin FIN body.On this FIN body, grow gate medium and gate electrode, then carry out conventional cmos later process, obtain FINFET transistor.
Above-mentioned two patents disclose respectively the preparation method of FinFET structure, but its technical scheme of taking is not identical with the technical scheme that the prepared FinFET structure of the present invention adopts, and and in unresolved prior art in FinFET structure in Fin hard mask be difficult for to remove and owing to being difficult for forming the stop-layer of the cmp of shallow trench isolations layer (STI) in FinFET structure, thereby cause forming thickness and the defect problem very rambunctious of the cmp processing procedure of shallow trench isolations layer.
Summary of the invention
Problem for above-mentioned existence, the present invention discloses a kind of preparation method of FinFET structure, to overcome in prior art in FinFET structure that hard mask in Fin is difficult for removing and owing to being difficult for forming the stop-layer of the cmp of shallow trench isolations layer (STI) in FinFET structure, thereby cause forming thickness and the defect problem very rambunctious of the cmp processing procedure of shallow trench isolations layer.
To achieve these goals, the application has recorded a kind of preparation method of FinFET structure, wherein, comprises the steps:
Semi-conductive substrate is provided;
In described Semiconductor substrate, according to order from bottom to up, prepare successively the first oxide skin(coating), barrier layer and sacrifice layer;
Sacrifice layer described in etched portions, sacrifices grid to form on described barrier layer;
Continue at the side wall that preparation on the sidewall of described sacrifice grid has predetermined thickness;
Take described side wall as barrier layer, described the first oxide skin(coating) described in mask successively etching and stop in described Semiconductor substrate, to form fin structure;
Remove after described side wall, continue depositing insulating layer, and described insulating barrier is carried out to the upper surface that flatening process stops at remaining described barrier layer;
Wherein, according to the thickness of described fin structure, set the value of described predetermined thickness.
The preparation method of above-mentioned FinFET structure, wherein, described method also comprises:
In the upper surface of described Semiconductor substrate, according to order from bottom to up, form successively described the first oxide skin(coating), described barrier layer, described sacrifice layer, an amorphous carbon layer and an antireflecting coating;
On described antireflecting coating, form and there is the photoresistance of gate patterns, and take described photoresistance as antireflecting coating, amorphous carbon layer and described sacrifice layer described in mask successively partial etching;
According to order from top to bottom, remove successively after described photoresistance, remaining antireflecting coating and remaining amorphous carbon layer, on described barrier layer, form and sacrifice grid.
The preparation method of above-mentioned FinFET structure, wherein, the material on described barrier layer is silicon nitride.
The preparation method of above-mentioned FinFET structure, wherein, the material of described sacrifice layer is unformed silicon.
The preparation method of above-mentioned FinFET structure, wherein, the material of described side wall and described insulating barrier is oxide.
The preparation method of above-mentioned FinFET structure, wherein, the step of preparing the side wall with predetermined thickness on the sidewall of described sacrificial gate is specially:
Deposit the second oxide skin(coating) and cover the surface of described barrier layer exposure and the surface of remaining described sacrifice layer;
Adopt dry etch process to remove after unnecessary described the second oxide skin(coating), remaining described the second oxide skin(coating) form cover described sacrifice gate lateral wall described in there is the side wall of predetermined thickness.
The preparation method of above-mentioned FinFET structure, wherein, described Semiconductor substrate is P type semiconductor substrate.
The preparation method of above-mentioned FinFET structure, wherein, adopts sacrifice layer described in dry etch process etched portions, to form described sacrifice grid on described barrier layer.
The preparation method of above-mentioned FinFET structure, wherein, adopt dry etch process take described side wall as mask according to barrier layer, the first oxide skin(coating) described in order from top to bottom successively etching to described Semiconductor substrate, to form described fin structure.
The preparation method of above-mentioned FinFET structure, wherein, described Semiconductor substrate comprises a silicon layer, forms described fin structure in described silicon layer.
Foregoing invention tool has the following advantages or beneficial effect:
The preparation method of a kind of FinFET structure disclosed by the invention, by introduce extra barrier layer after PAD oxide layer deposition, thereby after shallow trench isolations layer is filled as the stop-layer of cmp, thereby in the chemical machinery mask processing procedure of shallow trench isolations layer, realize the optimization of good THICKNESS CONTROL and defect, and the present invention adopts oxide as side wall, thereby in the process that forms Fin, be easy to adjust by the thickness of oxide the live width of Fin, and this side wall is easy to remove, thereby further optimized the preparation technology of FinFET structure.
Concrete accompanying drawing explanation
By reading the detailed description of non-limiting example being done with reference to the following drawings, the present invention and feature thereof, profile and advantage will become more apparent.In whole accompanying drawings, identical mark is indicated identical part.Can proportionally not draw accompanying drawing, focus on illustrating purport of the present invention.
Fig. 1-10th, the preparation method's of FinFET structure flowage structure schematic diagram in the embodiment of the present invention;
Figure 11 adopts FinFET structure prepared by method of the present invention structural representation under SEM.
Embodiment
Below in conjunction with accompanying drawing and specific embodiment, the present invention is further illustrated, but not as limiting to the invention.
As Figure 1-10 shows, the present embodiment relates to a kind of preparation method of FinFET structure, specifically comprises the steps:
Step S1, semi-conductive substrate 1 is provided, and (this Semiconductor substrate 1 can comprise a silicon layer, and in this silicon layer, form follow-up fin structure), in the upper surface (upper surface of silicon layer) of Semiconductor substrate 1, according to order from bottom to up, form successively the first oxide skin(coating) (PAD silicon oxide layer) 2, barrier layer 3, sacrifice layer 4, in an embodiment of the present invention, these sacrifice layer 4 upper surfaces can also be formed with amorphous carbon layer (A-C) 5, antireflecting coating (SiON) 6, wherein, antireflecting coating 6 is used for reducing reflection of light in follow-up photoetching process, and amorphous carbon layer 5 is mainly used to protect sacrifice layer in the etching technics of follow-up sacrifice layer, the technique that forms the first oxide skin(coating) 2, barrier layer 3, sacrifice layer 4, amorphous carbon layer 5, antireflecting coating 6 in Semiconductor substrate 1 all can adopt technology well-known to those skilled in the art, and at this, just it will not go into details, structure as shown in Figure 1.
Preferably, the material of the first oxide 2 is silica.
Preferably, the material on barrier layer 3 is silicon nitride.
Preferably, the material of sacrifice layer 4 is unformed silicon (A-Si), can certainly adopt other materials such as agraphitic carbon, and this does not affect object of the present invention.
Preferably, Semiconductor substrate 1 is P type semiconductor substrate.
Step S2, spin coating one deck photoresist in antireflecting coating 6, and form the photoresistance 7 with gate patterns, structure as shown in Figure 2 after this layer photoetching glue is exposed, developed.
Step S3, to barrier layer, 3 upper surface stops as mask successively etching antireflecting coating 6, amorphous carbon layer 5, sacrifice layer 4 to take photoresistance 7, preferred, adopts dry etch process etching sacrificial layer 4, structure as shown in Figure 3.
Step S4, according to order from top to bottom remove successively photoresistance 7, remaining antireflecting coating 6 ' and remaining amorphous carbon layer 5 ', be positioned at remaining sacrifice layer 4 on barrier layer 7 ' formation and sacrifice grid, structure as shown in Figure 4.
Step S5, continue at the side wall 8 (this side wall 8 covers the sidewalls of sacrificing grids) that preparation on the sidewall of sacrificing grid (be remaining sacrifice layer 4 ') has predetermined thickness, the thickness of the fin structure wherein, forming according to need is set the value of this predetermined thickness.Preferably, the material of side wall 8 is oxide (such as silica etc.), this is because the side wall of employing oxide material can be in the process of formation fin structure (Fin), by the thickness of oxide, the live width of Fin is adjusted to (predetermined thickness of this side wall 8 can be set according to the follow-up live width of the Fin of formation that needs) easily, and after forming Fin, this side wall 8 is also easy to remove; Concrete, the step that forms this side wall 8 is, deposit surface that the second oxide skin(coating) covering barrier layer 3 exposes and remaining sacrifice layer 4 ' surface after, adopt dry etch process to remove after the second unnecessary oxide skin(coating), form and cover the side wall with predetermined thickness 8 of sacrificing gate lateral wall, preferably, the material of this second oxide skin(coating) is silicon dioxide; Structure as shown in Figure 5.
Step S6, remove to sacrifice grid (be remaining sacrifice layer 4 '), preferred, adopts wet-etching technology to remove and sacrifices grid, structure as shown in Figure 6.
Step S7, adopt dry etch process to using side wall 8 as hard mask (Hard Mask, be called for short HM) according to order from top to bottom successively etching barrier layer 3, the first oxide skin(coating) 2 a to part that etches away described Semiconductor substrate stops, remaining barrier layer 3 ', remaining the first oxide skin(coating) 2 ', and the remaining Semiconductor substrate 1 of part ' (be remaining Semiconductor substrate 1 ' in be positioned at remaining the first oxide skin(coating) 2 ' under and the part identical with this remaining first oxide skin(coating) 2 ' live width, in an embodiment of the present invention, the material of this part is silicon) formation fin structure, structure as shown in Figure 7.
Step S8, removes side wall 8, and because the material of side wall 8 is oxide, the technique that therefore removes side wall 8 is very easy to (such as adopting dry etch process etc.), structure as shown in Figure 8.
Step S9, continue depositing insulating layer 9 cover remaining Semiconductor substrate 1 ', remaining the first oxide skin(coating) 2 ' and remaining barrier layer 3 ' upper surface and sidewall (filling of shallow trench isolations layer) thereof, preferably, the material of this insulating barrier 9 is oxide (such as silicon dioxide etc.), structure as shown in Figure 9.
Step S10, to insulating barrier 9 carry out flatening process (cmp) stop at remaining barrier layer 3 ' upper surface, form FinFET structure, wherein, in flatening process, due to remaining barrier layer 3 ' can be used as the grinding stop-layer of cmp, thereby realize the controlled and defect optimization of the thickness of cmp processing procedure of shallow trench isolations layer.
Figure 11 adopts FinFET structure prepared by method of the present invention structural representation under SEM, as seen from Figure 11, adopt its shallow trench isolations layer of FinFET structure prepared by method of the present invention (be remaining insulating barrier 9 ') can stop at the upper surface on remaining barrier layer.
To sum up, the preparation method of a kind of FinFET structure disclosed by the invention, by introduce extra barrier layer after PAD oxide layer deposition, thereby after shallow trench isolations layer is filled as the stop-layer of cmp, thereby in the chemical machinery mask processing procedure of shallow trench isolations layer, realize the optimization of good THICKNESS CONTROL and defect, and the present invention adopts oxide as side wall, thereby in the process that forms Fin, be easy to adjust by the thickness of oxide the live width of Fin, and this side wall is easy to remove, thereby further optimized the preparation technology of FinFET structure, and the method and traditional handicraft are compatible strong, be easy to realize.
It should be appreciated by those skilled in the art that those skilled in the art, realizing described variation example in conjunction with prior art and above-described embodiment, do not repeat at this.Such variation example does not affect flesh and blood of the present invention, does not repeat them here.
Above preferred embodiment of the present invention is described.It will be appreciated that, the present invention is not limited to above-mentioned specific implementations, and the equipment of wherein not describing in detail to the greatest extent and structure are construed as with the common mode in this area to be implemented; Any those of ordinary skill in the art, do not departing from technical solution of the present invention scope situation, all can utilize method and the technology contents of above-mentioned announcement to make many possible changes and modification to technical solution of the present invention, or being revised as the equivalent embodiment of equivalent variations, this does not affect flesh and blood of the present invention.Therefore, every content that does not depart from technical solution of the present invention,, all still belongs in the scope of technical solution of the present invention protection any simple modification made for any of the above embodiments, equivalent variations and modification according to technical spirit of the present invention.
Claims (10)
1. a preparation method for FinFET structure, is characterized in that, comprises the steps:
Semi-conductive substrate is provided;
In described Semiconductor substrate, according to order from bottom to up, prepare successively the first oxide skin(coating), barrier layer and sacrifice layer;
Sacrifice layer described in etched portions, sacrifices grid to form on described barrier layer;
Continue at the side wall that preparation on the sidewall of described sacrifice grid has predetermined thickness;
Take described side wall as barrier layer, described the first oxide skin(coating) described in mask successively etching and stop in described Semiconductor substrate, to form fin structure;
Remove after described side wall, continue depositing insulating layer, and described insulating barrier is carried out to the upper surface that flatening process stops at remaining described barrier layer;
Wherein, according to the thickness of described fin structure, set the value of described predetermined thickness.
2. the preparation method of FinFET structure as claimed in claim 1, is characterized in that, described method also comprises:
In the upper surface of described Semiconductor substrate, according to order from bottom to up, form successively described the first oxide skin(coating), described barrier layer, described sacrifice layer, an amorphous carbon layer and an antireflecting coating;
On described antireflecting coating, form and there is the photoresistance of gate patterns, and take described photoresistance as antireflecting coating, amorphous carbon layer and described sacrifice layer described in mask successively partial etching;
According to order from top to bottom, remove successively after described photoresistance, remaining antireflecting coating and remaining amorphous carbon layer, on described barrier layer, form and sacrifice grid.
3. the preparation method of FinFET structure as claimed in claim 1, is characterized in that, the material on described barrier layer is silicon nitride.
4. the preparation method of FinFET structure as claimed in claim 1, is characterized in that, the material of described sacrifice layer is unformed silicon.
5. the preparation method of FinFET structure as claimed in claim 1, is characterized in that, the material of described side wall and described insulating barrier is oxide.
6. the preparation method of FinFET structure as claimed in claim 5, is characterized in that, the step that preparation has a side wall of predetermined thickness on the sidewall of described sacrificial gate is specially:
Deposit the second oxide skin(coating) and cover the surface of described barrier layer exposure and the surface of remaining described sacrifice layer;
Adopt dry etch process to remove after unnecessary described the second oxide skin(coating), remaining described the second oxide skin(coating) form cover described sacrifice gate lateral wall described in there is the side wall of predetermined thickness.
7. the preparation method of FinFET structure as claimed in claim 1, is characterized in that, described Semiconductor substrate is P type semiconductor substrate.
8. the preparation method of FinFET structure as claimed in claim 1, is characterized in that, adopts sacrifice layer described in dry etch process etched portions, to form described sacrifice grid on described barrier layer.
9. the preparation method of FinFET structure as claimed in claim 1, it is characterized in that, adopt dry etch process take described side wall as mask according to barrier layer, the first oxide skin(coating) described in order from top to bottom successively etching to described Semiconductor substrate, to form described fin structure.
10. the preparation method of FinFET structure as claimed in claim 1, is characterized in that, described Semiconductor substrate comprises a silicon layer, forms described fin structure in described silicon layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410359358.3A CN104157573A (en) | 2014-07-25 | 2014-07-25 | Preparation method for FinFET structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410359358.3A CN104157573A (en) | 2014-07-25 | 2014-07-25 | Preparation method for FinFET structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN104157573A true CN104157573A (en) | 2014-11-19 |
Family
ID=51883047
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410359358.3A Pending CN104157573A (en) | 2014-07-25 | 2014-07-25 | Preparation method for FinFET structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104157573A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104465398A (en) * | 2014-11-28 | 2015-03-25 | 上海华力微电子有限公司 | FinFET preparation method |
| CN112366179A (en) * | 2020-10-15 | 2021-02-12 | 长江存储科技有限责任公司 | Semiconductor device structure and preparation method |
-
2014
- 2014-07-25 CN CN201410359358.3A patent/CN104157573A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104465398A (en) * | 2014-11-28 | 2015-03-25 | 上海华力微电子有限公司 | FinFET preparation method |
| CN104465398B (en) * | 2014-11-28 | 2018-04-03 | 上海华力微电子有限公司 | A kind of FinFET preparation methods |
| CN112366179A (en) * | 2020-10-15 | 2021-02-12 | 长江存储科技有限责任公司 | Semiconductor device structure and preparation method |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8513078B2 (en) | Structure and method for fabricating fin devices | |
| US9324790B2 (en) | Self-aligned dual-height isolation for bulk FinFET | |
| CN104900495A (en) | Self-aligned double patterning method and fin field effect transistor manufacturing method | |
| TWI524433B (en) | Integrated circuits and methods for fabricating integrated circuits with cladded non-planar transistor structures | |
| CN103578988A (en) | Fin part and finned-type field-effect transistor and forming method thereof | |
| CN104425220A (en) | Method for forming pattern | |
| CN104347409B (en) | The forming method of semiconductor structure | |
| CN104157573A (en) | Preparation method for FinFET structure | |
| TWI728966B (en) | Semiconductor device and method for fabricating the same | |
| CN111383994B (en) | Semiconductor structure and forming method thereof | |
| CN104064469A (en) | Semiconductor device manufacturing method | |
| CN103187280A (en) | Manufacturing method of fin type field effect transistor | |
| CN103165425A (en) | Method for forming fin formula field-effect tube grid side wall layer | |
| CN103187286B (en) | The manufacture method of fin formula field effect transistor | |
| US20180006112A1 (en) | Three-dimensional transisor | |
| CN108122762B (en) | Semiconductor structure and forming method thereof | |
| CN109841521A (en) | Semiconductor device and method of forming the same | |
| CN103887177A (en) | Finned active area manufacturing method | |
| CN103632978A (en) | Formation method for semiconductor structure | |
| CN106373993B (en) | The forming method of transistor | |
| CN103943500A (en) | Manufacturing method of fin field effect transistor | |
| CN107068764B (en) | Semiconductor device manufacturing method | |
| CN106449761B (en) | The forming method of semiconductor devices | |
| CN105225963A (en) | A kind of preparation method of FinFET semiconductor device | |
| CN104733316A (en) | FinFET device and forming method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20141119 |
|
| RJ01 | Rejection of invention patent application after publication |