CN110034187A - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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- CN110034187A CN110034187A CN201810026747.2A CN201810026747A CN110034187A CN 110034187 A CN110034187 A CN 110034187A CN 201810026747 A CN201810026747 A CN 201810026747A CN 110034187 A CN110034187 A CN 110034187A
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- side wall
- fin
- protective layer
- isolation structure
- layer
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- 238000000034 method Methods 0.000 title claims abstract description 88
- 239000004065 semiconductor Substances 0.000 title claims abstract description 64
- 238000002955 isolation Methods 0.000 claims abstract description 174
- 239000011241 protective layer Substances 0.000 claims abstract description 141
- 239000000758 substrate Substances 0.000 claims abstract description 49
- 238000005530 etching Methods 0.000 claims abstract description 38
- 239000010410 layer Substances 0.000 claims description 126
- 239000000463 material Substances 0.000 claims description 40
- 230000004224 protection Effects 0.000 claims description 26
- 238000000151 deposition Methods 0.000 claims description 22
- 230000008569 process Effects 0.000 claims description 19
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 14
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 13
- 239000012528 membrane Substances 0.000 claims description 13
- 229910052710 silicon Inorganic materials 0.000 claims description 13
- 239000010703 silicon Substances 0.000 claims description 13
- 230000008021 deposition Effects 0.000 claims description 11
- 229920002120 photoresistant polymer Polymers 0.000 claims description 11
- 238000005516 engineering process Methods 0.000 claims description 10
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 8
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 8
- 229910052799 carbon Inorganic materials 0.000 claims description 8
- 230000015572 biosynthetic process Effects 0.000 claims description 7
- 238000005229 chemical vapour deposition Methods 0.000 claims description 7
- 238000001039 wet etching Methods 0.000 claims description 6
- 239000007788 liquid Substances 0.000 claims description 5
- 238000005137 deposition process Methods 0.000 claims description 4
- 230000003647 oxidation Effects 0.000 claims description 4
- 238000007254 oxidation reaction Methods 0.000 claims description 4
- 230000008859 change Effects 0.000 claims description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 12
- 239000012530 fluid Substances 0.000 description 6
- 239000000377 silicon dioxide Substances 0.000 description 6
- 229910052732 germanium Inorganic materials 0.000 description 5
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 238000011049 filling Methods 0.000 description 4
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 3
- 230000005669 field effect Effects 0.000 description 3
- 229910052739 hydrogen Inorganic materials 0.000 description 3
- 239000001257 hydrogen Substances 0.000 description 3
- 229920000642 polymer Polymers 0.000 description 3
- 238000012545 processing Methods 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 2
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 125000004429 atom Chemical group 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 239000012459 cleaning agent Substances 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 239000008367 deionised water Substances 0.000 description 2
- 229910021641 deionized water Inorganic materials 0.000 description 2
- 230000003628 erosive effect Effects 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 125000004433 nitrogen atom Chemical group N* 0.000 description 2
- 125000004430 oxygen atom Chemical group O* 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
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- 238000001035 drying Methods 0.000 description 1
- YBMRDBCBODYGJE-UHFFFAOYSA-N germanium oxide Inorganic materials O=[Ge]=O YBMRDBCBODYGJE-UHFFFAOYSA-N 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 150000002431 hydrogen Chemical class 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- PVADDRMAFCOOPC-UHFFFAOYSA-N oxogermanium Chemical compound [Ge]=O PVADDRMAFCOOPC-UHFFFAOYSA-N 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 238000003079 width control Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/7855—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with at least two independent gates
Abstract
A kind of semiconductor structure and forming method thereof, wherein the forming method includes: offer substrate, has fin on the substrate, has opening in the isolated area fin；Initial isolation structure is formed over the substrate, and the initial isolation structure covers the fin side wall, and the initial isolation structure fills the opening；Protective layer is formed on the initial isolation structure of the isolated area, the protective layer sidewall surfaces have side wall；The initial isolation structure is performed etching using the protective layer and side wall as exposure mask, forms the first isolation structure in said opening, and be lower than the fin top surface on the isolation structure surface that the device region forms device region described in the second isolation structure.The forming method can improve semiconductor structure performance.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors more particularly to a kind of semiconductor structure and forming method thereof.
Background technique
With the raising of semiconductor devices integrated level, the critical size of transistor constantly reduces.However, with transistor ruler
Very little strongly reduces, and gate dielectric layer thickness corresponding cannot change the difficulty for making to inhibit short-channel effect to operating voltage and increase, and makes
The channel leakage stream of transistor increases.
The grid of fin formula field effect transistor (Fin Field-Effect Transistor, FinFET) is at similar fin
Forked 3D framework.The channel protrusion substrate surface of FinFET forms fin, and grid covers top surface and the side wall of fin, to make
Inversion layer is formed on each side of channel, can be in the connecting and disconnecting of the two sides control circuit of fin.This design can increase grid
Extremely to the control of channel region, so as to inhibit the short-channel effect of transistor well.However, fin formula field effect transistor is still
So there are short-channel effects.
In addition, reducing channel leakage stream to further decrease influence of the short-channel effect to semiconductor devices.Semiconductor
Technical field introduces strained silicon technology, and the method for strained silicon technology includes: to form groove in the fin of gate structure two sides；
Source and drain doping area is formed in the groove by epitaxial growth technology.In order to reduce the process that fin edge forms the groove
In expose isolation structure around fin, and make to be formed by that source and drain doping plot structure is imperfect, lead to the stress to channel
Reduce, forms pseudo- grid structure at the fin edge before forming the groove.The prior art is in order to improve semiconductor structure
Integrated level, generally on adjacent fin edge and isolation structure formed a dummy gate structure.
However, the performance for the semiconductor structure that the forming method of existing semiconductor structure is formed is poor.
Summary of the invention
Problems solved by the invention is to provide a kind of semiconductor structure and forming method thereof, can improve semiconductor structure
Energy.
To solve the above problems, the present invention provides a kind of forming method of semiconductor structure, comprising: substrate is provided, it is described
There is fin, the fin includes isolated area and the device region positioned at the isolated area two sides, the isolated area fin on substrate
In have opening, it is described opening be parallel to substrate surface and perpendicular on the fin extending direction run through the fin；?
Initial isolation structure is formed on the substrate, the initial isolation structure covers the fin side wall, and the initial isolation junction
Structure fills the opening；Protective layer is formed on the initial isolation structure of the isolated area, the protective layer sidewall surfaces have side
Wall；The initial isolation structure is performed etching using the protective layer and side wall as exposure mask, in the opening formed first every
From structure, and the second isolation structure of covering fin side wall is formed, second isolation structure surface is lower than the fin top
Surface.
Optionally, the material of the protective layer is silica, silicon nitride, silicon oxynitride, agraphitic carbon or amorphous silicon；It is described
The material of side wall is silicon nitride, agraphitic carbon or amorphous silicon.
Optionally, the protective layer is 72 angstroms~88 angstroms in the size on fin extending direction；The protective layer is along vertical
Directly in the size on substrate surface direction be 90 angstroms~110 angstroms.
Optionally, it is formed after the protective layer, forms side wall in the protective layer sidewall surfaces.
Optionally, the step of forming side wall includes: to form side wall layer on the protective layer side wall and top；Described in removal
Side wall layer at the top of protective layer forms side wall.
Optionally, the forming method of the side wall layer includes depositing operation, and the depositing operation includes atomic layer deposition work
Skill, chemical vapor deposition process or physical gas-phase deposition.
Optionally, the protective layer is identical as the material of the side wall layer, the density of the protective layer and side wall layer not phase
Together；Alternatively, the protective layer is not identical as the material of the side wall layer.
Optionally, the side wall with a thickness of 27 angstroms~33 angstroms.
Optionally, the method for forming the protective layer and side wall includes: to be formed on the fin and initial isolation structure
Protect structural membrane；Patterned photoresist is formed in the protection structural membrane, the photoresist, which exposes the isolated area, to be protected
Protection structure film；The protection structural membrane is performed etching using the photoresist as exposure mask, removes the device region protection structural membrane,
Protection structure is formed, the protection structure includes protective layer and the side wall positioned at the protective layer sidewall surfaces.
Optionally, the forming method of the protective layer includes depositing operation, and the depositing operation includes high-density plasma
Body depositing operation, high-aspect-ratio depositing operation or physical gas-phase deposition.
Optionally, the protective layer is along the thickness for being greater than the side wall perpendicular to the size on top surface direction.
Optionally, on the side wall is located at the top of the fin.
Optionally, it is formed after first isolation structure and the second isolation structure, further includes: remove the side wall；It goes
After the side wall, epitaxial layer is formed in the fin.
Optionally, it is formed before the epitaxial layer, further includes: the fin is performed etching, is formed in the fin
Groove；The epitaxial layer is located in the groove.
Optionally, it is formed after the groove, removes the side wall；Alternatively, first isolation structure be also located at it is described
On at the top of fin；It is formed before the groove, removes the side wall.
Optionally, the technique for removing the side wall includes wet-etching technology；The etching liquid for removing the side wall includes HF
Solution, wherein the volumetric concentration of HF is greater than 40%.
Optionally, the initial isolation structure surface is higher than the fin top surface, first isolation structure also position
In on the fin.
Optionally, the first isolation structure on the fin with a thickness of 27 angstroms~30 angstroms；The width of the open top
For 14nm~18nm.
Correspondingly, technical solution of the present invention also provides a kind of semiconductor structure, comprising: substrate has fin on the substrate
Portion, the fin include isolated area and the device region positioned at the isolated area two sides, have opening, institute in the isolated area fin
State opening be parallel to substrate surface and perpendicular on the fin extending direction run through the fin；In the opening
First isolation structure；The second isolation structure of fin side wall is covered, second isolation structure surface is lower than the fin top
Surface；Protective layer and side wall on first isolation structure, the side wall are located at the protective layer side wall.
Optionally, further includes: the epitaxial layer in the fin.
Compared with prior art, technical solution of the present invention has the advantage that
In the forming method for the semiconductor structure that technical solution of the present invention provides, the protective layer side wall has side wall.Institute
Protection to the initial isolation structure of the isolated area can be increased by stating side wall, prevent the initial isolation structure in the opening from being carved
It wears, so as to improve the isolation performance of isolation structure in the opening.
Further, it is formed after isolation structure, removes the side wall, the ruler of side wall limitation subsequent epitaxial layer can be prevented
It is very little, so as to keep the size of epitaxial layer larger, and then the performance of semiconductor structure can be improved.Therefore, the forming method
It can guarantee that the epitaxial layer is larger-size simultaneously, keep the size of the epitaxial layer larger, improve formed semiconductor junction
The performance of structure.
Further, the side wall is located on the initial isolation structure on the fin, and the side wall can be protected positioned at institute
The initial isolation structure at the top of fin is stated, is also located at the first isolation structure at the top of the fin.When etching fin is formed
During groove, the first isolation structure on the fin top can protect the fin of the opening sidewalls, prevent described
Recess sidewall exposes the first isolation structure in the opening, then the recess sidewall can be as the seed for forming epitaxial layer
Layer so as to form the epitaxial layer of structural integrity, and then provides biggish stress for fin, and carrier moves in increase fin
Move rate.
Further, the thickness of the protective layer is greater than the thickness of the side wall, so that after removing the side wall, institute
Stating still has protective layer on isolation structure.The protective layer can protect the isolation in the opening during subsequent technique
Structure.
Further, the protective layer is identical as the material of the side wall layer, the density of the protective layer and side wall layer not phase
Together；Alternatively, the protective layer is not identical as the material of the side wall layer.During removing the side wall, the side wall and guarantor
The etching selection of sheath is bigger, is beneficial to prevent side wall removal not exclusively, causes epitaxial layer too small, and can reduce protective layer
Loss, prevent protective layer too small.
Detailed description of the invention
Fig. 1 to Fig. 3 is a kind of structural schematic diagram of each step of forming method of semiconductor structure；
Fig. 4 to Figure 13 is the structural schematic diagram of each step of one embodiment of forming method of semiconductor structure of the invention.
Specific embodiment
There are problems for the forming method of semiconductor structure, such as: the performance for being formed by semiconductor structure is poor.
Now in conjunction with a kind of forming method of semiconductor structure, analyze semiconductor structure performance that the forming method is formed compared with
The reason of difference:
Fig. 1 to Fig. 3 is a kind of structural schematic diagram of each step of forming method of semiconductor structure.
Referring to FIG. 1, providing substrate 100, there is fin 101 on the substrate 100, there is opening in the fin 101
102, it is described opening 102 along be parallel to 100 surface of substrate and perpendicular on 101 extending direction of fin run through the fin 101.
Referring to FIG. 2, forming initial isolation structure 110 on the substrate 100, the initial isolation structure 110 is covered
101 side wall of fin, and 110 surface of initial isolation structure is higher than or is flush to 101 top surface of fin, it is described
Initial isolation structure 110 fills the opening 102；Protective layer is formed on the initial isolation structure 110 in the opening 102
131。
Referring to FIG. 3, being that exposure mask performs etching the initial isolation structure 110 with the protective layer 131, part is removed
Initial isolation structure 110, forms isolation structure 111；Dummy grid 140, the dummy grid 140 are formed on the protective layer 131
It is upper that there is mask layer；It is formed after isolation structure 111, forms epitaxial layer 150 in the fin 101.
Wherein, in order to improve integrated level, the length of the fin 101 is smaller.If the protective layer 131 is along fin 101
It is oversized on extending direction, it is easy to cause the undersized of the epitaxial layer 150, to influence formed semiconductor structure
Performance, therefore size of the protective layer 131 on 101 extending direction of fin is smaller.Form the initial isolation structure 110
Technique include fluid chemistry gas-phase deposition, between the initial isolation structure 110 that fluid chemistry gas-phase deposition is formed
Gap filling capacity is good, and the isolation performance of the initial isolation structure 110 of formation is preferable.However since chemical vapor deposition process is formed
Initial isolation structure 110 compactness it is poor, and the protective layer 131 is smaller along the size of 101 extending direction of fin, is carving
During losing the initial isolation structure 110, it is easy to cause the isolation structure 111 of 131 lower section of protective layer along fin
It is cut through on 101 extending directions, is collapsed so as to cause the protective layer 131.It is formed after the epitaxial layer 150, the extension
Layer 150 is easy to contact with dummy grid 140, and then causes the leakage current of the semiconductor structure larger.
To solve the technical problem, the present invention provides a kind of forming methods of semiconductor structure, comprising: in the lining
Initial isolation structure is formed on bottom, the initial isolation structure covers the fin side wall；In the initial isolation junction of the isolated area
Protective layer is formed on structure, the protective layer sidewall surfaces have side wall；It is exposure mask to described initial using the protective layer and side wall
Isolation structure performs etching, and forms the first isolation structure and the second isolation structure.The forming method can improve semiconductor junction
Structure performance.
The above objects, features, and advantages of invention can become apparent it is understandable, with reference to the accompanying drawing to of the invention specific
Embodiment is described in detail.
Fig. 4 to Figure 13 is the structural schematic diagram of each step of one embodiment of forming method of semiconductor structure of the present invention.
Fig. 4 and Fig. 5 are please referred to, Fig. 5 is sectional view of the Fig. 4 along cutting line 1-1 ', substrate 200 is provided, on the substrate 200
With fin 201, the fin 201 includes isolated area A and device region B, the isolated area A positioned at the two sides the isolated area A
There is opening, the opening is being parallel to 200 surface of substrate and perpendicular to passing through on 201 extending direction of fin in fin 201
Wear the fin 201.
In the present embodiment, the substrate 200 is silicon substrate.In other embodiments, the substrate can also for germanium substrate,
The semiconductor substrates such as silicon-Germanium substrate, silicon-on-insulator substrate or germanium on insulator.
In the present embodiment, the material of the fin 201 is silicon.In other embodiments, the material of the fin can be with
For germanium or SiGe.
In the present embodiment, the forming step of the substrate 200, the fin 201 and opening includes: offer initial substrate；
Patterned first mask layer is formed in the initial substrate；Using first mask layer as exposure mask to the initial substrate into
Row etching, forms substrate 200 and the fin 201 on substrate 200, and the opening in the fin 201；Form institute
After stating fin 201, first mask layer is removed.
Size of the opening on 201 extending direction of fin is the width of the opening.
If the width of the opening is excessive, it is easily reduced the integrated level of formed semiconductor structure, if the opening
Width it is too small, be easily reduced the isolation performance for the first isolation structure 211 being subsequently formed in opening.Specifically, this implementation
In example, the width of the open top is 14nm~18nm.
In the present embodiment, the material of first mask layer is silicon nitride or silicon oxynitride.
In the present embodiment, the substrate 200 has multiple fins 201 disposed in parallel.In other embodiments, the lining
Can also only have a fin on bottom.
In the present embodiment, the forming method further include: oxidation processes are carried out to the fin 201, form oxide layer.
The curvature that can reduce 201 turning of fin is aoxidized to the fin 201, to reduce fin 201
The point discharge of corner improves the performance of formed semiconductor structure.
The technique of the oxidation processes includes thermal oxidation technology or moisture-generation process in situ.
Referring to FIG. 6, forming initial isolation structure 210 on the substrate 200, the initial isolation structure 210 is covered
201 side wall of fin, and the initial isolation structure 210 is located in the opening.
The initial isolation structure 210 is for being subsequently formed the first isolation structure and the second isolation structure.
In the present embodiment, initial 210 surface of isolation structure be higher than 201 top surface of fin, it is described initially every
It is also located on 201 top of fin from structure 210.
The initial isolation structure 210 is also located on 201 top of the fin, then be subsequently formed the first isolation structure it
Afterwards, first isolation structure is also located on 201 top of fin, during etching the formation of fin 201 groove,
First isolation structure can protect the fin 201 of the opening sidewalls, prevent the groove from exposing in the opening
First isolation structure, and then the electric leakage between epitaxial layer and grid can be reduced.
In other embodiments, the initial isolation structure surface can also be flush to or lower than table at the top of the fin
Face.
In the present embodiment, the material of the initial isolation structure 210 is silica.In other embodiments, described initial
The material of isolation structure may be germanium oxide or silicon oxynitride.
In the present embodiment, the initial isolation structure 210 is formed by fluid chemistry vapor deposition (FCVD) technique.Fluid
The initial isolation structure that chemical vapor deposition process is formed can be sufficient filling with the gap between the opening and adjacent fin.
In the present embodiment, include: by the method that fluid chemistry gas-phase deposition forms the initial isolation structure 210
Presoma is formed on the substrate 200, the presoma is filled in the opening；The presoma is carried out at steam annealing
Reason, activates the presoma, forms initial isolation structure 210.
The presoma has certain mobility, between capable of being sufficient filling between the opening 201 and fin 201
Gap, to form the initial isolation structure 210 for being sufficient filling with gap between the opening 201 and fin 201.The fluid chemistry
The principle of gas-phase deposition are as follows: the presoma be by the former molecular polymer such as silicon, hydrogen, oxygen, nitrogen, it is annealed in steam
Cheng Zhong, hydrogen and nitrogen-atoms in the polymer are replaced to form silica by oxygen atom.However, in steam annealing process, institute
Hydrogen and nitrogen-atoms in polymer is stated to be difficult sufficiently to be replaced by oxygen atom, therefore, chemistry meter in the initial isolation structure 210 of formation
The silica content for measuring ratio is lower, and the consistency of the initial isolation structure 210 of formation is lower, is easy to be etched.
Subsequent that protective layer is formed on the initial isolation structure 210 of the isolated area A, the protective layer side wall has side wall
240。
It in the present embodiment, is formed after the protective layer, forms the side wall for covering the protective layer side wall.
Referring to FIG. 7, forming protective layer 250 on the initial isolation structure 210 of the isolated area A.
The protective layer 250 is used as the exposure mask of the initial isolation structure 210 of subsequent etching.
In order to improve the integrated level of formed semiconductor structure, the opening is in the size on 201 extending direction of fin
It is smaller.
In the present embodiment, the step of forming protective layer 250 includes: in the initial isolation structure 210 and fin 201
Upper formation sacrificial layer, the sacrificial layer expose the initial isolation structure 210 of the isolated area A；The isolated area A initially every
From forming initial protective layers in structure 210 and the sacrificial layer；Planarization process is carried out to the initial protective layers, described in removal
Initial protective layers on sacrificial layer form protective layer 250；It is formed after the protective layer 250, removes the sacrificial layer.
In the present embodiment, the material of the graph layer is photoresist.The photoresist material specifically, the material of the photoresist is positive
Material.In other embodiments, the material of the sacrificial layer can be anti-reflection coating.
The step of forming the sacrificial layer includes: to form initial sacrificial on the initial isolation structure 210 and fin 201
Layer；Processing is exposed to the initial sacrificial layer by light shield, removes the initial sacrificial layer of the isolated area A, is formed and is sacrificed
Layer.
It is formed before initial protective layers, forms the sacrificial layer, be easy the initial isolation junction for exposing the sacrificial layer
Size of the structure 210 on 201 extending direction of fin is smaller, so as to make the protective layer along 201 extending direction of fin
Size is smaller, and then the first isolation structure being subsequently formed can be made smaller along the size of 201 extending direction of fin, to improve
The integrated level of formed semiconductor structure.
The technique for forming the sacrificial layer includes spin coating proceeding.
In the present embodiment, the material of the initial protective layers is silicon nitride.Correspondingly, the material of the protective layer 250 is
Silicon nitride.In other embodiments, the material of the initial protective layers can be silicon oxynitride, agraphitic carbon or amorphous silicon.
In the present embodiment, the technique for forming the initial protective layers includes chemical vapor deposition process.Chemical vapor deposition
The thickness for the protective layer that technique is formed is larger, and protective layer is made to be not easy to be completely removed during subsequent removal side wall.?
In other embodiments, the technique for forming the protective layer includes physical gas-phase deposition.
Size of the protective layer 250 on 201 extending direction of fin is the width of the protective layer 250.
If the width of the protective layer 250 is too small, during being easy to cause the initial isolation structure 210 of subsequent etching,
The initial isolation structure 210 in 250 lower section of protective layer is cut through, and is collapsed so as to cause the protective layer 250, is influenced to form half
The performance of conductor structure；If the width of the protective layer 250 is excessive, it is easily reduced the integrated level of formed semiconductor structure.
Specifically, the width of the protective layer 250 is equal with the width of the open top in the present embodiment.Specifically, the protection
The width of layer 250 is 72 angstroms~88 angstroms, such as 80 angstroms.
The protective layer 250 with a thickness of the protective layer 250 perpendicular to the size in 200 surface direction of substrate.
If the thickness of the protective layer 250 is too small, during subsequent removal side wall, the protective layer 250 is easy quilt
It completely removes, is unfavorable for protecting the first isolation structure in the opening during being subsequently formed groove；If the protection
The thickness of layer 250 is excessive, is easy to increase technology difficulty.Specifically, the protective layer 250 with a thickness of 90 angstroms~110 angstroms, such as
100 angstroms.
In other embodiments, the width of the protective layer can be greater than the width of the open top.
Referring to FIG. 8, forming the side wall 240 for covering 250 side wall of protective layer.
The side wall 240 is used as the exposure mask of initial isolation structure 210 described in subsequent etching, increases at the beginning of the isolated area A
The protection of beginning isolation structure 210 prevents the initial isolation structure 210 in the opening from being cut through, and the protective layer 250 is caused to collapse
It falls into.In addition, the side wall 240 is located on the initial isolation structure 210 on the fin 201, the side wall in the present embodiment
240 can protect the initial isolation structure 210 on 201 top of fin, and the first isolation structure is made to be also located at the fin
On 201 top of portion.During etching fin 201 forms groove, the first isolation structure on 201 top of fin can
The fin 201 for protecting the opening sidewalls prevents the recess sidewall from exposing the first isolation structure in the opening, thus
Reduce the leakage current between the epitaxial layer and dummy grid being subsequently formed.
The step of forming side wall 240 includes: to form side wall layer on 250 side wall of protective layer and top；To institute
It states side wall layer to perform etching, removes the side wall layer on 250 top of protective layer, form side wall 240.
In the present embodiment, the material of the side wall layer is silicon nitride.
In the present embodiment, the technique for forming the side wall layer includes atom layer deposition process.Atom layer deposition process is formed
The thickness of side wall layer be easy to control, so as to prevent 240 thickness of side wall excessive, lead to 201 top of fin being subsequently formed
On the first isolation structure it is oversized on 201 extending direction of fin, lead to the undersized of epitaxial layer, influence to be formed
The performance of semiconductor structure；And the side wall thicknesses can be prevented too small, cause the first isolation structure in the opening to be easy
It is cut through.In other embodiments, the technique for forming the side wall layer includes physical gas-phase deposition.
The side wall 240 is low k silicon nitride, and the protective layer 250 is high k silicon nitride.
The side wall 240 is different from the formation process of protective layer 250, then the density of the side wall 240 and protective layer 250 is not
Together.During the subsequent removal side wall 240, the etching selection of the side wall 240 and protective layer 250 is bigger.
In the present embodiment, the protective layer 250 is identical as the material of the side wall layer, the protective layer 250 and side wall layer
Density it is not identical.
In other embodiments, the protective layer is not identical as the material of the side wall layer.
The protective layer 250 is identical as the material of the side wall layer, the density of the protective layer 250 and side wall layer not phase
Together；Alternatively, the protective layer 250 is not identical as the material of the side wall layer.During removing the side wall 240, the side
Wall 240 and the etching selection of protective layer 250 are bigger, are beneficial to prevent side wall 240 and remove not exclusively, cause to be subsequently formed outer
Prolong that layer is too small, and the loss of protective layer 250 can be reduced, prevents protective layer 250 too small.
In the present embodiment, the side wall 240 is identical as the material of the protective layer 250.In other embodiments, the side
The material of wall can be not identical as the material of the protective layer.The material of the side wall is silicon oxynitride, agraphitic carbon or amorphous
Silicon.
If the thickness of the side wall 240 is too small, it is unfavorable for during preventing the initial isolation structure 210 of subsequent etching,
Initial isolation structure 210 in the opening is cut through；If the thickness of the side wall 240 is excessive, it is easy to make the fin 201
The first isolation structure 211 on top is oversized on 201 extending direction of fin, thus be easy to reduce be subsequently formed it is outer
Prolong the size of layer, and then influences the performance of formed semiconductor structure.Specifically, the side wall 240 with a thickness of 27 angstroms~33
Angstrom, such as 30 angstroms.
Referring to FIG. 9, with the protective layer 250 and side wall 240 for exposure mask to the initial isolation structure 210 (such as Fig. 8 institute
Show) it performs etching, the first isolation structure 211 is formed in said opening, and forms the second isolation junction of covering 201 side wall of fin
Structure 212,212 surface of the second isolation structure are lower than 201 top surface of fin.
It should be noted that since the compactness of the initial isolation structure 210 is poor, to the initial isolation structure
During 210 perform etching, 210 side wall of initial isolation structure of 250 lower section of the side wall 240 and protective layer is easy to be carved
Erosion.Due to having side wall 240 on the initial isolation structure 210, the side wall 240 can increase side wall 240 and protective layer 250
The width of the initial isolation structure 210 of lower section, so that the initial isolation structure 210 in the opening is made to be not easy to be cut through, into
And the isolation performance of the first isolation structure 211 in the opening can be increased.
In addition, the side wall 240 is located on the initial isolation structure 210 on the fin 201, then 240 energy of side wall
Initial isolation structure 210 on the fin 201 of enough protections below, makes the first isolation structure 211 be also located at the fin 201
On.
In the present embodiment, second isolation structure 212 surrounds the fin 201.
In the present embodiment, the technique performed etching to the initial isolation structure 210 includes wet-etching technology.Wet process is carved
The selectivity of erosion is good, it is not easy to damage fin 201.In other embodiments, the work initial isolation structure performed etching
Skill includes dry etch process.
Specifically, it includes hydrofluoric acid that the technological parameter performed etching to the initial isolation structure 210, which includes etching liquid,.
It in the present embodiment, is formed after the protective layer 250, forms the side wall 240.In other embodiments, it is formed
The step of protective layer and side wall includes: that protection structural membrane is formed on the fin and initial isolation structure；In the guarantor
Patterned photoresist is formed on protection structure film, the photoresist exposes the isolated area protection structural membrane；With the photoetching
Glue is that exposure mask performs etching the protection structural membrane, removes the device region protection structural membrane, forms protection structure, the guarantor
Protection structure includes protective layer and the side wall positioned at the protective layer sidewall surfaces.
Referring to FIG. 10, being formed after first isolation structure 211 and the second isolation structure 212, the side wall is removed
240 (as shown in Figure 9).
It is formed after the first isolation structure 211, removes the side wall 240, can prevent side wall 240 from limiting subsequent epitaxial layer
230 size so as to keep the size of epitaxial layer 230 larger, and then can improve the performance of semiconductor structure.In other realities
It applies in example, the forming method can not remove the side wall.
In the present embodiment, the technique for removing the side wall 240 includes wet etching, and wet etching has good selection
Property, loss of the process for removing the side wall to protective layer can be reduced.
In the present embodiment, the etching liquid for removing the side wall 240 includes HF solution, and the volumetric concentration of middle HF is greater than 40%,
Such as 40%~60%.
After removing the side wall 240, further includes: started the cleaning processing by deionized water, remove remaining etching liquid；
It after the cleaning treatment, is dried, removes remaining cleaning agent.
The material of the cleaning agent is deionized water.The step of drying process includes: to be blown in a nitrogen atmosphere
Wind.
It should be noted that the thickness of the protective layer 250 is greater than the thickness of the side wall 240 in the present embodiment, thus
So that after removing the side wall 240 still there is protective layer 250 on first isolation structure 211.250 energy of protective layer
Enough during subsequent etching fin 201 forms groove and etching grid layer, the first isolation junction in the opening is protected
Structure 211.In other embodiments, the thickness of the protective layer is equal with the thickness of the side wall.Formed the first isolation structure it
It afterwards, further include removing the protective layer.
During removing side wall 240, the protective layer 250 can be also lost, and lead to the thickness of the protective layer 250
Degree reduces.Specifically, in the present embodiment, after removing the side wall 240, the protective layer 250 with a thickness of 45 angstroms~55 angstroms,
Such as 50 angstroms.
It is subsequent to form dummy grid on first isolation structure 211.
In this example, the step of forming the dummy grid, is as is illustrated by figs. 11 and 12.
Figure 11 is please referred to, forms grid layer 220 on the fin 201, the first isolation structure 211 and protective layer 250.
The grid layer 220 is for being subsequently formed grid.
The material of the grid layer 220 is polysilicon.In other embodiments, the material of the grid layer can also be more
Brilliant germanium or polycrystalline silicon germanium.
In the present embodiment, the technique for forming the grid layer 220 includes chemical vapor deposition process.In other embodiments
In, the technique for forming the grid layer includes physical gas-phase deposition.
Figure 12 is please referred to, processing is patterned to the grid layer 220, is formed on first isolation structure 211
Dummy grid 222.
The dummy grid 222 for realizing semiconductor devices in adjacent devices area isolation.
In order to improve the integrated level of formed semiconductor structure, the width of the grid is smaller.Specifically, the present embodiment
In, the width of the grid is 14nm~18nm.
In the present embodiment, the dummy grid 222 is located on the protective layer 250.
The step of graphical treatment includes: that patterned second mask layer 221 is formed on the grid layer 220,
Second mask layer 221 covers the grid layer 220 on the protective layer 250；It is exposure mask to institute with second mask layer 221
It states grid layer 220 to perform etching, forms dummy grid 222 on the protective layer 250.
The material of second mask layer 221 is silicon nitride.
The technique performed etching to the grid layer 220 includes dry etch process.Dry etch process has good
Line width control, can effectively control the size of dummy grid 222.
During performing etching to the grid layer 220, the protective layer 250 can be protected first in the opening
Isolation structure 211 reduces the loss of the first isolation structure 211 in opening.
In the present embodiment, the forming method further include: form offset side wall 251 in the dummy grid sidewall surfaces.
The offset side wall 251 is used to be isolated the epitaxial layer 230 and dummy grid 222 being subsequently formed, and reduction, which is formed, partly to be led
The electric leakage of body structure.
The material of the offset side wall 251 is silicon nitride.
It in the present embodiment, is formed before the dummy grid 222, removes the side wall 240.In other embodiments, may be used also
To remove the side wall after forming the dummy grid.
Figure 13 is please referred to, after removing the side wall 240, forms epitaxial layer 230 in the fin 201.
In the present embodiment, the epitaxial layer 230 is used to form the positive or negative pole of diode, the base stage of triode, current collection
Pole or emitter.In other embodiments, the epitaxial layer can be also used for being formed source region or the drain region of MOS transistor.
In the present embodiment, after removing the side wall 240, epitaxial layer 230 is formed in the fin 201, then the side
Wall 240 is without limitation on the size of the epitaxial layer 230, and so as to prevent, epitaxial layer 230 is undersized and influences to form half
The performance of conductor structure.
In the present embodiment, the step of forming epitaxial layer 230 includes: to perform etching to the fin 201, in the fin
Groove is formed in portion 201；Epitaxial layer 230 is formed in the groove.
It should be noted that since first isolation structure 211 is also located on the fin 201, it is described recessed being formed
During slot, the first isolation structure 211 on the fin 201 can protect the fin 201 of the opening sidewalls, so as to
Enough prevent the recess sidewall from exposing the first isolation structure 211, prevent between the epitaxial layer 230 and dummy grid 222 away from
From too small, and then electric leakage can be reduced.In addition, since the recess sidewall is not easy to expose first isolation structure 211,
Then the recess sidewall can be as the seed layer for forming epitaxial layer 230, so as to form the epitaxial layer of structural integrity
230, and then biggish stress is provided for fin 201, increase the migration rate of carrier in fin 201.
In the present embodiment, the top surface of the epitaxial layer 230 is higher than 211 top table of the first isolation structure in the opening
Face.The top surface of the extension, which is higher than 211 top surface of the first isolation structure in the opening, can increase epitaxial layer 230
Size, so that increasing epitaxial layer 230 is the stress that fin 201 provides.Due to the first isolation structure 211 on the fin 201
Upper not have side wall 240, then during forming epitaxial layer 230, the epitaxial layer 230 is also located on the fin 201
On first isolation structure 211, so as to increase the size of epitaxial layer 230.
In the present embodiment, formed the groove technique include one of dry etch process and wet-etching technology or
Two kinds of combinations.
In the present embodiment, the technique for forming the epitaxial layer 230 includes epitaxial growth technology.
The material of the epitaxial layer is silicon, germanium or SiGe.
In the present embodiment, the epitaxial layer 230 is used to form the current collection of the positive or negative pole of diode, the triode
Pole, emitter or base stage.In other embodiments, the epitaxial layer can be used for being formed source region or the drain region of MOS transistor.Shape
After first isolation structure and the second isolation structure, formed before epitaxial layer further include: on the device region substrate
Form gate structure；The epitaxial layer is located at the gate structure two sides.
3 are continued to refer to figure 1, the embodiment of the present invention also provides a kind of semiconductor structure, comprising: substrate 200, the substrate
There is fin 201 on 200, the fin 201 includes isolated area A and the device region B positioned at the two sides the isolated area A, it is described every
From having opening in area's A fin 201, the opening is being parallel to 200 surface of substrate and perpendicular to 201 extending direction of fin
It is upper to run through the fin 201；The first isolation structure 211 in the opening；Cover the second of 201 side wall of fin every
From structure 212,212 surface of the second isolation structure is lower than 201 top surface of fin；Positioned at the isolated area A first
Protective layer 250 and side wall 240 on isolation structure 211, the side wall 240 are located at 250 side wall of protective layer.
The semiconductor structure further include: the epitaxial layer 230 in the fin 201.
The material of the protective layer 250 is silicon nitride, silica, agraphitic carbon or amorphous silicon；The material of the side wall 240
For silicon nitride, silica, agraphitic carbon or amorphous silicon.
The protective layer 250 along perpendicular to the size on 200 direction of substrate be 45 angstroms~55 angstroms；The thickness of the side wall 240
Degree is 27 angstroms~33 angstroms, such as 30 angstroms.
In the present embodiment, second isolation structure 212 surrounds the fin 201.
Although present disclosure is as above, present invention is not limited to this.Anyone skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (20)
1. a kind of forming method of semiconductor structure characterized by comprising
Substrate is provided, there is fin on the substrate, the fin includes isolated area and the device positioned at the isolated area two sides
Area, has opening in the isolated area fin, and the opening is being parallel to substrate surface and perpendicular to the fin extending direction
It is upper to run through the fin；
Initial isolation structure is formed over the substrate, and the initial isolation structure covers the fin side wall, and described initial
Isolation structure fills the opening；
Protective layer is formed on the initial isolation structure of the isolated area, the protective layer sidewall surfaces have side wall；
The initial isolation structure is performed etching using the protective layer and side wall as exposure mask, in the opening formed first every
From structure, and the second isolation structure of covering fin side wall is formed, second isolation structure surface is lower than the fin top
Surface.
2. the forming method of semiconductor structure as described in claim 1, which is characterized in that the material of the protective layer is oxidation
Silicon, silicon nitride, silicon oxynitride, agraphitic carbon or amorphous silicon；The material of the side wall is silicon nitride, agraphitic carbon or amorphous silicon.
3. the forming method of semiconductor structure as described in claim 1, which is characterized in that the protective layer extends along fin
Size on direction is 72 angstroms~88 angstroms；The protective layer edge is 90 angstroms~110 angstroms perpendicular to the size on substrate surface direction.
4. the forming method of semiconductor structure as described in claim 1, which is characterized in that it is formed after the protective layer,
The protective layer sidewall surfaces form side wall.
5. the forming method of semiconductor structure as claimed in claim 4, which is characterized in that formed side wall the step of include:
Side wall layer is formed on the protective layer side wall and top；The side wall layer at the top of the protective layer is removed, side wall is formed.
6. the forming method of semiconductor structure as claimed in claim 5, which is characterized in that the forming method packet of the side wall layer
Depositing operation is included, the depositing operation includes atom layer deposition process, chemical vapor deposition process or physical gas-phase deposition.
7. the forming method of semiconductor structure as claimed in claim 5, which is characterized in that the protective layer and the side wall layer
Material it is identical, the density of the protective layer and side wall layer is not identical；Alternatively, the material of the protective layer and the side wall layer is not
It is identical.
8. the forming method of semiconductor structure as described in claim 1, which is characterized in that the side wall with a thickness of 27 angstroms~
33 angstroms.
9. the forming method of semiconductor structure as described in claim 1, which is characterized in that form the protective layer and side wall
Method includes: that protection structural membrane is formed on the fin and initial isolation structure；Figure is formed in the protection structural membrane
The photoresist of change, the photoresist expose the isolated area protection structural membrane；It is exposure mask to the protection using the photoresist
Structural membrane performs etching, and removes device region protection structural membrane, forms protection structure, the protection structure include protective layer with
Positioned at the side wall of the protective layer sidewall surfaces.
10. the forming method of the semiconductor structure as described in claim 5 or 9, which is characterized in that the formation side of the protective layer
Method includes depositing operation, and the depositing operation includes high-density plasma deposition process, high-aspect-ratio depositing operation or physics
Gas-phase deposition.
11. the forming method of semiconductor structure as claimed in claim 9, which is characterized in that the protective layer is along perpendicular to lining
Size on the top surface direction of bottom is greater than the thickness of the side wall.
12. the forming method of semiconductor structure as described in claim 1, which is characterized in that the side wall is located at the fin
On top.
13. the forming method of semiconductor structure as described in claim 1, which is characterized in that form first isolation structure
After the second isolation structure, further includes: remove the side wall；After removing the side wall, extension is formed in the fin
Layer.
14. the forming method of semiconductor structure as claimed in claim 13, which is characterized in that it is formed before the epitaxial layer,
Further include: the fin is performed etching, forms groove in the fin；The epitaxial layer is located in the groove.
15. the forming method of semiconductor structure as claimed in claim 14, which is characterized in that formed after the groove, gone
Except the side wall；
Alternatively, first isolation structure is also located at the top of the fin；It is formed before the groove, removes the side wall.
16. the forming method of semiconductor structure as claimed in claim 13, which is characterized in that remove the technique packet of the side wall
Include wet-etching technology；The etching liquid for removing the side wall includes HF solution, and wherein the volumetric concentration of HF is greater than 40%.
17. the forming method of semiconductor structure as described in claim 1, which is characterized in that the initial isolation structure surface
Higher than the fin top surface, first isolation structure is also located on the fin.
18. the forming method of semiconductor structure as claimed in claim 17, which is characterized in that the first isolation on the fin
Structure with a thickness of 27 angstroms~30 angstroms；The width of the open top is 14nm~18nm.
19. a kind of semiconductor structure characterized by comprising
Substrate has fin on the substrate, and the fin includes isolated area and the device region positioned at the isolated area two sides, institute
Stating has opening in isolated area fin, the opening is being parallel to substrate surface and perpendicular to running through on the fin extending direction
The fin；
The first isolation structure in the opening；
The second isolation structure of fin side wall is covered, second isolation structure surface is lower than the fin top surface；
Protective layer and side wall on first isolation structure, the side wall are located at the protective layer side wall.
20. semiconductor structure as claimed in claim 19, which is characterized in that further include: the epitaxial layer in the fin.
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