CN110707041A - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

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Publication number
CN110707041A
CN110707041A CN201910973259.7A CN201910973259A CN110707041A CN 110707041 A CN110707041 A CN 110707041A CN 201910973259 A CN201910973259 A CN 201910973259A CN 110707041 A CN110707041 A CN 110707041A
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layer
mask
forming
isolation
region
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余兴
蒋维楠
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Yangtze Delta Region Institute of Tsinghua University Zhejiang
ICLeague Technology Co Ltd
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Yangtze Delta Region Institute of Tsinghua University Zhejiang
ICLeague Technology Co Ltd
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Priority to CN201910973259.7A priority Critical patent/CN110707041A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

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  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

A semiconductor structure and a forming method thereof are provided, wherein the forming method comprises the following steps: providing a substrate, wherein the substrate is provided with a fin part, the fin part comprises a first area, a second area and a third area, the second area and the third area are respectively positioned at two sides of the first area, and the first area, the second area and the third area are arranged along the extending direction of the fin part; forming a groove in the first region, wherein the groove penetrates through the fin part along a direction perpendicular to the extending direction of the fin part; forming an isolation layer in the groove, wherein the isolation layer is also positioned on part of the top surface of the second region and part of the top surface of the third region; and forming epitaxial layers in the second region and the third region of the fin part, wherein the epitaxial layers are respectively positioned at two sides of the isolation layer and are adjacent to the isolation layer. The forming method can obtain the isolation layer which completely fills the groove of the first region of the fin part, thereby improving the isolation performance of the isolation layer and further improving the performance of the formed semiconductor structure.

Description

Semiconductor structure and forming method thereof
Technical Field
The present invention relates to the field of semiconductor technology, and more particularly, to a semiconductor structure and a method for forming the same.
Background
With the increase of the integration level of semiconductor devices, the critical dimension of transistors is continuously reduced, which weakens the control capability of the gate on channel current, thereby generating a short channel effect and further affecting the electrical performance of the semiconductor devices.
The grid of a fin field effect transistor (FinFET) is in a fork-shaped 3D structure similar to a fish fin. A fin part is formed by the protrusion of the channel of the FinFET out of the surface of the substrate, and the grid electrode covers the top surface and the side wall of the fin part, so that an inversion layer is formed on each side of the channel, and the connection and disconnection of circuits can be controlled on two sides of the fin part. The design can increase the control of the gate to the channel region, thereby well inhibiting the short-channel effect of the transistor. However, the short channel effect still exists in the fin field effect transistor.
In addition, in order to further reduce the influence of the short channel effect on the semiconductor device, the channel leakage current is reduced. The technical field of semiconductors introduces a strained silicon technology, and the method of the strained silicon technology comprises the following steps: forming grooves in the fin parts on two sides of the grid structure; and forming a source drain doped region in the groove by an epitaxial growth process. In order to reduce the exposure of the isolation structure around the fin part in the process of forming the groove at the edge of the fin part and ensure that the structure of the formed source-drain doped region is incomplete, so that the stress on a channel is reduced, and a pseudo-gate structure is formed at the edge of the fin part before the groove is formed. In order to improve the integration of the semiconductor structure, a dummy gate structure is generally formed on the edge of the adjacent fin and the isolation structure.
However, the performance of the semiconductor structure formed by the conventional method for forming the semiconductor structure is poor.
Disclosure of Invention
The invention provides a semiconductor structure and a forming method thereof, which can improve the performance of the semiconductor structure.
To solve the above technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein the substrate is provided with a fin part, the fin part comprises a first area, a second area and a third area, the second area and the third area are respectively positioned at two sides of the first area, and the first area, the second area and the third area are arranged along the extending direction of the fin part; forming a groove in the first region, wherein the groove penetrates through the fin part along a direction perpendicular to the extending direction of the fin part; forming an isolation layer in the groove, wherein the isolation layer is also positioned on part of the top surface of the second region and part of the top surface of the third region; and forming epitaxial layers in the second region and the third region of the fin part, wherein the epitaxial layers are respectively positioned at two sides of the isolation layer and are adjacent to the isolation layer.
Optionally, the method further includes: and forming an isolation structure on the substrate, wherein the isolation structure is positioned on the partial side wall surface of the fin part, and the surface of the isolation structure is lower than the top surface of the fin part.
Optionally, the method for forming the isolation structure and the isolation layer includes: forming an initial isolation material layer on the substrate, wherein the initial isolation material layer is also positioned on the side wall and the top surface of the fin part, and the surface of the initial isolation material layer is higher than the top surface of the fin part; forming a first mask structure on the surface of the initial isolation material layer, wherein the first mask structure is located on the first region of the fin portion and further extends to a part of the second region and a part of the third region; etching the initial isolation material layer by taking the first mask structure as a mask until the side wall surface of part of the fin part is exposed to form the isolation structure and the isolation layer; after the isolation structure and the isolation layer are formed, the first mask structure is removed.
Optionally, the first mask structure includes: the mask layer structure comprises a first mask layer positioned on the surface of the initial isolation material layer and a second mask layer positioned on the surface of the first mask layer.
Optionally, the material of the second mask layer is different from the material of the first mask layer; the material of the first mask layer is different from the material of the initial isolation material layer.
Optionally, the second mask layer is made of silicon nitride; the first mask layer is made of silicon oxide.
Optionally, the method for forming the first mask structure includes: forming a first mask material film on the surface of the initial isolation material layer; forming a second mask material film on the surface of the first mask material film; forming a patterned layer on the surface of the second mask material film, wherein the patterned layer is located on the first region of the fin portion and further extends to a part of the second region and a part of the third region; and etching the second mask material film and the first mask material film by taking the patterning layer as a mask until the surface of the initial isolation material layer is exposed.
Optionally, the patterned layer comprises a patterned photoresist layer.
Optionally, the method further includes: and before the isolation layer is formed, forming a liner layer on the surface of the side wall of the fin part and the surface of the substrate.
Optionally, the top surface of the fin portion has a second mask structure; the method for forming the fin portion comprises the following steps: providing an initial substrate; forming a second mask structure on the surface of the part of the initial substrate; and etching the initial substrate by taking the second mask structure as a mask to form the fin part.
Optionally, the second mask structure includes: a third mask layer; the third mask layer is made of silicon nitride.
Optionally, the method for forming the initial isolation material layer includes: depositing a first isolation material layer on the substrate and on the side walls and the top surface of the fin part; planarizing the first isolation material layer until the surface position of the second mask structure is exposed; back etching the first isolation material layer; and removing the third mask layer of the second mask structure.
Optionally, the method for forming the initial isolation material layer further includes: and after removing the third mask layer, forming a second isolation material layer on the first isolation material layer.
Optionally, the second mask structure further includes: a fourth mask layer located between the third mask layer and the surface of the initial substrate; the fourth mask layer is made of silicon oxide.
Optionally, the second mask structure further includes: a fifth mask layer positioned on the surface of the third mask layer; the fifth mask layer is made of silicon oxide.
Optionally, before forming the epitaxial layer, the method further includes: forming a gate structure crossing the fin portion; and forming a dummy gate structure on the isolation layer.
Optionally, after the gate structure and the dummy gate structure are formed, the epitaxial layer is formed in the fin portions on two sides of the gate structure respectively.
Optionally, the method for forming the epitaxial layer includes: etching the second region and the third region of the fin part, and forming an opening in the fin part on two sides of the grid structure; an epitaxial layer is formed in the opening.
The present invention also provides a semiconductor structure, comprising: the structure comprises a substrate, wherein a fin part is arranged on the substrate, the fin part comprises a first area, a second area and a third area, the second area and the third area are respectively positioned on two sides of the first area, and the first area, the second area and the third area are arranged along the extending direction of the fin part; the groove is positioned in the first region of the fin part and penetrates through the fin part along the direction perpendicular to the extending direction of the fin part; an isolation layer located within the recess, the isolation layer also located at a portion of the top surface of the second region and at a portion of the top surface of the third region; the epitaxial layer is respectively positioned in the second region and the third region of the fin portion on two sides of the isolation layer, and the epitaxial layer is adjacent to the isolation layer.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:
in the method for forming the semiconductor structure provided by the technical scheme of the invention, the isolation layer is formed in the groove of the first region of the fin part, and the isolation layer also covers part of the top surface of the second region of the fin part and part of the top surface of the third region of the fin part, so that the top of the formed isolation layer is higher than the top surface of the fin part, thereby improving the isolation performance of the formed isolation layer and further improving the performance of the formed semiconductor structure.
In the semiconductor structure provided by the technical scheme of the invention, the isolation layer is positioned in the groove of the first region of the fin part and covers partial top surfaces of the second region and the third region of the fin part, so that the isolation performance of the formed isolation layer can be improved, and the performance of the formed semiconductor structure is further improved.
Drawings
FIG. 1 is a schematic diagram of a semiconductor structure;
fig. 2 to 13 are schematic structural diagrams of steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Detailed Description
As known from the background art, in order to form complete source/drain doped regions on both sides of a gate structure, a dummy gate structure is generally formed on the edge of an adjacent fin and an isolation structure.
Fig. 1 is a schematic structural diagram of a semiconductor structure.
Referring to fig. 1, the top of the isolation structure 11 in the FinFET is usually lower than the top surface of the fin 20, the isolation performance of the isolation structure 11 is not good, and the adjacent source-drain doped regions 12 in the fin are easily bridged, resulting in leakage current; moreover, the bottom of the dummy gate structure 21 formed on the isolation structure is sunk in the fin portion, which is different from the structure of the gate structure 22 on the fin portion, resulting in different stress environments, so that the surface of the substrate 10 is subjected to different stresses, which may cause the substrate to bend, thereby adversely affecting the performance of the semiconductor structure.
In order to solve the problems, a method for forming a semiconductor structure is provided, wherein a groove is formed in a first region of a fin portion, an isolation layer is formed in the groove, and the isolation layer is also positioned on partial top surfaces of a second region and a third region of the fin portion; on the other hand, the bottom of a pseudo gate structure formed on the isolation layer subsequently is prevented from falling into the fin portion, so that the pseudo gate structure is basically consistent with the structure of the gate structure formed on the fin portion, epitaxial layers formed on two sides of the gate structure subsequently are in the same or similar stress environment, and the performance of the semiconductor structure is improved.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 2 to 13 are schematic structural diagrams of steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Referring to fig. 2, a substrate 100 is provided, the substrate 100 has a fin 200 thereon, the fin includes a first region 201, and a second region 202 and a third region 203 respectively located at two sides of the first region 201, and the first region 201, the second region 202, and the third region 203 are arranged along an extending direction of the fin.
In this embodiment, the substrate 100 has a plurality of fins 200 thereon, and the extending directions of the plurality of fins 200 are parallel.
In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the substrate 100 may also be a semiconductor substrate such as a germanium substrate, a silicon-on-insulator substrate, or a germanium-on-insulator substrate.
In this embodiment, the fin 200 is made of silicon. In other embodiments, the material of the fin 200 may also be germanium or silicon germanium.
With continued reference to fig. 2, in the present embodiment, the top surface of the fin 200 has a second mask structure 300.
The method of forming the fin 200 includes: providing an initial substrate (not shown); forming a second mask structure 300 on the part of the initial substrate surface; and etching the initial substrate by using the second mask structure 300 as a mask to form the fin portion 200.
In this embodiment, the second mask structure 300 includes a third mask layer 301 and a fourth mask layer 302 located between the third mask layer 301 and the initial substrate surface.
In other embodiments, the second mask structure 300 may further include a fifth mask layer on the third mask layer 301, and the material of the fifth mask layer is the same as that of the fourth mask layer 302.
The material of the third mask layer 301 is different from the material of the fourth mask layer 302. In this embodiment, the third mask layer 301 is made of silicon nitride, and the fourth mask layer 302 is made of silicon oxide.
The fourth mask layer 302 serves to increase the adhesion of the third mask layer 301 and protect the fin portion from being damaged during subsequent removal of the third mask layer.
With continued reference to fig. 2, after the fin 200 is formed, a groove 210 is formed in the first region 201 of the fin 200, and the groove 210 penetrates through the fin 200 along a direction perpendicular to the extending direction of the fin 200.
The method of forming the groove 210 includes: patterning the third mask layer 301 and the fourth mask layer 302; and etching the fin part 200 by using the patterned third mask layer 301 and the patterned fourth mask layer 302 as masks to form the groove 210.
After the grooves 210 are formed, an isolation structure is formed on the substrate 100, and the isolation structure is located on a portion of the sidewall surface of the fin portion 200, and the surface of the isolation structure is lower than the top surface of the fin portion 200; and forming an isolation layer within the recess 210, the isolation layer also being located at a portion of the top surface of the second region 202 and at a portion of the top surface of the third region 203.
The steps of forming the isolation structure and the isolation layer are shown in fig. 3 to 10.
Referring to fig. 3, a first isolation material layer 111 is deposited on the substrate 100 and on the sidewalls and the top surface of the fin 200, and the surface of the first isolation material layer 111 is higher than the top surface of the fin 200 and completely covers the second mask structure 300.
In this embodiment, the first isolation material layer 111 is made of silicon oxide; in other embodiments, the material of the first isolation material layer 111 may also be silicon oxynitride.
In this embodiment, the first isolation material layer 111 is formed by a fluid chemical vapor deposition process. The first isolation material layer 111 formed by the fluid chemical vapor deposition process has strong filling capability on gaps and grooves between adjacent fins 200, and the isolation performance of the formed first isolation material layer 111 is good. In other embodiments, the process of forming the first isolation material layer 111 may also be a plasma enhanced chemical vapor deposition process.
It should be noted that, in this embodiment, before depositing the first isolation material layer 111, a liner layer 112 is further formed on the sidewall surface of the fin 200 and the surface of the substrate 100 (refer to fig. 7). The liner layer 112 can increase the adhesion of the initial spacer material layer, making deposition of the initial spacer material layer easier.
In this embodiment, the liner layer 112 is made of silicon oxide; in other embodiments, the material of the liner layer 112 may also be silicon oxynitride.
In this embodiment, the liner layer 112 is formed by an in-situ water vapor generation process. The liner layer 112 formed by the in-situ water vapor generation process has fewer defects and better performance. In other embodiments, the process of forming the liner layer 112 may also be a high density plasma method.
Referring to fig. 4, the first isolation material layer 111 is planarized until the top surface locations of the second mask structure 300 are completely exposed.
In this embodiment, the process parameters for planarizing the first isolation material layer 111 include: using CeO2The grinding pressure of the grinding fluid used as the raw material is 3 psi-12 psi. Using CeO2As a polishing raw material, a high selectivity ratio of silicon nitride to silicon oxide can be achieved.
In this embodiment, the third mask layer 301 serves as a polishing stop layer during the planarization process, so that excessive loss of the first isolation material layer 111 in the groove 210 due to over-polishing is avoided, and the top of the subsequently formed isolation layer is lower than the top surface of the fin portion, thereby affecting the isolation effect.
Referring to fig. 5, the first isolation material layer 111 is etched back until the third mask layer 301 is completely exposed.
In this embodiment, the first isolation material layer 111 is etched back by a dry etching method. By etching back the first isolation material layer 111 by a dry etching method, the height of the first isolation material layer can be better controlled, so that the top surface of the first isolation material layer 111 is flush with the top surface of the fourth mask layer 302, and the height of a subsequently formed isolation layer can be controlled.
Referring to fig. 6, the third mask layer 301 is removed.
After removing the third mask layer 301, the first isolation material layer 111 and the fourth mask layer 302 form an initial isolation material layer 110, and the fourth mask layer 302 serves as a part of a subsequently formed isolation layer. The initial isolation material layer 110 is located on the sidewalls and the top surface of the fin 200, and the surface of the initial isolation material layer 110 is higher than the top surface of the fin 200.
The initial isolation material layer 110 is used for the subsequent formation of the isolation structure and the isolation layer.
In this embodiment, the method for removing the third mask layer 301 is dry etching. Since the material of the initial isolation material layer 110 is different from the material of the third mask layer 301, when the third mask layer 301 is removed by etching, the initial isolation material layer 110 is not etched, and the fin 200 can be protected from being affected.
In this embodiment, the step of forming the initial isolation material layer 110 further includes forming a second isolation material layer (not shown) on the first isolation material layer 111. In other embodiments, the second isolation material layer may not be formed.
The second isolation material layer is formed to enable the height of the subsequently formed isolation layer higher than the top surface of the fin portion to be higher, so that the isolation capability of the formed isolation layer is improved, and the bridging prevention capability is better.
The second isolation material layer is made of the same material as the first isolation material layer. In this embodiment, the second isolation material layer is made of silicon oxide. In other embodiments, the material of the second isolation material layer may also be silicon oxynitride.
After the initial isolation material layer 110 is formed, a first mask structure is formed on the surface of the initial isolation material layer 110, wherein the first mask structure comprises a first mask layer and a second mask layer.
The steps for forming the first mask structure are shown in fig. 7 to 9.
Referring to fig. 7, a first mask material film 410 is formed on the surface of the initial isolation material layer 110; forming a second mask material film 420 on the surface of the first mask material film 410; a patterned layer 430 is formed on the surface of the second mask material film 420, the patterned layer 430 is located on the first region 201 of the fin 200, and the patterned layer 430 further extends to a portion of the second region 202 and a portion of the third region 203.
In this embodiment, the material of the first mask material film 410 is different from the material of the second mask material film 420, and the material of the first mask material film 410 is different from the material of the initial isolation material layer 110.
In this embodiment, the first mask material film 410 is made of silicon nitride; in other embodiments, the first mask material film 410 may also be a polymer, a carbon compound, metal tungsten, aluminum oxide, hafnium oxide, or other materials different from the material of the second mask material film 420.
In this embodiment, the material of the second mask material film 420 is silicon oxide; in other embodiments, the second mask material film 420 may also be made of silicon carbide, carbon compound, aluminum oxide, hafnium oxide, or other materials different from the material of the first mask material film 410.
This is because the first mask layer and the second mask layer are required to have an etching selectivity ratio in a subsequent etching process, and thus the material 410 of the first mask material film and the material 420 of the second mask material film cannot be the same.
The first mask material film 410 is formed by chemical vapor deposition or physical vapor deposition, and the second mask material film 420 is formed by chemical vapor deposition or physical vapor deposition.
In this embodiment, the patterned layer 430 is a patterned photoresist layer; in other embodiments, the patterned layer may also be other materials different from the material of the second mask material film 420, such as silicon nitride, carbon compound, etc.
In this embodiment, the second mask material film 420 may increase adhesion between the first mask material film 410 and the patterned layer 430, and may transfer the pattern of the patterned layer 430 to the first mask material film 410.
Referring to fig. 8, the second mask material film 420 is etched using the patterned layer 430 as a mask until the surface of the first mask material film 410 is exposed, thereby forming a second mask layer 402.
In this embodiment, the method for etching the second mask material film 420 is dry etching.
Since the material of the first mask material film 410 is different from the material of the second mask material film 420, there is an etching selectivity ratio, when the second mask material film 420 is etched, the first mask material film 410 is not eroded, and the underlying initial isolation material layer 110 is prevented from being damaged.
Referring to fig. 9, the patterned layer 430 is removed, and the first mask material film 410 is etched using the second mask layer 402 as a mask until the surface of the initial isolation material layer 110 is exposed, thereby forming a first mask layer 401.
The first mask structure 400 includes the first mask layer 401 and the second mask layer 402, the first mask structure 400 is located on the first region 201 of the fin 200, and the first mask structure 400 further extends to a portion of the second region 202 and a portion of the third region 203.
In this embodiment, the method for etching the first mask material film 410 is dry etching.
Since the material of the first mask material film 410 is different from the material of the initial isolation material layer 110, there is an etching selectivity ratio, and the initial isolation material layer 110 is not affected when the first mask material film 410 is etched.
Referring to fig. 10, after the first mask structure 400 is formed, the initial isolation material layer 110 is etched by using the first mask structure 400 as a mask until the sidewall surfaces of some of the fins are exposed, so as to form the isolation structure 120 and the isolation layer 130.
It should be noted that, in this embodiment, since the material of the second mask layer 402 is the same as the material of the initial isolation material layer 110, the second mask layer 402 is removed simultaneously when the initial isolation material layer 110 is etched.
Therefore, the initial isolation material layer 110 is etched by using the first mask layer 401 in the first mask structure 400 as a mask.
In this embodiment, the method for etching the initial isolation material layer 110 is isotropic dry etching.
The isotropic dry etching has the same etching rate in each direction, and since the material of the first mask layer 401 is different from the material of the initial isolation material layer 110, when the initial isolation material layer 110 is etched, the first mask layer 401 and the first mask layer cover the first region and a part of the initial isolation material layer of the second region and the third region are not etched, so that the isolation layer 130 is formed in the groove 210, and the isolation layer 130 also covers a part of the top surface of the second region 202 and a part of the top surface of the third region 203.
Referring to fig. 11 and 12, fig. 12 is a perspective view of fig. 11, and fig. 11 is a cross-sectional view of fig. 12 along a dotted line AA, after the isolation structure 120 and the isolation layer 130 are formed, the first mask structure 400 is removed. Specifically, the first mask layer 401 in the first mask structure 400 is removed.
In this embodiment, the method for removing the first mask layer 401 is dry etching.
Since the first mask structure 400 is located on the first region 201 of the fin 200, and the first mask structure 400 further extends to a portion of the second region 202 and a portion of the third region 203, the formed isolation layer 130 completely fills the groove 210 in the first region 201, and the isolation layer 130 further covers a portion of top surfaces of the second region 202 and the third region 203, and a top of the isolation layer 130 is higher than the top surface of the fin 200. The isolation layer 130 can avoid bridging between adjacent source and drain regions formed in the fin portion subsequently, so that a leakage current phenomenon is prevented, and isolation capability is better; in addition, a dummy gate structure is formed on the isolation layer 130 in the following step, the dummy gate structure and the gate structure formed on the fin portion have the same structure, and the stress environment is the same or similar, so that the substrate is subjected to the same stress, the substrate is prevented from being bent, and the performance of the semiconductor structure is improved.
Referring to fig. 13, after the isolation structure 120 and the isolation layer 130 are formed, a gate structure 220 crossing the fin 200 is formed, wherein the gate structure 220 covers a portion of the sidewall and the top surface of the fin 200; a dummy gate structure 230 is formed on the isolation layer 130, and an extending direction of the dummy gate structure 230 is the same as an extending direction of the gate structure 220.
With reference to fig. 13, after the gate structure 220 and the dummy gate structure 230 are formed, the epitaxial layer 221 is formed in the fin 200 on both sides of the gate structure 220.
In this embodiment, the process of forming the epitaxial layer 221 includes an epitaxial growth process. The epitaxial layer 221 is made of silicon, germanium or silicon germanium.
In this embodiment, the epitaxial layer 221 is used to form a source region and a drain region.
In this embodiment, the step of forming the epitaxial layer 221 includes: etching the second region 202 and the third region 203 of the fin 200, and forming an opening (not shown) in the fin 200 on both sides of the gate structure 220; the epitaxial layer 221 is formed in the opening by an epitaxial growth process.
Before forming the openings in the fin 200 on both sides of the gate structure 220, since the isolation layer 130 covers part of the top surfaces of the second region and the third region, the isolation layer 130 in the opening region to be formed later needs to be etched away, and then the fin 200 is etched to form the openings.
Because the isolation layer 130 has a large size, and the top surface of the isolation layer 130 is higher than the top surface of the fin portion 200, when the epitaxial layer 221 is formed in the opening, even if a spreading condition occurs, the isolation layer 130 still has a good isolation effect, and the occurrence of bridging between adjacent epitaxial layers is avoided, so that leakage current is prevented.
In this embodiment, the gate structure 220 is located at two sides of the dummy gate structure 230; the epitaxial layer 221 is located in the fin 200 at two sides of the dummy gate structure 230.
In this embodiment, the surface of the isolation layer 130 is higher than the top surface of the fin 200, so that the isolation layer 130 can prevent the adjacent epitaxial layers 221 from contacting during the process of forming the epitaxial layers 221, thereby ensuring the performance of the formed semiconductor structure.
With continued reference to fig. 13, the present invention also provides an embodiment of a semiconductor structure comprising: the substrate 100 is provided with a fin portion 200, the fin portion 200 comprises a first region 201, a second region 202 and a third region 203, the second region 202 and the third region 203 are respectively located on two sides of the first region 201, and the first region 201, the second region 202 and the third region 203 are arranged along the extending direction of the fin portion; a recess 210 located in the first region 201 of the fin 200 and penetrating through the fin 200 along a direction perpendicular to the extending direction of the fin 200; an isolation layer 130 located within the recess 210, the isolation layer 210 further located at a portion of the top surface of the second region 202 and a portion of the top surface of the third region 203; the epitaxial layer 221 is respectively located in the second region 202 and the third region 203 of the fin 200 at two sides of the isolation layer 130, and the epitaxial layer 221 is adjacent to the isolation layer 130.
In this embodiment, the semiconductor structure further includes: an isolation structure 120 on the substrate 100, wherein the isolation structure 120 is located on a portion of a sidewall surface of the fin 200, and a surface of the isolation structure 120 is lower than a top surface of the fin 200.
In this embodiment, the semiconductor structure further includes: a gate structure 220 spanning the fin 200, the gate structure 220 covering a portion of the sidewalls and top surface of the fin 200; a dummy gate structure 230 on the isolation layer 130, wherein the dummy gate structure 230 extends in the same direction as the gate structure 220.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (19)

1. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein a fin part is arranged on the substrate, the fin part comprises a first region, a second region and a third region, the second region and the third region are respectively positioned at two sides of the first region, and the first region, the second region and the third region are arranged along the extending direction of the fin part;
forming a groove in the first region, wherein the groove penetrates through the fin part along a direction perpendicular to the extending direction of the fin part;
forming an isolation layer in the groove, wherein the isolation layer is also positioned on part of the top surface of the second region and part of the top surface of the third region;
and forming epitaxial layers in the second region and the third region of the fin part, wherein the epitaxial layers are respectively positioned at two sides of the isolation layer and are adjacent to the isolation layer.
2. The method of forming a semiconductor structure of claim 1, further comprising: and forming an isolation structure on the substrate, wherein the isolation structure is positioned on the partial side wall surface of the fin part, and the surface of the isolation structure is lower than the top surface of the fin part.
3. The method of forming a semiconductor structure of claim 2, wherein the method of forming the isolation structure and the isolation layer comprises:
forming an initial isolation material layer on the substrate, wherein the initial isolation material layer is also positioned on the side wall and the top surface of the fin part, and the surface of the initial isolation material layer is higher than the top surface of the fin part;
forming a first mask structure on the surface of the initial isolation material layer, wherein the first mask structure is located on the first region of the fin portion and further extends to a part of the second region and a part of the third region;
etching the initial isolation material layer by taking the first mask structure as a mask until the side wall surface of part of the fin part is exposed to form the isolation structure and the isolation layer;
after the isolation structure and the isolation layer are formed, the first mask structure is removed.
4. The method of forming a semiconductor structure of claim 3, wherein the first mask structure comprises: the mask layer structure comprises a first mask layer positioned on the surface of the initial isolation material layer and a second mask layer positioned on the surface of the first mask layer.
5. The method for forming a semiconductor structure according to claim 4, wherein a material of the second mask layer is different from a material of the first mask layer; the material of the first mask layer is different from the material of the initial isolation material layer.
6. The method for forming a semiconductor structure according to claim 5, wherein the second mask layer is made of silicon nitride; the first mask layer is made of silicon oxide.
7. The method of forming a semiconductor structure of claim 4, wherein the method of forming the first mask structure comprises:
forming a first mask material film on the surface of the initial isolation material layer;
forming a second mask material film on the surface of the first mask material film;
forming a patterned layer on the surface of the second mask material film, wherein the patterned layer is located on the first region of the fin portion and further extends to a part of the second region and a part of the third region;
and etching the second mask material film and the first mask material film by taking the patterning layer as a mask until the surface of the initial isolation material layer is exposed.
8. The method of forming a semiconductor structure of claim 7, wherein the patterned layer comprises a patterned photoresist layer.
9. The method of forming a semiconductor structure of claim 1, further comprising: and before the isolation layer is formed, forming a liner layer on the surface of the side wall of the fin part and the surface of the substrate.
10. The method of claim 3, wherein a top surface of the fin has a second mask structure; the method for forming the fin portion comprises the following steps: providing an initial substrate; forming a second mask structure on the surface of the part of the initial substrate; and etching the initial substrate by taking the second mask structure as a mask to form the fin part.
11. The method of forming a semiconductor structure of claim 10, wherein the second mask structure comprises: a third mask layer; the third mask layer is made of silicon nitride.
12. The method of forming a semiconductor structure of claim 11, wherein the method of forming the initial layer of isolation material comprises: depositing a first isolation material layer on the substrate and on the side walls and the top surface of the fin part; planarizing the first isolation material layer until the surface position of the second mask structure is exposed; back etching the first isolation material layer; and removing the third mask layer of the second mask structure.
13. The method of forming a semiconductor structure of claim 12, wherein the method of forming the initial layer of isolation material further comprises: and after removing the third mask layer, forming a second isolation material layer on the first isolation material layer.
14. The method of forming a semiconductor structure of claim 11, wherein the second mask structure further comprises: a fourth mask layer located between the third mask layer and the surface of the initial substrate; the fourth mask layer is made of silicon oxide.
15. The method of forming a semiconductor structure of claim 11, wherein the second mask structure further comprises: a fifth mask layer positioned on the surface of the third mask layer; the fifth mask layer is made of silicon oxide.
16. The method of forming a semiconductor structure of claim 1, further comprising, prior to forming the epitaxial layer: forming a gate structure crossing the fin portion; and forming a dummy gate structure on the isolation layer.
17. The method as claimed in claim 16, wherein after forming the gate structure and the dummy gate structure, the epitaxial layer is formed in the fin portion on both sides of the gate structure.
18. The method of forming a semiconductor structure of claim 17, wherein the method of forming the epitaxial layer comprises: etching the second region and the third region of the fin part, and forming an opening in the fin part on two sides of the grid structure; an epitaxial layer is formed in the opening.
19. The semiconductor structure formed by the method of any of claims 1 to 18, comprising:
the structure comprises a substrate, wherein a fin part is arranged on the substrate, the fin part comprises a first area, a second area and a third area, the second area and the third area are respectively positioned on two sides of the first area, and the first area, the second area and the third area are arranged along the extending direction of the fin part;
the groove is positioned in the first region of the fin part and penetrates through the fin part along the direction perpendicular to the extending direction of the fin part;
an isolation layer located within the recess, the isolation layer also located at a portion of the top surface of the second region and at a portion of the top surface of the third region;
the epitaxial layer is respectively positioned in the second region and the third region of the fin portion on two sides of the isolation layer, and the epitaxial layer is adjacent to the isolation layer.
CN201910973259.7A 2019-10-14 2019-10-14 Semiconductor structure and forming method thereof Pending CN110707041A (en)

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CN106952818A (en) * 2016-01-06 2017-07-14 中芯国际集成电路制造(上海)有限公司 The forming method of semiconductor structure
CN107045979A (en) * 2016-02-05 2017-08-15 中芯国际集成电路制造(上海)有限公司 The forming method of semiconductor structure
CN107170741A (en) * 2016-03-07 2017-09-15 三星电子株式会社 IC-components and its manufacture method
CN107785315A (en) * 2016-08-26 2018-03-09 中芯国际集成电路制造(上海)有限公司 The forming method of semiconductor structure
CN110034187A (en) * 2018-01-11 2019-07-19 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103219340A (en) * 2012-01-23 2013-07-24 台湾积体电路制造股份有限公司 Halbleiterstruktur und verfahren zu deren herstellung
CN106952818A (en) * 2016-01-06 2017-07-14 中芯国际集成电路制造(上海)有限公司 The forming method of semiconductor structure
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