CN118039567A - Method for forming semiconductor structure - Google Patents

Method for forming semiconductor structure Download PDF

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Publication number
CN118039567A
CN118039567A CN202211384335.9A CN202211384335A CN118039567A CN 118039567 A CN118039567 A CN 118039567A CN 202211384335 A CN202211384335 A CN 202211384335A CN 118039567 A CN118039567 A CN 118039567A
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China
Prior art keywords
isolation
layer
forming
interlayer dielectric
substrate
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CN202211384335.9A
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Chinese (zh)
Inventor
谭程
肖杏宇
纪世良
王彦
张海洋
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Semiconductor Manufacturing International Shanghai Corp
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Semiconductor Manufacturing International Shanghai Corp
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Priority to CN202211384335.9A priority Critical patent/CN118039567A/en
Publication of CN118039567A publication Critical patent/CN118039567A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823468—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

The embodiment of the invention provides a method for forming a semiconductor structure, which comprises the following steps: providing a substrate, wherein the substrate comprises a substrate, a fin part, an isolation layer, a plurality of pseudo gate structures, source-drain doping structures respectively positioned at two sides of each pseudo gate structure, and an interlayer dielectric layer positioned between the pseudo gate structures, wherein the interlayer dielectric layer is filled between the source-drain doping structures and covers the source-drain doping structures; removing part of the interlayer dielectric layer with the thickness, and forming a gap between the pseudo gate structures, wherein the residual interlayer dielectric layer covers the source-drain doping structure; forming a protective layer of a predetermined thickness in the gap; forming a metal gate structure in the space occupied by the dummy gate structure; removing the metal gate structure in a part of the region to form an initial isolation trench; removing at least part of the interlayer dielectric layer in the initial isolation groove by taking the protective layer as a mask to form a target isolation groove; an isolation structure is formed within the target isolation trench. The method for forming the semiconductor structure can improve the performance of the semiconductor structure.

Description

Method for forming semiconductor structure
Technical Field
The embodiment of the application relates to the field of semiconductor manufacturing, in particular to a method for forming a semiconductor structure.
Background
In semiconductor manufacturing, with the trend of very large scale integrated circuits, the feature size of integrated circuits is continuously reduced, and in order to adapt to smaller feature sizes, the channel length of Metal-Oxide-semiconductor field effect transistors (MOSFETs) is continuously shortened. However, as the channel length of the device is shortened, the distance between the source and the drain of the device is also shortened, so that the control capability of the gate structure on the channel is further and further reduced, and the difficulty of pinching off the channel by the gate voltage is further and further increased, so that the phenomenon of subthreshold leakage (subthreshold leakage), namely the so-called Short channel effect (Short CHANNEL EFFECTS, SCE), is more likely to occur.
Accordingly, to reduce the impact of short channel effects, semiconductor processes are gradually beginning to transition from planar MOSFETs to three-dimensional transistors with higher efficiency, such as Fin Field effect transistors (finfets-Effect Transistor, finfets). In the FinFET, the gate structure can control the ultrathin body (fin part) from at least two sides, compared with a planar MOSFET, the gate structure has stronger control capability on a channel, can well inhibit short channel effect, and has better compatibility with the existing integrated circuit manufacturing.
However, the existing semiconductor process forms devices with poor performance.
Disclosure of Invention
In view of this, the embodiment of the application provides a method for forming a semiconductor structure, which improves the performance of the device.
The embodiment of the invention provides a method for forming a semiconductor structure, which comprises the following steps:
Providing a substrate, wherein the substrate comprises a substrate, a plurality of parallel fin parts positioned on the substrate, an isolation layer positioned between the fin parts and covering the side walls of part of the fin parts, a plurality of pseudo gate structures crossing the fin parts, source-drain doping structures respectively positioned on the fin parts at two sides of each pseudo gate structure, and an interlayer dielectric layer positioned between the pseudo gate structures, and the interlayer dielectric layer is filled between the source-drain doping structures and covers the source-drain doping structures;
Removing part of the interlayer dielectric layer with the thickness, and forming a gap between the pseudo gate structures, wherein the residual interlayer dielectric layer covers the source-drain doping structure;
Forming a protective layer of a predetermined thickness in the gap;
Forming a metal gate structure in the space occupied by the dummy gate structure;
Removing the metal gate structure in a part of the region to form an initial isolation trench;
removing at least part of the isolation layer in the initial isolation groove by taking the protection layer as a mask to form a target isolation groove;
And forming an isolation structure in the target isolation trench.
Optionally, in the step of removing at least a portion of the isolation layer in the initial isolation trench, 20% -80% of the thickness of the isolation layer is removed.
Optionally, the step of forming the target isolation trench by removing at least a portion of the isolation layer in the initial isolation trench with the protection layer as a mask includes:
Removing all isolation layers in the initial isolation trenches, and exposing the substrate under the isolation layers;
And removing part of the exposed substrate to form the target isolation trench.
Optionally, forming a protective layer with a predetermined thickness in the gap, including:
depositing a covering protection material layer at the gap and the top end of the pseudo gate structure;
And flattening and grinding to remove the protective material layer covered on the top end of the pseudo gate structure, so as to form a protective layer with a planar surface.
Optionally, the material of the protective layer is one or more of silicon nitride, silicon carbide, silicon carbonitride oxide, silicon oxynitride, boron nitride and boron carbonitride.
Optionally, in the step of providing a substrate, the height of the interlayer dielectric layer is greater than the sum of the source-drain doping structure and a preset value;
And in the step of removing the interlayer dielectric layer with partial thickness and forming gaps between the dummy gate structures, the heights of the gaps are the same as the preset value in the step of providing the substrate.
Optionally, in the step of providing a substrate, the substrate further includes a sidewall between the doped structure and the dummy gate structure, where the sidewall is made of the same material as the protective layer.
Optionally, in the step of removing the metal gate structure in the partial region, an extension direction of the partial region intersects with and covers a plurality of the metal gate structures in the step of forming the initial isolation trench.
Optionally, the step of removing the metal gate structure in the partial region to form an initial isolation trench includes:
A hard mask layer is formed on the substrate,
Etching part of the hard mask layer to expose part of the metal gate structure;
and removing the exposed part of the metal gate structure to form an initial isolation trench.
Optionally, the step of forming an isolation structure in the target isolation trench specifically includes:
Forming an isolation material layer covering the target isolation trench and the hard mask layer by adopting a deposition process;
and removing the isolation material layer on the hard mask layer through a chemical mechanical polishing process to form an isolation structure.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
According to the embodiment of the invention, before the metal gate structure is formed, the interlayer dielectric layer with partial thickness is removed, a gap is formed between the pseudo gate structures, and a protective layer with preset thickness is formed in the gap, so that the metal gate structure used for forming the area of the isolation structure is firstly removed in the process of forming the isolation structure for isolating the metal gate structure, an initial isolation groove is formed, and the protective layer is used as a mask, at least part of isolation layer in the initial isolation groove is further removed, and a target isolation groove is formed, so that the interlayer dielectric layer is not damaged in the process of forming the target isolation groove, and the source-drain doping structure covered by the interlayer dielectric layer is not damaged; meanwhile, according to the embodiment of the invention, the protective layer is used as a mask, the isolation layer in the initial isolation groove is further removed, and the target isolation groove is formed, so that the target isolation groove can completely isolate the metal gate structures at two sides of the target isolation groove, correspondingly, the isolation structure is formed in the target isolation groove to completely isolate the metal gate structures at the side parts of the isolation structure, the bridging phenomenon of the metal gate structures is avoided, and the performance of the semiconductor structure is improved.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are required to be used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only embodiments of the present application, and that other drawings can be obtained according to the provided drawings without inventive effort for a person skilled in the art.
Fig. 1 to 6 are schematic structural views corresponding to steps in a method for forming a semiconductor structure;
Fig. 7 to 17 are schematic structural views corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Detailed Description
As known from the background art, the devices formed by the existing technology still have the problem of poor performance. The reason for the poor performance of the device is analyzed by combining a forming method of a semiconductor structure.
Referring to fig. 1 to 6, fig. 1 to 6 show schematic structural diagrams corresponding to steps in a method for forming a semiconductor structure.
As shown in fig. 1 to 2, fig. 2 is a cross-sectional view of a direction A1A2 in fig. 1, and a substrate is provided, where the substrate includes a substrate 101, a fin 102, an isolation layer 108, a plurality of gate structures 103 located on the substrate 101, an interlayer dielectric layer 105 between a plurality of dummy gate structures, and a sidewall 104 located between the gate structures 103 and the interlayer dielectric layer 105. The substrate includes an isolation region 106, and the extension direction of the isolation region 106 intersects the plurality of dummy gates 103 (only one dummy gate 103 is illustrated in the drawing) and covers at least a portion of the source-drain doped structure 107 (shown in fig. 4).
A method of cutting the gate structure 103 is shown in fig. 3, wherein the gate structure 103 is removed from the isolation region 106, and shallow isolation trenches 110 are formed transverse to the plurality of gate structures 103.
The inventors found that the device performance formed by the above method is poor, and particularly referring to fig. 4 in conjunction with fig. 1 to 3, where fig. 4 is a cross-sectional view along the direction B1B2 of fig. 1, as shown in the drawing, since only the gate structure 103 in the isolation region 106 is removed, and the interlayer dielectric layer 105 and the isolation layer 108 in the isolation region 106 are not further removed, there may be a residue at the bottom of the gate structure 103, and bridging is easy to occur when the Critical Dimension (CD) is small.
Another method of cutting the gate structure 103 is shown in fig. 5, in which the gate structure 103, the interlayer dielectric layer 105 and the substrate 101 in the isolation region 106 are removed to form a deep isolation trench 109 intersecting the plurality of gate structures 103.
The inventors have found that the device performance formed by the above method is poor, and refer to fig. 6 in conjunction with fig. 1 to 3, wherein fig. 6 is a cross-sectional view of fig. 1 along the direction B1B 2. As shown in the figure, the inter-layer dielectric layer 105 and the isolation layer 108 in the isolation region 106 and the substrate 101 are removed in addition to the gate structure 103, so that the residue of the gate structure 103 and the bridging phenomenon caused by the residue can be reduced, but when the inter-layer dielectric layer in the isolation region 106 is removed, part of the source-drain doped structure 107 may be removed, especially when the critical dimension is too large or the source-drain doped structure 107 is too large.
Therefore, how to avoid bridging and damaging the source/drain doped structure 107 during the gate structure 103 cutting is a technical problem that needs to be solved by those skilled in the art.
Based on the above, the embodiment of the invention provides a semiconductor structure forming method, which comprises the following steps: providing a substrate, wherein the substrate comprises a substrate, a plurality of parallel fin parts positioned on the substrate, an isolation layer positioned between the fin parts and covering the side walls of part of the fin parts, a plurality of pseudo gate structures crossing the fin parts, source-drain doping structures respectively positioned on the fin parts at two sides of each pseudo gate structure, and an interlayer dielectric layer positioned between the pseudo gate structures, and the interlayer dielectric layer is filled between the source-drain doping structures and covers the source-drain doping structures; removing part of the interlayer dielectric layer with the thickness, and forming a gap between the pseudo gate structures, wherein the residual interlayer dielectric layer covers the source-drain doping structure; forming a protective layer of a predetermined thickness in the gap; forming a metal gate structure in the space occupied by the dummy gate structure; removing the metal gate structure in a part of the region to form an initial isolation trench; removing at least part of the isolation layer in the initial isolation groove by taking the protection layer as a mask to form a target isolation groove; and forming an isolation structure in the target isolation trench.
According to the embodiment of the invention, before the metal gate structure is formed, the interlayer dielectric layer with partial thickness is removed, a gap is formed between the pseudo gate structures, and a protective layer with preset thickness is formed in the gap, so that the metal gate structure used for forming the area of the isolation structure is firstly removed in the process of forming the isolation structure for isolating the metal gate structure, an initial isolation groove is formed, and the protective layer is used as a mask, at least part of isolation layer in the initial isolation groove is further removed, and a target isolation groove is formed, so that the interlayer dielectric layer is not damaged in the process of forming the target isolation groove, and the source-drain doping structure covered by the interlayer dielectric layer is not damaged; meanwhile, according to the embodiment of the invention, the protective layer is used as a mask, the isolation layer in the initial isolation groove is further removed, and the target isolation groove is formed, so that the target isolation groove can completely isolate the metal gate structures at two sides of the target isolation groove, correspondingly, the isolation structure is formed in the target isolation groove to completely isolate the metal gate structures at the side parts of the isolation structure, the bridging phenomenon of the metal gate structures is avoided, and the performance of the semiconductor structure is improved.
In order to make the above objects, features and advantages of the embodiments of the present invention more comprehensible, a detailed description of specific embodiments of the present invention is provided below with reference to the accompanying drawings.
Fig. 7 to 17 are schematic structural views corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Referring to fig. 7, a base is provided, where the base includes a substrate 201, a plurality of parallel fins located on the substrate 201, an isolation layer 210 located between the fins and covering a portion of sidewalls of the fins, a plurality of dummy gate structures 202 crossing the fins, source-drain doped structures located on two sides of each of the dummy gate structures 202, and an interlayer dielectric layer 203 located between the dummy gate structures 202, and the interlayer dielectric layer 203 is filled between the source-drain doped structures and covers the source-drain doped structures.
The substrate 201 is used to provide support for other structures. In an embodiment of the present invention, the material of the substrate 201 may be silicon. In other embodiments, the substrate material may also be germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate. The material of the substrate may be a material suitable for process requirements or easy integration. The surface of the substrate 201 may further be formed with an interface layer, where a material of the interface layer is silicon oxide, silicon nitride, silicon oxynitride, or the like.
The dummy gate structure 202 occupies a space for a metal gate structure 204 formed in a subsequent process. The dummy gate structure 202 may be polysilicon, and in other embodiments, the material of the dummy gate may be silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride oxide, or amorphous carbon.
In the process of forming the device structure, in order to form a plurality of device structures simultaneously, a plurality of parallel dummy gate structures 202 are generally formed on the substrate simultaneously, so that corresponding processing is performed simultaneously in the process of forming the device, thereby simplifying the process flow.
The source-drain doped structure may be made of doped semiconductor material, such as polysilicon doped material, germanium doped material, etc.
In some embodiments, the sidewalls 205 may be formed on two sides of the dummy gate structure 202, and the sidewalls 205 may define a formation region of the source-drain doped structure. In some embodiments, the sidewall 205 is located between the source-drain doped structure and the dummy gate structure 202, and the material of the sidewall 205 may be silicon nitride. In other embodiments of the present invention, the sidewall 205 may be one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, and boron carbonitride.
The interlayer dielectric layer 203 is filled between and covers the source-drain doped structures in a surrounding manner, and is used for protecting the device structures and providing support and isolation for the device structures.
The material of the interlayer dielectric layer 203 may be an insulating material. In this embodiment, the material of the interlayer dielectric layer 203 is silicon oxide. In other embodiments, the material of the interlayer dielectric layer may be another dielectric material such as silicon nitride or silicon oxynitride.
In order to avoid damaging the source-drain doped structure when removing part of the thickness of the interlayer dielectric layer 203 later, in some embodiments of the invention, the height of the interlayer dielectric layer 203 is greater than the sum of the source-drain doped structure and a preset value.
Referring to fig. 8, a portion of the interlayer dielectric layer 203 is removed, and a gap is formed between the dummy gate structures 202, wherein the remaining interlayer dielectric layer 203 covers the source-drain doped structures.
The removal of a portion of the thickness interlayer dielectric layer 203 may be performed by a dry etching process, and the corresponding process gas may be a fluorine-containing gas, such as CF 4、CHF3.
When removing part of the thickness of the interlayer dielectric layer, the thickness cannot be too large, so that the interlayer dielectric layer 203 remained after the removal still covers the source-drain doped structure, i.e. is actually removed only from the interlayer dielectric layer 203 covering the source-drain doped structure. Thus, the source-drain doping structure can be prevented from being damaged when the interlayer dielectric layer 203 is removed.
After removing part of the thickness of the interlayer dielectric layer 203, a gap between the bottom and the sidewall formed by the interlayer dielectric layer 203 and the dummy gate structure 202 is formed, and the interlayer dielectric layer 203 is sandwiched between the gaps, so that the active drain doping structure is formed.
In some embodiments, when the height of the interlayer dielectric layer 203 in the step of providing a substrate is greater than the sum of the source-drain doping structure and the preset value, removing a portion of the thickness of the interlayer dielectric layer 203 needs to make the height of the gap the same as the preset value in the step of providing a substrate.
In this way, when the interlayer dielectric layer is removed to form a gap, a certain distance (the distance is the difference between the height of the interlayer dielectric layer 203 and the sum of the height of the source-drain doped structure and the height of the gap) is formed between the formed gap and the source-drain doped structure, so that the excessive thickness removed when the interlayer dielectric layer 203 is removed can be avoided, and the source-drain doped structure is damaged.
Referring to fig. 9, a protective layer 206 of a predetermined thickness is formed at the gap.
The material of the protective layer 206 may be silicon nitride, and in other embodiments, the protective layer 206 may be one or more of silicon carbide, silicon carbonitride oxide, silicon oxynitride, boron nitride, and boron carbonitride.
In the embodiment of the present invention, the silicon nitride is deposited to be level with the dummy gate structure in the gap formed after removing part of the thickness interlayer dielectric layer 203 by deposition. In the embodiment of the present invention, a layer of covering protection material may be deposited specifically on top of the gaps and the dummy gate structures 202; the planarization and polishing remove the protective material layer covering the top of the dummy gate structure 202, and form a protective layer 206 with a planar surface. In the embodiment of the present invention, the thickness of the protective material layer may be greater than the height of the gap, so that the formed protective layer 206 is flush with the dummy gate structure 202; in other embodiments of the invention, the thickness of the material layer may be less than the height of the gap, and the protective layer 206 formed on the gap with a predetermined thickness is not flush with the dummy gate structure.
Referring to fig. 10-11, a metal gate structure is formed in the space occupied by the dummy gate structure.
Referring to fig. 10, the dummy gate structure 202 is removed, forming a gate recess.
Specifically, the dummy gate structure 202 may be removed by an etching process, which may be dry etching or wet etching, so that a gate trench surrounded by the isolation layer 210 and the interlayer dielectric layer 203 is formed in the original position of the dummy gate structure 202.
Since the dummy gate structure 202 is different from the structures of the interlayer dielectric layer 203 and the protective layer 206, the interlayer dielectric layer 203 and the protective layer 206 are not removed when the dummy gate structure 202 is removed. After the dummy gate structure 202 is removed, a gate recess is formed in situ in the dummy gate structure 202.
Specifically, in the embodiment of the present invention, the dummy gate structure 202 may be removed by etching.
Of course, before removing the dummy gate structure 202, gate cutting may be performed on the dummy gate structure 202, and after the dummy gate structure 202 is cut, the metal gate structure 204 may be deposited.
Referring to fig. 11, a metal gate structure 204 is formed within the gate recess.
In the gate recess formed by removing the dummy gate structure 202, the metal gate structure 204 has a high dielectric constant in the embodiment of the present application.
Specifically, a metal gate material layer may be first formed in the gate trench and over the protection layer 206 by a deposition process, a sputtering process, or an electroplating process, and then the metal gate material layer over the protection layer 206 is removed by grinding to form the metal gate structure 204 flush with the protection layer 206. In the embodiment of the invention, the metal gate material layer may be polished by a chemical mechanical polishing process, and in other embodiments of the invention, the metal gate material layer may also be polished by other processes.
Referring to fig. 12-14, the metal gate structure 204 is removed in a portion of the region to form an initial isolation trench 207.
After forming the metal gate structure 204, the metal gate 204 needs to be cut to form the initial isolation trench 207 following a subsequent process step of patterning the substrate. Please refer to fig. 10-12 in detail.
Referring to fig. 12, a hard mask layer 209 is formed on a substrate.
A hard mask layer 209 is deposited over the substrate. The material of the hard mask layer 209 may be silicon nitride, and in other embodiments, the material of the hard mask layer 240 may also be silicon oxynitride.
In an embodiment of the present invention, a titanium nitride layer 212 may be deposited on the substrate before the hard mask layer 209 is deposited, and an oxide layer 211 may be deposited after the hard mask layer 209 is deposited. In this way, the oxide layer 211 may be covered with photoresist, after the photoresist is photo-etched and developed, a portion of the oxide layer 211 is exposed, and the exposed oxide layer 211 is etched, so that the oxide layer 211 is used as a hard mask to etch the hard mask layer 209 and the titanium nitride layer 212. The remaining titanium nitride layer 212 may be used to stop polishing during subsequent planarization polishing.
When there are a plurality of parallel metal gate structures 208 on the substrate, in some embodiments, the extension direction of the partial region intersects the plurality of metal gate structures 208 and covers the plurality of metal gate structures 204. Wherein the partial region is a region for forming an isolation structure. In this way, multiple metal gate structures 204 may be cut simultaneously.
Referring to fig. 13, a portion of the hard mask layer 209 is etched to expose a portion of the metal gate structure 204.
After the oxide layer is subjected to photoetching development, a photoetching mask layer is formed, and the photoetching mask layer is taken as a mask, and part of the oxide layer is etched and removed to expose part of the hard mask layer 209, so that the oxide layer is taken as a hard mask to etch the hard mask layer 209 and the titanium nitride layer, and part of the metal gate structure 204 is exposed.
Referring to fig. 14, the exposed portion of the metal gate structure 204 is removed to form an initial isolation trench.
The metal gate structure 204 is etched using the hard mask layer 209 as a mask, in which embodiment the exposed metal gate structure 204 is completely removed, and in other embodiments only the exposed metal gate structure 204 may be partially removed as desired.
After etching the metal gate structure 204, a recess with a sidewall and a bottom formed by the interlayer dielectric layer 203 is formed in the original position of the metal gate structure 204, and the recess and the interlayer dielectric layer 203 forming the bottom of the recess are the initial isolation trenches.
Of course, the source-drain doped structure is outside the sidewall formed by the interlayer dielectric layer 203, and the source-drain doped structure is not damaged by removing the metal gate structure 204 due to the protection of the interlayer dielectric layer 203.
Referring to fig. 15, with the protection layer 206 as a mask, at least a portion of the interlayer dielectric layer 203 in the initial isolation trench is removed to form a target isolation trench 208.
To avoid bridging caused by the remaining metal gate structure 204, it is necessary to further etch at least the interlayer dielectric layer 203 within the initial isolation trench to form the target isolation trench 208. It should be noted that, as shown in the drawing, the hard mask layer 209 after the photolithography etching may expose the metal gate structure 204 and also expose the interlayer dielectric layer 203 adjacent to the metal gate structure 204, but since the protective layer 206 is disposed on the interlayer dielectric layer 203, the interlayer dielectric layer 203 under the protective layer 206 and the source-drain doped structure covered by the interlayer dielectric layer 203 are not etched when the interlayer dielectric layer 203 in the initial isolation trench is etched, so that bridging can be avoided and damage to the source-drain doped structure can be prevented in the process of cutting the metal gate structure 204.
It should be noted that, in some embodiments of the present invention, not all of the interlayer dielectric layer in the initial isolation trench needs to be removed, and 20% -80% of the interlayer dielectric layer in the initial isolation trench may be removed; in other embodiments of the present invention, to further avoid bridging, all of the interlayer dielectric layer in the initial isolation trench may be removed, exposing the substrate under the initial isolation trench, and further removing a portion of the exposed substrate to form the target isolation trench, so that the residual metal gate structure 204 may be further avoided, and thus the bridging problem may be caused.
In order to avoid that when the interlayer dielectric layer in the initial isolation trench is etched, the etching solution etches the source-drain doped structure protected by the interlayer dielectric layer by etching the sidewall of the initial isolation trench (also formed by the interlayer dielectric layer 203), in some embodiments of the invention, the substrate further includes a sidewall 205 located between the source-drain doped structure and the dummy gate structure 202, where the sidewall 205 is made of the same material as the protective layer 206, so as to protect the sidewall formed by the interlayer dielectric layer 203 of the initial isolation trench and further protect the source-drain doped structure.
To achieve isolation of the device structure, an isolation structure 210 filling the target isolation trench 208 may be formed. To form the isolation structure 210, referring to fig. 14-15, an isolation structure is formed in the target isolation trench 208.
Referring to fig. 16, a deposition process is used to form an isolation material layer covering the target isolation trench 208 and the hard mask layer.
In an embodiment of the present invention, the process of forming the isolation structure 210 that fills the target isolation trench 208 may first form an isolation material layer that covers the target isolation trench 208 and the hard mask layer by using a deposition process, where a material of the isolation material layer may be an insulating material so as to electrically isolate the device structures from each other, and specifically, a material of the isolation material layer may be one or more of silicon nitride, silicon oxide, silicon carbide, silicon carbonitride, silicon oxynitride, boron nitride, and boron carbonitride. In an embodiment of the present invention, a material of the isolation material layer may be silicon nitride.
The deposition process for forming the isolation material layer may be a flow chemical vapor deposition process (Flowable Chemical Vapor Deposition, FCVD).
Referring to fig. 17, the isolation material layer on the hard mask layer is removed by a chemical mechanical polishing process to form an isolation structure 210.
After depositing the isolation material layer, in the embodiment of the present invention, the isolation material layer on the hard mask layer may be removed by a chemical mechanical polishing process to form the isolation structure 210, so that the isolation structure 210 forms good morphology features. Of course, in other embodiments, other grinding processes may be employed.
According to the embodiment of the invention, before the metal gate structure is formed, the interlayer dielectric layer with partial thickness is removed, a gap is formed between the pseudo gate structures, and a protective layer which is flush with the pseudo gate structure is formed in the gap, so that in the process of subsequently forming the isolation structure for isolating the metal gate structure, the metal gate structure for forming the area of the isolation structure is firstly removed, an initial isolation groove is formed, the interlayer dielectric layer in the initial isolation groove is further removed by taking the protective layer as a mask, and a target isolation groove 208 is formed, so that the interlayer dielectric layer is not damaged in the process of forming the target isolation groove 208, and the source drain doping structure covered by the interlayer dielectric layer is not damaged; meanwhile, according to the embodiment of the invention, the interlayer dielectric layer in the initial isolation trench is further removed by taking the protective layer as a mask, so that the target isolation trench 208 is formed, and further, the target isolation trench 208 can completely isolate the metal gate structures at two sides of the target isolation trench 208, accordingly, an isolation structure is formed in the target isolation trench 208 to completely isolate the metal gate structures at the side parts of the isolation structure, the bridging phenomenon of the metal gate structures is avoided, and the performance of the semiconductor structure is improved.
The semiconductor structure may be formed by the forming method described in the foregoing embodiments, or may be formed by other forming methods. For a specific description of the semiconductor structure in this embodiment, reference may be made to the corresponding description in the foregoing embodiment, which is not repeated here.
Although the embodiments of the present invention are disclosed above, the embodiments of the present invention are not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the embodiments of the invention, and the scope of the embodiments of the invention should be pointed out in the appended claims.

Claims (10)

1. A method of forming a semiconductor structure, comprising:
Providing a substrate, wherein the substrate comprises a substrate, a plurality of parallel fin parts positioned on the substrate, an isolation layer positioned between the fin parts and covering the side walls of part of the fin parts, a plurality of pseudo gate structures crossing the fin parts, source-drain doping structures respectively positioned on the fin parts at two sides of each pseudo gate structure, and an interlayer dielectric layer positioned between the pseudo gate structures, and the interlayer dielectric layer is filled between the source-drain doping structures and covers the source-drain doping structures;
Removing part of the interlayer dielectric layer with the thickness, and forming a gap between the pseudo gate structures, wherein the residual interlayer dielectric layer covers the source-drain doping structure;
Forming a protective layer of a predetermined thickness in the gap;
Forming a metal gate structure in the space occupied by the dummy gate structure;
Removing the metal gate structure in a part of the region to form an initial isolation trench;
removing at least part of the isolation layer in the initial isolation groove by taking the protection layer as a mask to form a target isolation groove;
And forming an isolation structure in the target isolation trench.
2. The method of forming a semiconductor structure of claim 1, wherein in said step of removing at least a portion of the isolation layer within the initial isolation trench, 20% -80% of the thickness of the isolation layer is removed.
3. The method of forming a semiconductor structure of claim 1, wherein said step of forming a target isolation trench by removing at least a portion of the isolation layer in the initial isolation trench using the protective layer as a mask comprises:
Removing all isolation layers in the initial isolation trenches, and exposing the substrate under the isolation layers;
And removing part of the exposed substrate to form the target isolation trench.
4. The method of forming a semiconductor structure of claim 1, wherein forming a protective layer of a predetermined thickness in the gap comprises:
depositing a covering protection material layer at the gap and the top end of the pseudo gate structure;
And flattening and grinding to remove the protective material layer covered on the top end of the pseudo gate structure, so as to form a protective layer with a planar surface.
5. The method of forming a semiconductor structure of claim 1, wherein the material of the protective layer is one or more of silicon nitride, silicon carbide, silicon carbonitride oxide, silicon oxynitride, boron nitride, and boron carbonitride.
6. The method of forming a semiconductor structure of claim 1, wherein in said step of providing a substrate, a height of said interlayer dielectric layer is greater than a sum of a source-drain doped structure and a predetermined value;
And in the step of removing the interlayer dielectric layer with partial thickness and forming gaps between the dummy gate structures, the heights of the gaps are the same as the preset value in the step of providing the substrate.
7. The method of forming a semiconductor structure of claim 2, wherein in the step of providing a substrate, the substrate further comprises a sidewall between the doped structure and the dummy gate structure, the sidewall being of the same material as the protective layer.
8. The method of forming a semiconductor structure according to claim 4, wherein in the step of removing the metal gate structure in the partial region, an extending direction of the partial region intersects with and covers a plurality of the metal gate structures to form an initial isolation trench.
9. The method of forming a semiconductor structure of claim 1, wherein the step of removing a portion of the metal gate structure in the region to form an initial isolation trench comprises:
A hard mask layer is formed on the substrate,
Etching part of the hard mask layer to expose part of the metal gate structure;
and removing the exposed part of the metal gate structure to form an initial isolation trench.
10. The method of forming a semiconductor structure of claim 1, wherein the step of forming an isolation structure within the target isolation trench comprises:
Forming an isolation material layer covering the target isolation trench and the hard mask layer by adopting a deposition process;
and removing the isolation material layer on the hard mask layer through a chemical mechanical polishing process to form an isolation structure.
CN202211384335.9A 2022-11-07 2022-11-07 Method for forming semiconductor structure Pending CN118039567A (en)

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CN202211384335.9A CN118039567A (en) 2022-11-07 2022-11-07 Method for forming semiconductor structure

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Application Number Priority Date Filing Date Title
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