CN109841527B - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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- CN109841527B CN109841527B CN201711235288.0A CN201711235288A CN109841527B CN 109841527 B CN109841527 B CN 109841527B CN 201711235288 A CN201711235288 A CN 201711235288A CN 109841527 B CN109841527 B CN 109841527B
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Abstract
A semiconductor structure and a forming method thereof are provided, wherein the forming method comprises the following steps: providing a substrate, wherein a functional layer is arranged on the substrate, a plurality of grooves are formed in the functional layer, and the functional layer between every two adjacent grooves is defined as an active area; forming an etching stop layer, wherein the etching stop layer is at least positioned on the side wall which is arranged opposite to the vertical extending direction of the groove; and forming an isolation structure in the groove with the etching stop layer formed on the side wall. The side wall of the isolation structure facing the active region is provided with the etching stop layer, so that the etching stop layer can protect the isolation structure between the adjacent active regions in the subsequent epitaxial layer forming process, the opening width is prevented from being increased, the thickness of the isolation structure between the subsequently formed adjacent epitaxial layers is increased, the bridging problem caused by the over-small distance between the adjacent epitaxial layers is solved, and the manufacturing yield and the device performance of the formed semiconductor structure are improved.
Description
Technical Field
The present invention relates to the field of semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same.
Background
Transistors are currently being widely used as the most basic semiconductor devices. As the density and integration of devices in integrated circuits increases, the size of transistors becomes smaller and smaller. As transistor dimensions shrink, the channel length and gate length of the transistor also shrink. The shortening of the channel length of the transistor makes the approximation of the graded channel no longer true, which causes short channel effect, and further generates leakage current, which affects the performance of the semiconductor device. By introducing stress into the channel region of the transistor, the mobility of current carriers in the channel can be improved, and the drive current of the transistor is further improved, so that the drive current is not lost while the leakage current of the transistor is inhibited by increasing the channel doping.
The method for introducing stress into the channel region of the transistor is to form an epitaxial layer in the transistor, wherein the epitaxial layer is used for providing compressive stress to the channel region of the PMOS transistor and introducing tensile stress to the channel region of the NMOS transistor, so that the mobility of carriers in the channel region of the transistor is improved, and the performance of the transistor is further improved. Specifically, the epitaxial layer is generally formed of a silicon germanium material or a silicon carbon material, and a compressive stress or a tensile stress is formed by lattice mismatch between the epitaxial layer and the silicon crystal.
However, the semiconductor structure with the epitaxial layer formed in the prior art often has the problem of poor electrical performance.
Disclosure of Invention
The invention provides a semiconductor structure and a forming method thereof, which are used for improving the electrical performance of the formed semiconductor structure.
To solve the above problems, the present invention provides a method for forming a semiconductor structure, comprising:
providing a substrate, wherein a functional layer is arranged on the substrate, a plurality of grooves are formed in the functional layer, and the functional layer between every two adjacent grooves is defined as an active area; forming an etching stop layer, wherein the etching stop layer is at least positioned on the side wall which is arranged opposite to the vertical extending direction of the groove; and forming an isolation structure in the groove with the etching stop layer formed on the side wall.
Optionally, the groove penetrates through the functional layer, and the substrate is exposed from the bottom of the groove; the etching stop layer also extends to the substrate exposed at the bottom of the groove.
Optionally, the density of the etching stop layer material is greater than the density of the isolation structure material.
Optionally, the etching stop layer is made of silicon nitride, and the isolation structure is made of silicon oxide.
Optionally, the thickness of the etching stop layer is within
To
Within the range.
Optionally, the etching stop layer is formed by atomic layer deposition or furnace tube.
Optionally, after providing the substrate and before forming the etch stop layer, the method further includes: forming linear oxide layers on the side wall and the bottom of the groove; the etching stop layer is positioned on the linear oxidation layer.
Optionally, after the forming the isolation structure, the method further includes: forming an opening in the active region, wherein at least part of the side wall of the opening exposes the etching stop layer; and forming an epitaxial layer filled in the opening with the side wall exposed out of the etching stop layer.
Optionally, after forming the opening in the active region and before forming the epitaxial layer, the method further includes: and cleaning the bottom and the side wall of the opening.
Optionally, the etching rate of the cleaning process on the etching stop layer is less than the etching rate of the cleaning process on the isolation structure.
Optionally, the bottom and the side wall of the opening are cleaned by hydrofluoric acid.
Accordingly, the present invention also provides a semiconductor structure comprising:
a substrate; a functional layer on the substrate; the isolation structures are positioned in the functional layers, and the functional layers between the adjacent isolation structures are defined as active regions; and the etching stop layer is at least positioned on the side wall of the isolation structure facing the active region.
Optionally, the density of the etching stop layer is greater than that of the isolation structure.
Optionally, the etching stop layer is made of silicon nitride, and the isolation structure is made of silicon oxide.
Optionally, the thickness of the etching stop layer is within
To
Within the range of。
Optionally, the isolation structure penetrates through the functional layer; the etch stop layer is also located between the isolation structure and the substrate.
Optionally, the method further includes: an epitaxial layer located within the active region; the etching stop layer is positioned between the isolation structure and the epitaxial layer and extends to a position between the isolation structure and the active region.
Compared with the prior art, the technical scheme of the invention has the following advantages:
the etching stop layer is used for protecting the isolation structure between the adjacent active regions and preventing the opening width from being increased in the subsequent epitaxial layer forming process, so that the thickness of the isolation structure between the subsequently formed adjacent epitaxial layers is increased, the bridging problem caused by the undersize distance between the adjacent epitaxial layers is solved, and the manufacturing yield and the device performance of the formed semiconductor structure are improved.
In an alternative of the present invention, the etch stop layer may be formed by atomic layer deposition or by a furnace tube. The atomic layer deposition or furnace tube mode can form a material film layer with higher density and better step coverage, so that the etching stop layer is formed in the atomic layer deposition or furnace tube mode, the quality and the thickness uniformity of the formed etching stop layer can be effectively improved, the device performance is favorably improved, and the difficulty of subsequent processes is favorably reduced.
In an alternative aspect of the invention, the etch stop layer has a thickness of
To
Within the range. The thickness of the etch stop layer is preferably not too small nor too large. If the thickness of the etching stop layer is too small, the effect of the etching stop layer on the etching stop layer can be influenced, and the etching stop layer can not protect an isolation structure between adjacent active regions and can influence the improvement effect of the bridging problem; due to the etching stopThe layer is located on the side walls, arranged oppositely, in the first direction of the active area, the side walls, arranged oppositely, in the first direction of the active area are used for enclosing a groove, the groove is used for forming an isolation structure, so if the thickness of the etching stop layer is too large, the depth-to-width ratio of the groove is too large, the filling difficulty of a medium material in the forming process of the isolation structure can be increased, the yield and the performance of the formed isolation structure can be influenced, and the manufacturing yield and the device performance of the formed semiconductor structure can be influenced.
Drawings
FIGS. 1-3 are schematic cross-sectional views of a semiconductor structure in accordance with various steps of a method for forming the semiconductor structure;
fig. 4 to 8 are schematic cross-sectional views corresponding to steps of the method for forming a semiconductor structure according to the present invention.
Detailed Description
As can be seen from the background art, the semiconductor structure having the epitaxial layer in the prior art has a problem of poor electrical performance. The cause of the problem of poor performance is now analyzed in conjunction with a method of forming a semiconductor structure having an epitaxial layer:
referring to fig. 1 to 3, schematic cross-sectional structures corresponding to respective steps of a semiconductor structure forming method are shown.
The forming method of the semiconductor structure comprises the following steps: as shown in fig. 1, a substrate 11 is provided having a functional layer 12 thereon; forming grooves 14 in the functional layer 12, wherein the functional layer 12 between adjacent grooves 14 is defined as an active area aa; as shown in fig. 2, forming an isolation structure 16 in the groove 14 (shown in fig. 1) to fill the groove 14; as shown in fig. 3, an opening 17 is formed in the active region aa.
Specifically, the step of forming the opening 17 includes: etching the functional layer 12 of the active area aa, and forming the opening 17 in the functional layer 12 of the active area aa; the opening 17 is subjected to a cleaning process to remove impurities on the side wall and bottom surface of the opening 17.
As shown in fig. 3, the opening 17 is generally surrounded by the isolation structure 16 and the functional layer 12 of the active area aa, that is, the sidewall of the opening 17 exposes the isolation structure 16, and the material of the isolation structure 16 is typically silicon oxide; in the step of cleaning the opening 17, a wet cleaning method using dilute hydrofluoric acid is used, so that the isolation structure 16 forming the sidewall of the opening 17 is corroded by hydrofluoric acid during the cleaning process of the opening 17, which may increase the width of the opening 17. The increase of the width of the opening 17 will reduce the distance d between adjacent openings 17, and the thickness of the isolation structure 16 between adjacent openings 17 will be reduced, so that the probability of bridging between the epitaxial layers formed in the openings 17 will increase, and the electrical performance of the formed semiconductor structure will be degraded.
Particularly for PMOS transistors, in order to better apply stress to carriers in the channel, the volume of the epitaxial layer in the PMOS transistor is larger, so the depth of the opening 17 is larger, thereby increasing the probability of damage to the isolation structure 16, increasing the probability of bridging between the subsequently formed epitaxial layers, and causing the degradation of the manufacturing yield and device performance of the formed semiconductor structure.
In order to solve the technical problem, the invention provides a semiconductor structure and a forming method thereof, wherein an etching stop layer is arranged on the side wall of the isolation structure facing the active region, so that the etching stop layer can protect the isolation structure between the adjacent active regions and prevent the opening width from being enlarged in the subsequent epitaxial layer forming process, thereby increasing the thickness of the isolation structure between the subsequently formed adjacent epitaxial layers, improving the bridging problem caused by the over-small distance between the adjacent epitaxial layers and further improving the manufacturing yield and the device performance of the formed semiconductor structure.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Referring to fig. 4 to 8, schematic cross-sectional structures corresponding to steps of a semiconductor structure forming method according to an embodiment of the invention are shown.
Referring to fig. 4, a substrate 110 is provided, the substrate 110 has a functional layer 120 thereon, the functional layer 120 has a plurality of grooves 140 therein, and the functional layer 120 between adjacent grooves 140 defines an active area AA.
In this embodiment, after providing the substrate 110, the forming method further includes: a linear oxide layer 150 is formed on the sidewalls and bottom of the groove 140.
The substrate 110 is used to provide a process platform.
In this embodiment, the substrate 110 is made of monocrystalline silicon. In other embodiments of the present invention, the material of the substrate may also be selected from polysilicon or amorphous silicon; the substrate may also be selected from silicon, germanium, gallium arsenide, or silicon germanium compounds; the substrate may also be other semiconductor materials, or the substrate may also be selected to have an epitaxial layer or a silicon-on-epitaxial layer structure.
The functional layer 120 is used to form a semiconductor device, and a channel, a source terminal, and a drain terminal of the semiconductor device are located in the active area AA.
In this embodiment, the material of the functional layer 120 is the same as that of the substrate 110, and is also single crystal silicon. In other embodiments of the present invention, the material of the functional layer may also be different from the material of the substrate. The functional layer may be made of germanium, silicon carbide, gallium arsenide, indium gallium arsenide, or other materials.
It should be noted that, in this embodiment, the substrate 110 and the functional layer 120 are of an integral structure, that is, there is no distinct boundary between the substrate 110 and the functional layer 120. In other embodiments of the present invention, the functional layer and the substrate may also be different layers, i.e. there is a distinct boundary between the functional layer and the substrate.
The groove 140 is used to define the position and size of the active regions AA, so that different active regions AA are separated from each other, and thus, electrical isolation between different active regions AA is achieved.
In this embodiment, the groove 140 penetrates through the thickness of the functional layer 120, and the bottom of the groove 140 is exposed out of the substrate 110, that is, the groove 140 is defined by sidewalls of the active area AA on two sides of the groove 140 and a surface of the exposed substrate 110.
In this embodiment, a plurality of grooves 140 are formed in the functional layer 120, the plurality of grooves 140 are arranged in parallel along a first direction X, and the first direction X is parallel to the surface of the substrate 110; each of the grooves 140 extends along a second direction Y, which is parallel to the surface of the substrate 110 and perpendicular to the first direction X. The extending direction of the groove 140 is the second direction Y, and the first direction X is a direction perpendicular to the extending direction of the groove 140.
Specifically, the step of forming the groove 140 includes: forming a patterned isolation mask layer 130 on the functional layer 120, wherein the patterned isolation mask layer 130 exposes a part of the surface of the functional layer 120; and etching the functional layer 120 by using the patterned isolation mask layer 130 as a mask until the substrate 120 is exposed, so as to form the groove 140.
The isolation mask layer 130 is used to define the size and position of the active area AA, that is, to define the size and position of the recess 140, to protect the surface of the active area AA in a subsequent process, and to mark a stop position in a subsequent planarization process.
In this embodiment, the isolation mask layer 130 is made of silicon nitride. In other embodiments of the present invention, the isolation mask layer 130 may also be made of silicon oxynitride, silicon carbonitride, or other materials that are different from the functional layer 120 and can serve as an etching mask.
The step of forming the patterned isolation mask layer 130 includes: forming a mask material layer (not shown) on the functional layer 120; forming a pattern layer on the mask material layer, wherein the pattern layer exposes part of the surface of the mask material layer; and etching the mask material layer by taking the pattern layer as a mask until the functional layer 120 is exposed, so as to realize the patterning of the mask material layer and form a patterned isolation mask layer 132.
The pattern layer can be a patterned photoresist layer and can be formed by coating, exposing and developing; the graphic layer can also be other hard mask layers and can be formed by a multiple graphic mask process.
It should be noted that, in this embodiment, before forming the isolation mask layer 130, the step of forming the groove 140 further includes: an interfacial layer (not shown) is formed on the functional layer 120.
The interface layer is used to provide a good process surface for the formation of the patterned mask layer, and to improve the lattice mismatch between the isolation mask layer 130 and the functional layer 120.
In this embodiment, the interface layer is made of silicon oxide, and may be formed on the initial substrate surface by chemical vapor deposition, physical vapor deposition, atomic layer deposition, or furnace tube. The interface layer may be made of a material different from the substrate and suitable for improving the interface condition between the isolation mask layer and the substrate.
The linear oxide layer 150 is used for repairing damage formed on the sidewall and the bottom of the groove 140 in the process of etching the groove 140, that is, repairing damage on the exposed substrate 110 and the sidewall of the active area AA; the linear oxide layer 150 may be formed to round sharp corners of the substrate 110 and the surface of the active area AA, so as to reduce the occurrence of the point discharge phenomenon; moreover, the linear oxide layer 150 may also serve as a buffer layer between the subsequently formed film layer and the substrate 110 and the active area AA, so as to improve the problem of lattice mismatch.
The material of the linear oxide layer 150 is silicon oxide. In other embodiments of the present invention, the material of the linear oxide layer may be different from the substrate and the functional layer, and may be a material capable of implementing the function thereof.
As shown in fig. 4, in the present embodiment, the groove 140 is surrounded by sidewalls of the active regions located at two sides of the groove 140 and the surface of the substrate 110 exposed, so the linear oxide layer 150 is located on the sidewalls of the active regions AA located at two sides of the groove 140 and the substrate 110 exposed at the bottom of the groove 140.
In addition, the plurality of grooves 140 in the functional layer 120 are arranged in parallel along the first direction X, so that the linear oxide layer 150 is formed on the sidewalls of the active region opposite to each other along the first direction X.
It should be noted that, in this embodiment, the patterned isolation mask layer 130 is further formed on the functional layer 120, so that the linear oxide layer 150 is located on the top and the sidewall of the patterned isolation mask layer 130. In addition, the material of the interfacial layer between the isolation mask layer 130 and the functional layer 120 is also silicon oxide, so the linear oxide layer 150 is connected to the interfacial layer.
Referring to fig. 5, an etch stop layer 180 is formed, wherein the etch stop layer 180 is at least located on the sidewall of the groove 140 opposite to the vertical extending direction.
The etching stop layer 180 is used for protecting the isolation structure 160 between adjacent active regions AA during the subsequent epitaxial layer formation process, and preventing the isolation structure from being damaged by etching.
The groove 140 extends along the second direction Y, and the first direction X is a direction perpendicular to the extending direction of the groove 140, so that the etching stop layer 180 is at least located on the sidewall of the groove 140 opposite to the first direction X.
The etching stop layer 180 can protect the isolation structure and prevent the opening width from being increased in the subsequent epitaxial layer forming process, so that the thickness of the isolation structure between the subsequently formed adjacent epitaxial layers is maintained, the bridging problem caused by the undersize distance between the adjacent epitaxial layers is solved, and the manufacturing yield and the device performance of the formed semiconductor structure are improved.
In addition, as shown in fig. 5, in the present embodiment, the groove 140 penetrates through the functional region 120, and the bottom of the groove 140 exposes the substrate 110; the etch stop layer 180 is also located on the substrate 110 exposed at the bottom of the recess 140.
It should be noted that, in this embodiment, the isolation mask layer 130 is further formed on the functional layer 120; the etch stop layer 180 is also located on the top and sidewalls of the isolation mask layer 130. In addition, the linear oxide layer 150 is further formed on the bottom and the sidewall of the groove 140 and the top and the sidewall of the isolation mask layer 130, so the etch stop layer 180 is located on the surface of the linear oxide layer 150, which faces away from the functional layer 120 and the substrate 110.
In this embodiment, the density of the material of the etching stop layer 180 is greater than that of the material of the subsequently formed isolation structure. The material of the etching stop layer 180 is set to be a material with higher density, so that the etching stop function of the etching stop layer 180 can be effectively ensured, and an effective protection function can be achieved in the subsequent process.
Specifically, in this embodiment, the material of the etch stop layer 180 is silicon nitride. The silicon nitride has higher density, so the material of the etching stop layer 180 is set to be the silicon nitride, the protection effect of the etching stop layer 180 can be effectively ensured, the thickness of an isolation structure between adjacent epitaxial layers formed subsequently can be maintained, and the phenomenon of epitaxial layer bridging can be reduced. In other embodiments of the present invention, the material of the etching stop layer may also be other materials with higher density, which can effectively protect the formed isolation structure in the subsequent process.
In this embodiment, the etching stop layer 180 may be formed on the sidewall of the active area AA by atomic layer deposition or a furnace tube. The material film layer with higher density and better step coverage can be formed by the atomic layer deposition or furnace tube, so that the etching stop layer 180 is formed by the atomic layer deposition or furnace tube, the quality and the thickness uniformity of the etching stop layer 180 can be effectively improved, the device performance is favorably improved, and the difficulty of the subsequent process is favorably reduced.
In this embodiment, the thickness of the etching stop layer 180 is within
To
Within the range.
The thickness of the etch stop layer 180 is preferably neither too large nor too small. If the thickness of the etching stop layer 180 is too small, the etching stop effect of the etching stop layer 180 may be affected, the protection capability of the etching stop layer 180 on a subsequently formed isolation structure may be affected, and the improvement of the epitaxial layer bridging problem is not facilitated; if the thickness of the etching stop layer 180 is too large, the aspect ratio of the groove 140 after the etching stop layer 180 is formed may be increased, the process difficulty of subsequently filling the groove 140 with a dielectric material to form an isolation structure may be increased, the problems of material waste and process difficulty increase may be caused, and moreover, if the thickness of the etching stop layer 180 is too large, unnecessary stress may be introduced into the active area AA, and adverse effects may be caused on the electrical properties of the active area AA.
Referring to fig. 5 and 6, an isolation structure 160 (shown in fig. 6) is formed in the recess 140 having the etch stop layer 180 formed on the sidewalls thereof.
The isolation structure 160 is located in the functional layer 120, fills the groove 140, is disposed between the adjacent active regions AA, and is configured to define the active regions AA and achieve electrical isolation between the adjacent active regions AA.
In this embodiment, the plurality of grooves 140 are arranged in parallel along a first direction X, each groove 140 extends along the second direction Y, and the first direction X is perpendicular to the extending direction of the groove 140, so that the plurality of isolation structures 160 are arranged in parallel along the first direction X, and each isolation structure 160 extends along the second direction Y.
The etch stop layer 180 is at least located on the sidewall of the groove 140 opposite to the vertical extension direction. Specifically, as shown in fig. 6, along the first direction X, the etch stop layer 180 is at least located between the isolation structure 160 and the active area AA.
In this embodiment, the isolation structure 160 is made of silicon oxide. The material of the etch stop layer 180 is silicon nitride. The density of the material of the etching stop layer 180 is greater than the density of the material of the isolation structure 160, so that the etching stop layer 180 can play a role in protecting the isolation structure 160 in the subsequent process, prevent the isolation structure 160 from being damaged, maintain the thickness of the isolation structure 160 between the adjacent epitaxial layers formed subsequently, and reduce the occurrence of the epitaxial layer bridging phenomenon.
In other embodiments of the present invention, the material of the isolation structure may also be one or more of silicon nitride, silicon oxynitride, low-K dielectric material (dielectric constant greater than or equal to 2.5 and less than 3.9), or ultra-low-K dielectric material (dielectric constant less than 2.5).
Specifically, the step of forming the isolation structure 160 includes: as shown in fig. 5, a dielectric material 161 is filled into the groove 140 having the etching stop layer 180 formed on the sidewall and the bottom, and the top of the dielectric material 161 is higher than the top of the active area AA; as shown in fig. 6, the dielectric material 161 (shown in fig. 5) is planarized to form an isolation structure 160 having a top level with the top of the active area AA.
In this embodiment, the dielectric material 161 is filled by a High Aspect Ratio Process (HARP) to fill the recess 140 with the dielectric material 160, so as to avoid forming a void in the dielectric material 161 and improve the insulating performance of the isolation structure 160.
The planarization process is used to remove the dielectric material 160 above the top of the active area AA, so that the isolation structure 150 is formed flush with the top of the active area AA. Specifically, the planarization treatment may be performed by means of chemical mechanical polishing.
It should be noted that, in this embodiment, the isolation mask layer 130 is further formed on the functional layer 120 (as shown in fig. 5), so that the planarization process not only removes the dielectric material 160 on the top of the active area AA, but also removes the isolation mask layer 130 until the top of the active area AA is exposed.
After forming the isolation structure 160, the forming method further includes: as shown in fig. 7, an opening 170 is formed in the active area AA, and at least a portion of a sidewall of the opening 170 exposes the etch stop layer 180; as shown in fig. 8, an epitaxial layer 190 filling the opening 170 is formed in the opening 170 with the sidewall of the etch stop layer 180 exposed.
The opening 170 is used to provide a process space for the formation of a subsequent epitaxial layer.
The step of forming the opening 170 in the active area AA includes: etching the active area AA to form the opening 170 in the active area AA; the bottom and the side walls of the opening 170 are subjected to a cleaning process.
In this embodiment, the opening 170 is formed in the active area AA by a combination of dry etching and wet etching. Specifically, the active region AA is used for forming a PMOS transistor, so a tetramethylammonium hydroxide (TMAH) solution is used for etching in the wet etching process to form the Σ -shaped opening 170.
In this embodiment, after forming the opening 170 in the active area AA and before forming the epitaxial layer 190, the method further includes: the bottom and the side walls of the opening 170 are subjected to a cleaning process.
The cleaning process is used to remove impurities on the sidewalls and bottom of the formed opening 170, thereby providing a highly clean process surface for subsequent epitaxial layer formation.
Specifically, the etching rate of the cleaning process to the etch stop layer 180 is less than the etching rate of the cleaning process to the isolation structure 160. Therefore, during the cleaning process, the etching stop layer 180 exposed on the sidewall of the opening 170 can effectively protect the isolation structure 160, prevent the isolation structure 160 from being corroded by the cleaning process, and reduce the widening of the opening 170, thereby ensuring the thickness of the isolation structure 160 between adjacent openings 170.
In this embodiment, the bottom and the sidewall of the opening 170 are cleaned by hydrofluoric acid. The hydrofluoric acid can effectively remove impurities on the bottom and the side wall of the opening 170, so that the surface cleanliness of the bottom and the side wall of the opening 170 is improved; furthermore, the etching rate of hydrofluoric acid to the etching stop layer 180 made of silicon nitride is relatively low, so that the etching stop layer 180 can effectively protect the isolation structure 160 and prevent the opening 170 from widening.
It should be noted that, since hydrofluoric acid etches the linear oxide layer 150 made of silicon oxide, the linear oxide layer 150 exposed on the sidewall of the opening 170 is removed during the cleaning process, so as to expose the etch stop layer 180; the etching rate of the etching stop layer 180 by the cleaning process is relatively low, so that the exposed etching stop layer 180 can effectively prevent the isolation structure 160 from being exposed and etched, and the phenomenon of widening of the opening 170 can be effectively reduced.
Referring to fig. 8, after the opening 170 is formed, a semiconductor material is filled into the opening 170 (shown in fig. 7), and an epitaxial layer 190 is formed in the opening 170.
The epitaxial layer 190 is used for applying stress to the channel region and serves as a source-drain doped region of the semiconductor structure. Specifically, in this embodiment, the opening 170 is filled with a semiconductor material by epitaxial growth to form the epitaxial layer 190.
Since the etching stop layer 180 is exposed on the sidewall of the opening 170, the width of the opening 170 is maintained, the problem that the width of the opening 170 is increased does not occur, the distance between adjacent openings 170 is large, and the thickness of the isolation structure 160 between adjacent openings 170 is large, so the distance D between adjacent epitaxial layers 190 is large, the probability that the problem of bridging occurs between adjacent epitaxial layers 190 is small, and the manufacturing yield and the device performance of the formed semiconductor structure can be effectively improved.
In this embodiment, the active area AA is used to form a PMOS transistor, the opening is "sigma" shaped, so the material of the epitaxial layer 190 is silicon germanium, and the epitaxial layer 190 fills the opening 170 of the "sigma" shape to apply a greater compressive stress to the channel region.
Correspondingly, the invention also provides a semiconductor structure.
Referring to fig. 8, a cross-sectional structure diagram of an embodiment of a semiconductor structure of the invention is shown.
The semiconductor structure includes: a substrate 110; a functional layer 120, said functional layer 120 being located on said substrate 110; isolation structures 160, wherein the isolation structures 160 are located in the functional layer 120, and an active area AA is defined in the functional layer 120 between adjacent isolation structures 160; an etch stop layer 180, wherein the etch stop layer 180 is at least located on a sidewall of the isolation structure 160 facing the active area AA.
In this embodiment, the semiconductor structure is formed by the semiconductor structure forming method of the present invention, and the specific technical solution of the semiconductor structure refers to the semiconductor structure forming method.
In this embodiment, the semiconductor structure further includes: an epitaxial layer 190, the epitaxial layer 190 being located within the active area AA; the etch stop layer 180 is located between the isolation structure 160 and the epitaxial layer 190 and extends between the isolation structure 160 and the active area AA.
The etching stop layer 180 is used for protecting the isolation structure 160 between the adjacent active regions AA during the epitaxial layer 190 process, and preventing the opening width from increasing, so as to increase the thickness of the isolation structure 160 between the adjacent epitaxial layers 190, improve the bridging problem caused by the over-small distance between the adjacent epitaxial layers 190, and further improve the manufacturing yield and the device performance of the semiconductor structure.
The substrate 110 is used to provide a process platform.
In this embodiment, the substrate 110 is made of monocrystalline silicon. In other embodiments of the present invention, the material of the substrate may also be selected from polysilicon or amorphous silicon; the substrate may also be selected from silicon, germanium, gallium arsenide, or silicon germanium compounds; the substrate may also be other semiconductor materials, or the substrate may also be selected to have an epitaxial layer or a silicon-on-epitaxial layer structure.
The functional layer 120 is used to form a semiconductor device, and a channel, a source terminal, and a drain terminal of the semiconductor device are located in the active area AA.
In this embodiment, the material of the functional layer 120 is the same as that of the substrate 110, and is also single crystal silicon. In other embodiments of the present invention, the material of the functional layer may also be different from the material of the substrate. The functional layer may be made of germanium, silicon carbide, gallium arsenide, indium gallium arsenide, or other materials.
It should be noted that, in this embodiment, the substrate 110 and the functional layer 120 are of an integral structure, that is, there is no distinct boundary between the substrate 110 and the functional layer 120. In other embodiments of the present invention, the functional layer and the substrate may also be different layers, i.e. there is a distinct boundary between the functional layer and the substrate.
The isolation structure 160 is located in the functional layer 120, disposed between adjacent active regions AA, and configured to define the active regions AA and achieve electrical isolation between the adjacent active regions AA.
The functional layer 120 has a plurality of the isolation structures 160 therein, the plurality of isolation structures 160 are arranged in parallel along the first direction X, and each of the isolation structures 160 extends along the second direction Y. Therefore, the active areas AA and the isolation structures 160 are arranged in parallel along the first direction X, and each active area AA and each isolation structure 160 extend along the second direction Y.
In this embodiment, the isolation structure 160 is made of silicon oxide. In other embodiments of the present invention, the material of the isolation structure may also be one or more of silicon nitride, silicon oxynitride, low-K dielectric material (dielectric constant greater than or equal to 2.5 and less than 3.9), or ultra-low-K dielectric material (dielectric constant less than 2.5).
The etch stop layer 180 is used to protect the isolation structures 160 between adjacent active areas AA during the formation of the epitaxial layer 190, and prevent the loss of the isolation structures.
The etch stop layer 180 is located on a sidewall of the isolation structure 160 facing the active area AA, and the active area AA and each isolation structure 160 extend along the second direction Y, so the etch stop layer 180 is located on a sidewall of the active area AA opposite to the isolation structure 160 along the second direction Y.
In this embodiment, the epitaxial layer 190 is further disposed on the active area AA, so the etch stop layer 180 is located between the isolation structure 160 and the epitaxial layer 190 and extends to between the isolation structure 160 and the active area AA.
Therefore, the etch stop layer 180 can protect the isolation structure 160 during the formation of the epitaxial layer 190, and prevent the opening width from becoming large, so as to maintain the thickness of the isolation structure 160 between adjacent epitaxial layers 190, improve the bridging problem caused by the over-small distance between adjacent epitaxial layers 190, and further improve the manufacturing yield and device performance of the semiconductor structure.
In addition, as shown in fig. 8, in the present embodiment, the active regions AA are separately disposed, and the isolation structure 160 penetrates through the functional layer 120; the etch stop layer 180 is also located between the isolation structure 160 and the substrate 110.
In this embodiment, the density of the material of the etching stop layer 180 is greater than that of the functional layer 120 of the active area AA. The material of the etching stop layer 180 is set to be a material with higher density, so that the etching stop function of the etching stop layer 180 can be effectively ensured, and the protection function can be effectively realized.
Specifically, the functional layer 120 is made of silicon, that is, the functional layer 120 of the active area AA is made of silicon, and the etch stop layer 180 is made of silicon nitride. In other embodiments of the present invention, the material of the etching stop layer may also be other materials with higher density, which can effectively protect the isolation structure 160 in the subsequent process.
In this embodiment, the thickness of the etching stop layer 180 is within
To
Within the range.
The thickness of the etch stop layer 180 is preferably neither too large nor too small. If the thickness of the etching stop layer 180 is too small, the etching stop effect of the etching stop layer 180 may be affected, the protection capability of the etching stop layer 180 on the isolation structure 160 may be affected, and the improvement of the epitaxial layer bridging problem is not facilitated; if the thickness of the etching stop layer 180 is too large, the difficulty of the formation process of the isolation structure 160 may be increased, which may cause material waste and increase process difficulty, and further, if the thickness of the etching stop layer 180 is too large, unnecessary stress may be introduced into the active area AA, which may adversely affect the electrical performance of the active area AA.
In this embodiment, the semiconductor structure further includes: a linear oxide layer 150, wherein the linear oxide layer 150 is located between the active area AA and the isolation structure 160.
The linear oxide layer 150 is used for repairing damages suffered by the substrate 110 and the active area AA in the process of forming the isolation structure 160, and rounding sharp corners on the surfaces of the substrate 110 and the active area AA to reduce the occurrence of a point discharge phenomenon; moreover, the linear oxide layer 150 may also serve as a buffer layer between the etch stop layer 180 and the substrate 110 and the active area AA to improve lattice mismatch.
The material of the linear oxide layer 150 is silicon oxide. In other embodiments of the present invention, the material of the linear oxide layer may be different from the substrate and the functional layer, and may be a material capable of implementing the function thereof.
The epitaxial layer 190 is used for applying stress to the channel region and serves as a source-drain doped region of the semiconductor structure.
An etching stop layer 180 is arranged between the epitaxial layer 190 and the isolation structure 160, the etching stop layer 180 is exposed from the side wall of an opening formed in the process of forming the epitaxial layer 190, the isolation structure 160 is not corroded, so that the width of the opening is maintained, the problem that the width of the opening is increased is solved, the distance between adjacent openings is large, the thickness of the isolation structure between adjacent openings is large, the distance D between adjacent epitaxial layers 190 is large, the probability that the problem of bridging occurs between adjacent epitaxial layers 190 is small, and the manufacturing yield and the device performance of the formed semiconductor structure can be effectively improved.
In this embodiment, the active area AA is used to form a PMOS transistor, the opening is shaped like a "sigma", so the material of the epitaxial layer 190 is silicon germanium, and the epitaxial layer 190 fills the opening to apply a larger compressive stress to the channel region.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (15)
1. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein a functional layer is arranged on the substrate, a plurality of grooves are formed in the functional layer, and the functional layer between every two adjacent grooves is defined as an active area;
forming an etching stop layer, wherein the etching stop layer is at least positioned on the side wall which is arranged opposite to the vertical extending direction of the groove;
forming an isolation structure in the groove with the etching stop layer formed on the side wall;
after the isolation structure is formed, forming an opening in the active region under the protection of the etching stop layer, wherein at least part of the side wall of the opening exposes the etching stop layer;
and forming an epitaxial layer filled in the opening with the side wall exposed out of the etching stop layer.
2. The forming method according to claim 1, wherein the groove penetrates through the functional layer, and a bottom of the groove exposes the substrate;
the etching stop layer also extends to the substrate exposed at the bottom of the groove.
3. The method of claim 1, wherein a density of the etch stop layer material is greater than a density of the isolation structure material.
4. The method according to claim 1 or 3, wherein the etch stop layer is made of silicon nitride, and the isolation structure is made of silicon oxide.
5. The method of claim 1, wherein the etch stop layer has a thickness of
To
Within the range.
6. The method of claim 1, wherein the etch stop layer is formed by atomic layer deposition or furnace.
7. The method of forming as claimed in claim 1, wherein after providing the substrate and before forming the etch stop layer, further comprising: forming linear oxide layers on the side wall and the bottom of the groove;
the etching stop layer is positioned on the linear oxidation layer.
8. The method of forming of claim 1, wherein after forming the opening in the active region and before forming the epitaxial layer, further comprising: and cleaning the bottom and the side wall of the opening.
9. The method of forming of claim 8, wherein an etch rate of the etch stop layer by the cleaning process is less than an etch rate of the isolation structure by the cleaning process.
10. The method of claim 8, wherein a cleaning process is performed on a bottom and a sidewall of the opening by hydrofluoric acid.
11. A semiconductor structure, comprising:
a substrate;
a functional layer on the substrate;
the isolation structures are positioned in the functional layers, and the functional layers between the adjacent isolation structures are defined as active regions;
the etching stop layer is at least positioned on the side wall of the isolation structure facing the active region;
the epitaxial layer is positioned in the active region, and the etching stop layer is positioned between the isolation structure and the epitaxial layer and extends to a position between the isolation structure and the active region.
12. The semiconductor structure of claim 11, wherein a density of the etch stop layer is greater than a density of the isolation structure.
13. The semiconductor structure of claim 11 or 12, wherein the etch stop layer is made of silicon nitride and the isolation structure is made of silicon oxide.
14. The semiconductor structure of claim 11, wherein the etch stop layer is at a thickness of
To
Within the range.
15. The semiconductor structure of claim 11, wherein the isolation structure extends through the functional layer; the etch stop layer is also located between the isolation structure and the substrate.
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| KR20160035650A (en) * | 2014-09-23 | 2016-04-01 | 삼성전자주식회사 | Semiconductor device and method of manufacturing the same |
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| KR100652419B1 (en) * | 2005-07-28 | 2006-12-01 | 삼성전자주식회사 | Method for manufacturing gate of fin type transistor |
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| EP0614230A2 (en) * | 1993-03-05 | 1994-09-07 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device with recessed gate and production method thereof |
| CN101197287A (en) * | 2006-12-05 | 2008-06-11 | 中芯国际集成电路制造(上海)有限公司 | Production method of high voltage MOS transistor |
| TW201115737A (en) * | 2009-10-28 | 2011-05-01 | Alpha & Omega Semiconductor | Power MOSFET device with an added tungsten spacer in its contact hole and the manufacturing method |
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